JP2018200570A - Bus monitor and bus monitoring method - Google Patents

Abstract

To make accuracy improvement of information obtained by statistical processing and suppression of memory cost compatible.SOLUTION: A bus monitor includes an observation means for observing a transfer event of a bus, a statistical means for statistically processing the transfer event every statistical processing period, a holding means for holding a statistical processing result, and a changing means for changing the statistical processing period according to the observed transfer event or a result of the statistical processing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a bus monitor and a bus monitoring method.

  There is a technique in which a monitor device is used to observe a CPU (central processing unit) or system bus signal in a semiconductor integrated circuit to acquire necessary information and perform analysis using the information. In recent years, the degree of integration has been improved in semiconductor integrated circuits, and many master modules such as DMAC (Direct Memory Access Controller) and CPU have been mounted on semiconductor integrated circuits. In such a system, since many master modules issue transfers on the system bus, the operation on the system bus becomes complicated.

  Therefore, a bus monitor is mounted on the system, and various state analyzes have been performed using the bus monitor in the product development process. The bus monitor is a device that observes bus transfer events. The bus transfer events to be observed include bus transfer ID information, address information, data size, write data, read data, and the like. In some cases, bus transfer events are sequentially stored as information, or statistical processing is performed every predetermined period from a bus transfer event, and the results of the statistical processing are stored. The information acquired by the bus monitor in this way is used for failure analysis and performance analysis in the product development process.

  When used for performance analysis such as bus bandwidth, it is common to obtain the result of statistical processing of bus transfer events. At this time, by shortening the statistical processing period, the state of the bus can be analyzed with higher accuracy. Patent Literature 1 discloses a bus monitor device that enables performance analysis with high accuracy by allowing a statistical processing period to be specified in units of clocks.

JP 2009-205334 A

  The shorter the period for performing statistical processing, the higher the accuracy of the information obtained, but at the same time the amount of information increases. Therefore, considering that the memory capacity is finite, the technique described in Patent Document 1 is limited in improving the accuracy of information.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a bus monitor technique capable of achieving both improvement in accuracy of information obtained by statistical processing and reduction in memory cost.

  One embodiment of the present invention relates to a bus monitor. This bus monitor includes observation means for observing bus transfer events, statistical means for performing statistical processing of transfer events for each statistical processing period, holding means for holding statistical processing results, and observed transfer events or statistical processing. And changing means for changing the statistical processing period according to the result.

  According to the present invention, it is possible to achieve both improvement in accuracy of information obtained by statistical processing and reduction in memory cost.

The schematic diagram of the bus system which concerns on embodiment. 2A to 2C are graphs showing an example of time transition of the bus bandwidth. It is a schematic diagram which shows an example of the competition of the bus use period in the bus system of FIG. 4A and 4B are schematic views showing a first comparative example in which the statistical processing period is changed by software. FIGS. 5A and 5B are schematic diagrams illustrating a second comparative example in which the statistical processing period is changed by software. 6A and 6B are schematic diagrams illustrating an example in which the statistical processing period is changed by the bus monitor according to the embodiment. It is a block diagram which shows the structure of the bus monitor of FIG. It is a flowchart which shows the flow of a series of processes in the determination part of FIG. It is a flowchart which shows the flow of a series of processes in the determination part of FIG. It is a flowchart which shows the flow of a series of processes in the observation and statistics part of FIG. 3 is a timing chart showing the operation of the bus monitor of FIG. 1. 12A to 12C are block diagrams illustrating a partial configuration of a bus monitor according to a modification. It is a flowchart which shows the flow of a series of processes in the determination part of FIG.12 (c). It is a flowchart which shows the flow of a series of processes in the determination part of FIG.12 (c). It is a timing chart which shows operation | movement of the bus monitor which concerns on a 3rd modification.

  Hereinafter, the same or equivalent components, members, processes, and signals shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. In addition, in the drawings, some of the members that are not important for explanation are omitted.

(Embodiment)
FIG. 1 is a schematic diagram of a bus system 20 according to an embodiment. The bus system 20 employs a bus topology. The bus system 20 includes a master module A4, a master module B6, a master module C8, a master module D10, a slave module A12, and a bus monitor 14, each of which is connected to the system bus 2. The bus monitor 14 observes (or monitors) signals transferred via the system bus 2 and performs statistical processing. The bus monitor 14 stores the result of the statistical processing in the memory, that is, the SRAM 16. The result of the statistical processing held in the SRAM 16 is output to an external device and used for checking the operation of the bus system 20 and analyzing the performance.

  In order to perform performance analysis with high accuracy, it is desirable to obtain the necessary statistical processing results in detail. The result of statistical processing is generally stored in a memory. In order to perform statistical processing every short period and keep the result, a relatively large memory is required. However, increasing the memory capacity increases the cost. Therefore, the bus monitor 14 according to the present embodiment acquires a statistical processing result by setting only a desired period of the statistical processing period to be short in order to obtain a highly accurate measurement result with a limited memory capacity. To do.

  FIG. 2A is a graph showing an example of time transition of the bus bandwidth. A failure is likely to occur at a location where the bus bandwidth fluctuates greatly during a specific short period, such as a location indicated by reference numeral 32 in the figure. In order to grasp the cause of the failure, it is desirable to be able to analyze in detail the fluctuation range and transition state of the bus bandwidth. Therefore, at locations where large fluctuations in the bus bandwidth are expected, it is required to perform statistical processing every short period and obtain the results. FIG. 2B is a graph showing an example when the statistics of the bus bandwidth are acquired for each fixed length period. FIG.2 (c) is a graph which shows an example at the time of changing a period short only by the location which fluctuates greatly, and acquiring a statistic. When used for performance analysis, it is desirable to be able to obtain statistics as shown in FIG.

  In the present embodiment, the bus monitor 14 is provided with a function for changing the length of a period during which statistical processing is performed in order to obtain a result of statistical processing (for example, a statistic) as shown in FIG. Implement with. On the other hand, it is also conceivable to change the period for performing the statistical processing by external software. In this case, since the software can be changed more easily than the hardware, versatility is enhanced. However, in the implementation by software, for example, it waits until receiving an interrupt event notifying that the bus operation of a specific master module has started, and the period is changed after receiving the event, so a time lag occurs. Also, when there is no interrupt event, it may be necessary to try again and again by trial and error.

  Hereinafter, the comparative example 1 and the comparative example 2 corresponding to the case of mounting by software and the present embodiment mounted by hardware will be compared.

  FIG. 3 is a schematic diagram showing an example of competition between bus use periods in the bus system 20 of FIG. A location indicated by reference numeral 22 corresponds to a location where a steady transfer is issued or a location where the transfer amount is relatively small. In such a place, a failure is relatively unlikely. Therefore, if a unit period for statistical processing (hereinafter referred to as a statistical processing period) is set to be relatively long, the amount of memory used can be suppressed. On the other hand, at a location indicated by reference numeral 24, bus rights compete among a relatively large number of master modules. In such places, failures are relatively likely. If a long statistical processing period is used in such a place, it becomes difficult to analyze what is happening from the statistical information when a failure occurs. Therefore, if the statistical processing period is set relatively short in such a place, detailed failure analysis from the statistical information becomes possible. The bus monitor 14 according to the present embodiment enables detailed analysis by acquiring the statistical information of the portion indicated by reference numeral 26 every short period, and lengthens the statistical processing period in other portions. To reduce memory usage.

  4A and 4B are schematic views showing a first comparative example in which the statistical processing period is changed by software. The operation of each master module shown in FIG. 4A corresponds to that of FIG. In section 1, section 2, and section 3 where failure is unlikely to occur, the statistical processing period is set long by software, and statistical information is acquired at a high compression rate. At the location indicated by reference numeral 28, the bus monitor detects the transaction ID of the master module D10. The detection of the transaction ID of the master module D10 is transmitted to the CPU, and the statistical processing periods of the sections 5, 6, and 7 are changed by software. Here, since a period in which software intervenes occurs, a time lag occurs until the statistical processing period is changed. In this example, the change of the statistical processing period is not applied to the section 4 (or is not in time). Therefore, there may be a case where information of a portion that is desired to be seen in detail (a portion indicated by reference numeral 24 in this example) cannot be acquired every short period. FIG. 4B is a schematic diagram showing a log storage state in the SRAM. If the information amount of one section is 16 bytes, the total amount of information acquired in the eight sections shown in FIG. 4A is 16 × 8 = 128 bytes. The acquisition logs of section 5, section 6, and section 7 are high-resolution information, but do not correspond to the part that is desired to be seen in detail (the part indicated by reference numeral 24 in this example).

  FIGS. 5A and 5B are schematic diagrams illustrating a second comparative example in which the statistical processing period is changed by software. The operation of each master module shown in FIG. 5A corresponds to that in FIG. In section 1 and section 2 where failure is unlikely to occur, the statistical processing period is set long by software, and statistical information is acquired at a high compression rate. In section 3 to section 16 indicated by reference numeral 30, the statistical processing period is changed by software before the master module D10 issues a transfer. In this case, information on a portion that is desired to be seen in detail (location indicated by reference numeral 24 in this example) can be acquired every short period, but the total number of such periods is relatively large, and the memory cost is deteriorated. FIG. 5B is a schematic diagram showing a log storage state in the SRAM. If the information amount of one section is 16 bytes, the total amount of information acquired in the 17 sections shown in FIG. 5A is 16 × 17 = 272 bytes. The acquisition logs in the sections 3 to 16 are high-resolution information, and correspond to a portion to be viewed in detail (a portion indicated by reference numeral 24 in this example).

  6A and 6B are schematic diagrams illustrating an example in which the statistical processing period is changed by the bus monitor 14 according to the present embodiment. The operation of each master module shown in FIG. 6A corresponds to that of FIG. The bus monitor 14 sets the statistical processing period longer in the sections 1, 2, and 3 where failure is unlikely to occur, and acquires statistical information at a high compression rate. At a location indicated by reference numeral 28, the bus monitor 14 detects the transaction ID of the master module D10 and changes the length of the statistical processing period. Since there is no software intervention, the time lag is suppressed, and this change is reflected in the next section 4. As described above, information is acquired at short intervals so that detailed analysis can be performed at a location where a bus right conflict occurs between many master modules and a failure is likely to occur. For the sections 7 and 8 after the completion of the transaction of the master module D10, the bus monitor 14 restores the length of the statistical processing period. FIG. 6B is a schematic diagram showing a log storage state in the SRAM 16. If the information amount of one section is 16 bytes, the total amount of information acquired in the eight sections shown in FIG. 6A is 16 × 8 = 128 bytes. The acquisition logs of the section 4, the section 5, and the section 6 are high-resolution information, and correspond to locations that are desired to be viewed in detail (locations indicated by reference numeral 24 in this example).

  FIG. 7 is a block diagram showing the configuration of the bus monitor 14 according to the present embodiment. The bus monitor 14 observes the transfer event of the target system bus 2, performs statistical processing of the transfer event for each statistical processing period, and holds and outputs the result. The statistical processing includes, for example, processing for measuring a data transfer amount from a transfer event of the system bus 2 and calculating a cumulative value of the data transfer amount for each statistical processing period. In this case, a cumulative value for each statistical processing period is output as a result of the statistical processing. The bus monitor 14 includes a determination unit 101, a determination unit 102, an observation / statistical unit 103, a holding unit 104, and an SRAM 16. The observation / statistical unit 103 and the system bus 2 are connected by an observation bus signal data transfer interface. The SRAM 16 and the external device 109 are connected by a data transfer interface between the bus monitor and the external device.

  The determination unit 102 determines the length of the statistical processing period used in the statistical processing by the observation / statistical unit 103. For example, the determination unit 102 specifies a statistical processing period. The determination unit 102 changes the statistical processing period based on the determination result in the determination unit 101. The determination unit 102 includes a setting register 106 for setting the length of the statistical processing period and a change register 107 for setting the degree of change of the length of the statistical processing period. The determination unit 102 changes the length of the statistical processing period by changing the setting value of the setting register 106 using the setting value of the change register 107 based on the determination result in the determination unit 101. The change in the length of the statistical processing period will be described later.

  The observation / statistical unit 103 observes the transfer event of the system bus 2 and generates information necessary for analyzing the state. The observation / statistical unit 103 performs statistical processing of the transfer event for each statistical processing period based on the designation by the determining unit 102, and generates a result of the statistical processing and time information. The time information is, for example, the time when the result of statistical processing is generated or the time stamp thereof.

  The holding unit 104 holds determination information that is referred to when the determination unit 101 determines whether or not the statistical processing period needs to be changed. The determination information is information that is the basis of the determination. The determination information includes, for example, a bus transfer transaction ID and address, or a threshold value of the acquired statistical processing result. In the present embodiment, the holding unit 104 includes a reference register 108 for detecting a transaction ID of a specific bus transfer. The reference register 108 holds a transaction ID of a specific bus transfer as determination information.

  The SRAM 16 holds the result of statistical processing generated by the observation / statistical unit 103 and time information in association with each other. The SRAM 16 transfers the statistical processing result and time information held to the external device 109.

  The determination unit 101 determines whether or not the statistical processing period needs to be changed based on the determination information held by the reference register 108 of the holding unit 104 and the ID information observed by the observation / statistical unit 103. The method of determining whether or not the change is necessary in the determination unit 101 includes a method of determining that the change is necessary when the observed ID information matches the ID information held in the reference register 108. The determination method may include a method of preparing a plurality of detection registers and determining that a change is necessary when the observed ID information is within a specified range.

  In this embodiment, the case where ID information is used as determination information will be described. However, in another embodiment, an address may be used as determination information. In this case, whether or not the change is necessary is determined based on whether or not the observed bus transfer address is in an address space designated by a register or the like. Or it is good also considering the threshold value with respect to the result of a statistical process as determination information. In this case, whether or not the change is necessary is determined based on the magnitude relationship between the acquired statistical processing result and the threshold value specified by the register or the like.

The operation of the bus monitor 14 having the above configuration will be described.
The bus monitor 14 observes the transfer event of the system bus 2, performs statistical processing of the transfer event every statistical processing period, and acquires the result of the statistical processing. In this, the bus monitor 14 changes the length of the statistical processing period. FIG. 8 is a flowchart showing a flow of a series of processes in the determination unit 102 of FIG. In S <b> 11, an external controller, for example, a CPU (not shown) sets the value of the setting register 106 and the value of the change register 107 of the determination unit 102. The setting value is specified by the number of clock cycles. In S <b> 12, the determination unit 102 issues a set value update flag to the observation / statistical unit 103. In S13, the determination unit 102 checks whether or not a minus change flag, which is a flag for changing the set value of the statistical processing period to a smaller value, is set. If the flag is not set, the process proceeds to S14. If the flag is set, the process proceeds to S15. The logic of the minus change flag will be described later. In S14, the determination unit 102 checks whether or not a plus change flag that is a flag for changing the set value of the statistical processing period to a larger value is set. If the flag is not set, the process proceeds to S22. If the flag is set, the process proceeds to S18. The logic of the plus change flag will be described later. In S22, the determination unit 102 determines whether or not the measurement is finished. If the measurement has not ended, the process proceeds to S13 again. If the measurement has ended, the operation ends here.

  Therefore, when neither the minus change flag nor the plus change flag is raised during measurement, the transition from S13 to S14 to S22 is repeated. When the minus change flag is set, the process proceeds from S13 to S15. In S15, the determination unit 102 changes (or updates or resets) the setting value of the setting register 106 to a value obtained by subtracting the setting value of the change register 107 from the current setting value. In S <b> 16, the determination unit 102 issues a set value update flag to the observation / statistical unit 103. In S <b> 17, the determination unit 102 issues a change notification flag for notifying the determination unit 101 that the set value of the statistical processing period has been changed to a small value. In S21, the determination unit 102 clears the minus change flag, and the process returns to S13. Similarly, when the plus change flag is set in S14, the process proceeds from S14 to S18. In S18, the determination unit 102 changes the setting value of the setting register 106 to a value obtained by adding the setting value of the change register 107 to the current setting value. In S <b> 19, the determination unit 102 issues a set value update flag to the observation / statistical unit 103. In S20, the determination unit 102 clears the change notification flag in order to notify the determination unit 101 that the set value of the statistical processing period has been returned to the initial value. In S21, the determination unit 102 clears the plus change flag, and the process returns to S13.

  In the present embodiment, a plurality of registers (for example, a setting register 106 and a change register 107) each holding information regarding the length of the statistical processing period are prepared, and the statistical processing after the change is performed by calculating those values. Although the length of a period is determined, it is not restricted to this. In another embodiment, a function of holding a plurality of pieces of information related to the length of the statistical processing period may be prepared and used by switching them.

  FIG. 9 is a flowchart showing a flow of a series of processes in the determination unit 101 of FIG. In the present embodiment, the statistical processing period is made relatively short when a transfer related to a specific transaction ID occurs. In S31, the determination unit 101 determines whether or not a time corresponding to one statistical processing period has elapsed. For example, when receiving the arrival flag indicating the expiration of the statistical processing period from the observation / statistical unit 103, the determination unit 101 determines that one statistical processing period has elapsed. If it has not elapsed, S31 is repeated until it has elapsed. When it determines with having passed, it changes to S32. In S32, the ID information received by the determination unit 101 from the observation / statistical unit 103 becomes valid when a pulse control signal indicating the establishment timing of a transaction having the ID is activated. The determination unit 101 determines whether a transaction having a specific transaction ID is detected by comparing the valid ID information with the ID information held in the reference register 108. If not detected, the process proceeds to S33. If detected, the process proceeds to S34. In S <b> 33, the determination unit 101 determines whether the change notification flag received from the determination unit 102 is set. If the flag is not set, the process proceeds to S37. If the flag is set, the process proceeds to S36. In S37, the determination unit 101 determines whether the measurement is finished. If the measurement has not ended, the process proceeds to S31 again. If the measurement has ended, the operation ends here.

  Therefore, when no transaction having a specific transaction ID is detected during the measurement, the transition from S31 to S32 and S33 to S37 is repeated. When a transaction having a specific transaction ID is detected, the process proceeds from S32 to S34. In S <b> 34, the determination unit 101 determines whether the change notification flag received from the determination unit 102 is set. If the flag is not set, the length of the statistical processing period remains the set value held in the setting register 106, and the process proceeds to S35. In S35, the determination unit 101 issues a minus change flag to the determination unit 102, and the process returns to S31. If the flag is set, the statistical processing period has already been changed to a small value, and the process returns to S31 without doing anything. If a transaction with a specific transaction ID that was detected in the previous statistical processing period is no longer detected in the next statistical processing period, the length of the statistical processing period has been changed once, and the change notification flag is set Therefore, the process proceeds from S33 to S36. In S36, the determination unit 101 issues a plus change flag to the determination unit 102, and the process returns to S31.

  FIG. 10 is a flowchart showing a flow of a series of processes in the observation / statistical unit 103 of FIG. In S <b> 41, the observation / statistical unit 103 determines whether the set value update flag received from the determination unit 102 is set. If the flag is not set, the observation / statistical unit 103 waits until the flag is set. When the flag is set, the process proceeds to S42. In S <b> 42, the observation / statistical unit 103 reflects the set value of the setting register 106 on the internal signal of the observation / statistical unit 103. The internal signal is a signal that holds the number of clock cycles in the statistical processing period. In S43, the observation / statistical unit 103 clears the set value update flag. In S <b> 44, the observation / statistical unit 103 determines whether a measurement start trigger has been received from the outside of the bus monitor 14. When it is received, the process proceeds to S45 and measurement is started. If not received, the observation / statistical unit 103 waits in S44 until it is received. In S46, the observation / statistical unit 103 determines whether or not a time corresponding to one statistical processing period has elapsed. If not, the observation / statistical unit 103 stands by in S46 until it has passed. If it has elapsed, the process proceeds to S47. In S 47, the observation / statistical unit 103 generates a predetermined statistical processing result and time information from the observed transfer event, and outputs the result to the SRAM 16. In S48, the observation / statistical unit 103 determines whether or not a measurement end trigger has been received. If a measurement end trigger is received, the process proceeds to S49, where the measurement ends, and the operation ends there. If not received, the process proceeds to S50. In S50, the observation / statistical unit 103 determines whether or not the set value update flag received from the determining unit 102 is set. If the flag is not set, the process proceeds to S46, and the length of the next statistical processing period is the same as the length of the previous statistical processing period. If the flag is set, the process proceeds to S51. In S51, the observation / statistical unit 103 reflects the set value of the setting register 106 in the internal signal of the observation / statistical unit 103, and changes the length of the statistical processing period. In S52, the observation / statistical unit 103 clears the set value update flag, and the process returns to S46.

  FIG. 11 is a timing chart showing the operation of the bus monitor 14. The timing chart shown in FIG. 11 shows an example when the bus monitor 14 acquires the cumulative value of the data transfer amount of the system bus 2 as a result of the statistical processing. FIG. 11 does not show all signals and register values of the bus monitor 14. In the timing chart of FIG. 11, the initial value of the setting register 106 set before time T2 is 1000 (cycles), and the setting value of the change register 107 is 750 (cycles) (S11). Due to the action of the setting update flag at time T2, the setting value of the setting register 106 is reflected in the setting value of the internal signal of the observation / statistical unit 103 (S41, S42). At time T7, the bus monitor 14 receives a measurement start trigger (S44), and measurement starts from time T8 (S45).

  The time stamp counter is a counter that holds time information, starts counting up in response to the start of measurement, and does not reset the value until the end of measurement. The measurement cycle number counter is a counter that measures the statistical processing period, and is reset every time the statistical processing period expires. When the value of the measurement cycle number counter reaches the internal signal set value, the observation / statistical unit 103 determines that the statistical processing period has expired and asserts (activates) the arrival flag. The data counter holds a cumulative value of the data transfer amount during the statistical processing period. The observation / statistical unit 103 observes the transfer event of the system bus 2, and when valid data is observed, adds the number of bytes to the current count value of the data counter. In this manner, the data counter accumulates and counts the number of data bytes. The data counter is reset every time the statistical processing period expires.

  For the first statistical processing period after the measurement is started, the bus monitor 14 calculates a cumulative value of the data transfer amount for 1000 cycles as a result of the statistical processing. The bus monitor 14 asserts a valid signal at time T1007. At time T1007, the bus monitor 14 outputs the value of the data counter (cumulative value of the data transfer amount) together with the time information of the time stamp counter to the SRAM 16 as DATA1 (S47). Further, since a transaction having a specific transaction ID is detected in the first statistical processing period (S32), the bus monitor 14 changes the setting value of the setting register 106 to 250 (cycles) (S15). At time T1007, the setting value (250 cycles) of the setting register 106 is reflected in the setting value of the internal signal of the observation / statistical unit 103 by the action of the setting update flag. As a result, the next (second) statistical processing period is shorter than the first statistical processing period.

  In the second statistical processing period, the bus monitor 14 calculates a cumulative value of the data transfer amount for 250 cycles as a result of the statistical processing. At time T1257, the bus monitor 14 outputs the value of the data counter as DATA2 to the SRAM 16 together with the time information of the time stamp counter (S47). Even during this statistical processing period, a transaction having a specific transaction ID has been detected (S32), but since the setting value of the setting register 106 has already been changed (S34), the setting value of the setting register 106 is not changed. Therefore, the third statistical processing period is measured while the set value of the internal signal of the observation / statistical unit 103 remains 250 (cycles).

  In the third statistical processing period, the bus monitor 14 calculates a cumulative value of the data transfer amount for 250 cycles as a result of the statistical processing. At time T1507, the bus monitor 14 outputs the value of the data counter together with the time information of the time stamp counter to the SRAM 16 as DATA3 (S47). Since no transaction having a specific transaction ID was detected during this statistical processing period (S32), the bus monitor 14 changes the setting value of the setting register 106 to 1000 (cycles) (S18). At time T1507, the setting value (1000 cycles) of the setting register 106 is reflected in the setting value of the internal signal of the observation / statistical unit 103 by the action of the setting update flag. As a result, the length of the fourth statistical processing period is the same as the length of the first statistical processing period.

  Thereafter, similar processing continues. At time T5507, the bus monitor 14 receives a measurement end trigger from the outside as the statistical processing period expires. The bus monitor 14 outputs the value of the data counter together with the time information of the time stamp counter to the SRAM 16 as DATA6 (S47), and the measurement ends (S49).

  According to the bus monitor 14 according to the present embodiment, the bus monitor 14 can autonomously change the statistical processing period according to the transfer event observed by the bus monitor 14. Therefore, it is possible to obtain a pinpoint statistical processing result in real time as compared with a case where the statistical processing period is reset from the outside. Since the bus monitor 14 performs statistical processing at a necessary granularity when necessary, the result of the statistical processing can be acquired effectively with a small memory cost.

  The configuration and operation of the bus monitor 14 according to the embodiment has been described above. This embodiment is an exemplification, and it is understood by those skilled in the art that various modifications can be made to each component and combination of processes, and such modifications are within the scope of the present invention.

  In the present embodiment, a case has been described in which one reference register 108 is provided, one transaction ID is stored therein, and the one transaction ID is used as a determination criterion in the determination unit 101. However, the present invention is not limited to this. For example, a plurality of holding functions may be provided to specify a plurality of transaction IDs. Alternatively, a range of transaction IDs may be specified and a transaction ID falling within that range may be detected.

  Or you may use the result of the detection of a specific address, or the produced | generated statistical process as a determination criterion in a determination part. These are realized by the same control as the control for changing the statistical processing period shown in the present embodiment.

(First modification)
FIG. 12A is a block diagram showing a partial configuration of the bus monitor according to the first modification. Of the configuration of the bus monitor according to the first modification, the configuration that is not shown in FIG. 12A conforms to the corresponding configuration of the bus monitor 14 shown in FIG. The bus monitor according to the present modification changes the length of the statistical processing period in response to detection of a specific address.

  The holding unit 601 has an address register 602 for address detection. The determination unit 603 receives address information and a control signal from the observation / statistical unit 604. The address information received by the determination unit 603 from the observation / statistical unit 604 becomes valid when a control signal indicating the establishment timing of a transaction having the address is activated. The determination unit 603 determines whether or not a transaction having a specific address has been detected by comparing the valid address information with the specific address information held in the address register 602. When it is determined that it has been detected, the set value of the length of the statistical processing period is changed to a smaller value by the same processing as in the embodiment. Based on the response information received from the observation / statistical unit 604, the determination unit 603 determines whether or not a response of a transaction having a specific address has been returned. If it is determined that the response has been made, the set value of the length of the statistical processing period is restored.

(Second modification)
FIG. 12B is a block diagram illustrating a partial configuration of the bus monitor according to the second modification. Of the configuration of the bus monitor according to the second modification, the configuration that is not shown in FIG. 12B conforms to the corresponding configuration of the bus monitor 14 shown in FIG. The bus monitor according to the present modification changes the length of the statistical processing period according to the generated statistical processing result. There may be a plurality of pieces of information generated by the statistical process from the transfer event. In this modification, one piece of information is used for changing the statistical process period.

  The holding unit 605 includes an upper limit threshold register 606 that holds an upper limit threshold of a result of statistical processing, and a lower limit threshold register 607 that holds a lower limit threshold of a result of statistical processing. The determination unit 608 receives the result of the statistical processing from the observation / statistical unit 609. The determination unit 608 compares the received statistical processing result with the upper threshold stored in the upper threshold register 606. When the result of statistical processing exceeds the upper limit threshold, the set value of the length of the statistical processing period is changed to a smaller value by the same processing as in the embodiment. The determination unit 608 compares the statistical processing result received thereafter with the lower threshold stored in the lower threshold register 607. When the result of statistical processing falls below the lower limit threshold, the set value of the length of the statistical processing period is returned to the original by the same processing as in the embodiment.

  According to the bus monitor according to this modification, the bus monitor can autonomously change the statistical processing period according to the result of the statistical processing generated by the bus monitor. Therefore, it is possible to obtain a pinpoint statistical processing result in real time as compared with a case where the statistical processing period is reset from the outside. Since the bus monitor performs statistical processing at a required granularity when necessary, the result of the statistical processing can be acquired effectively with a small memory cost.

(Third Modification)
FIG. 12C is a block diagram illustrating a partial configuration of the bus monitor according to the third modification. Of the configuration of the bus monitor according to the third modified example, the configuration not shown in FIG. 12C conforms to the corresponding configuration of the bus monitor 14 shown in FIG. The bus monitor according to this modification refers to an event signal input from the outside when determining whether or not it is necessary to change the length of the statistical processing period.

  The determination unit 610 includes ID information held in the reference register 108 of the holding unit 104, ID information observed by the observation / statistical unit 611, whether an event signal received from the outside of the bus monitor is activated, Based on the above, it is determined whether or not the statistical processing period needs to be changed. Specifically, the determination unit 610 determines that a change is necessary when the observed ID information matches the ID information held in the reference register 108 and an external event signal is activated. .

  There may be a plurality of external event signals, a register may be selected from among them, or on / off may be possible. The event signal is an arbitrary signal generated outside the bus monitor and indicating a system event other than an event of the system bus 2. For example, the event signal may include a synchronization signal, a data enable signal, and a field signal superimposed on the video. Alternatively, the event signal may include a signal indicating an activation state of a master module such as DMA (Direct Memory Access).

  The determination unit 612 includes a setting register 613 for setting a default value for the length of the statistical processing period, and a change register 614 for setting a change value for the length of the statistical processing period. The determination unit 612 switches a register referred to by the observation / statistical unit 611 (hereinafter referred to as a reference destination) between the setting register 613 and the change register 614 according to the determination result in the determination unit 610. Thereby, the length of the statistical processing period is changed.

The operation of the bus monitor according to this modification example having the above configuration will be described.
The bus monitor observes the transfer event of the system bus 2, performs statistical processing of the transfer event every statistical processing period, and acquires the result of the statistical processing. In this, the bus monitor changes the length of the statistical processing period. FIG. 13 is a flowchart showing a flow of a series of processes in the determination unit 612 in FIG. In S61, the external controller sets the value of the setting register 613 and the value of the change register 614 of the determining unit 612. In addition, the determination unit 612 sets the setting register 613 as a reference destination. In S65, the determination unit 612 switches the reference destination from the setting register 613 to the change register 614. In S <b> 68, the determination unit 612 switches the reference destination from the change register 614 to the setting register 613.

  FIG. 14 is a flowchart showing a flow of a series of processes in the determination unit 610 of FIG. In S72, the determination unit 610 determines whether or not a transaction having a specific transaction ID has been detected by comparing the ID information received from the observation / statistical unit 611 with the ID information held in the reference register 108. In addition, the determination unit 610 determines whether or not an external event signal is activated. If it is determined that a transaction having a specific transaction ID has been detected and it is determined that the event signal has been activated, the process proceeds to S34. Otherwise, the process proceeds to S33.

  Therefore, if the event signal is not activated, the bus monitor does not change the statistical processing period even if it detects a specific transaction ID. If the activation of the event signal is canceled in a state where the length of the statistical processing period is changed, the length of the statistical processing period is returned to the original set value.

  The operation of the observation / statistical unit 611 conforms to the operation described in the flowchart shown in FIG.

  FIG. 15 is a timing chart showing the operation of the bus monitor according to the third modification. The timing chart shown in FIG. 15 shows an example in which the bus monitor acquires the cumulative value of the data transfer amount of the system bus 2 as a result of statistical processing. FIG. 15 does not show all signals and register values of the bus monitor. In the timing chart of FIG. 15, the initial value of the setting register 613 set before time T2 is 1000 (cycles), and the initial value of the change register 614 is 250 (cycles) (S11). By the action of the setting update flag at time T2, the setting value of the setting register 613, which is the default reference destination, is reflected in the setting value of the internal signal of the observation / statistic unit 611 (S41, S42). At time T7, the bus monitor receives a measurement start trigger (S44), and measurement starts from time T8 (S45).

  For the first statistical processing period after the measurement is started, the bus monitor calculates a cumulative value of the data transfer amount for 1000 cycles as a result of the statistical processing. The bus monitor asserts a valid signal at time T1007. At time T1007, the bus monitor outputs the value of the data counter together with the time information of the time stamp counter as DATA1 to the SRAM 16 (S47). In the first statistical processing period, a transaction having a specific transaction ID is detected, and an external event signal is activated (S72). Therefore, the reference destination is changed from the default setting register 613 to the change register 614 (S65). At time T1007, the change register 614 is referred to by the action of the setting update flag, and the set value (250 cycles) is reflected in the set value of the internal signal of the observation / statistic unit 611. As a result, the next (second) statistical processing period is shorter than the first statistical processing period.

  In the second statistical processing period, the bus monitor calculates a cumulative value of the data transfer amount for 250 cycles as a result of the statistical processing. At time T1257, the bus monitor outputs the data counter value as DATA2 to the SRAM 16 together with the time information of the time stamp counter (S47). Even during this statistical processing period, a transaction having a specific transaction ID is detected and an external event signal is activated (S72), but the reference register has already been switched (S34). Is not done. Therefore, the third statistical processing period is measured while the set value of the internal signal of the observation / statistical unit 611 remains 250 (cycles).

  In the third statistical processing period, the bus monitor calculates a cumulative value of the data transfer amount for 250 cycles as a result of the statistical processing. At time T1507, the bus monitor outputs the value of the data counter together with the time information of the time stamp counter as DATA3 to the SRAM 16 (S47). In this statistical processing period, since an external event signal is deactivated (S72), the reference destination is changed from the change register 614 to the setting register 613 (S68). At time T1507, the setting value (1000 cycles) of the setting register 613 is reflected in the setting value of the internal signal of the observation / statistical unit 611 by the action of the setting update flag. As a result, the length of the fourth statistical processing period is the same as the length of the first statistical processing period.

  Thereafter, similar processing continues. At time T5507, the bus monitor receives a measurement end trigger from the outside as the statistical processing period expires. The bus monitor outputs the value of the data counter together with the time information of the time stamp counter as DATA6 to the SRAM 16 (S47), and the measurement ends (S49).

  According to the bus monitor according to this modification, the bus monitor can autonomously change the statistical processing period according to the transfer event observed by the bus monitor 14 and the state of the external event signal. Therefore, it is possible to obtain a pinpoint statistical processing result in real time as compared with a case where the statistical processing period is reset from the outside. Since the bus monitor performs statistical processing at a required granularity when necessary, the result of the statistical processing can be acquired effectively with a small memory cost.

  In this modification, a case has been described in which the length of the statistical processing period is changed when a specific transaction ID is detected and an external event signal is activated. In another modification, whether or not the statistical processing period needs to be changed may be determined only by an external event signal (that is, regardless of the transfer event or the result of statistical processing).

  2 system bus, 14 bus monitor, 20 bus system, 101 determination unit, 102 determination unit, 103 observation / statistics unit.

Claims (10)

Observation means for observing bus transfer events;
Statistical means for performing statistical processing of transfer events every statistical processing period;
Holding means for holding the results of statistical processing;
A bus monitor comprising: changing means for changing a statistical processing period according to an observed transfer event or a result of statistical processing.   The bus monitor according to claim 1, wherein the changing unit changes a statistical processing period according to an event signal input from outside.   3. The bus monitor according to claim 1, wherein the bus transfer event includes specific ID information of the bus transfer.   4. The bus monitor according to claim 1, wherein the bus transfer event includes specific address information of the bus transfer. Based on the observed transfer event or the result of statistical processing, further comprises a determination means for determining whether or not the statistical processing period needs to be changed,
The bus monitor according to any one of claims 1 to 4, wherein the changing unit changes a statistical processing period when the determination unit determines that a change is necessary.   The bus monitor according to claim 5, further comprising means for holding determination information referred to when determining whether or not the statistical processing period needs to be changed.   The bus monitor according to any one of claims 1 to 6, wherein the holding unit holds a statistical processing result and time information in association with each other. A setting register to set the length of the statistical processing period;
A change register, and
The statistical means counts a statistical processing period by referring to the setting register;
The bus monitor according to claim 1, wherein the changing unit changes a statistical processing period by changing the setting register with reference to the change register. A first register and a second register for setting the length of the statistical processing period;
The change means changes the statistical processing period by switching a register referred to by the statistical means between the first register and the second register to measure the statistical processing period. The bus monitor according to any one of the above. Observing bus transfer events;
Perform statistical processing of transfer events every statistical processing period,
Storing the results of statistical processing in the holding means;
Changing the statistical processing period in accordance with the observed transfer event or the result of the statistical processing.

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