CN118034991A

CN118034991A - Memory data access method and device, electronic equipment and readable storage medium

Info

Publication number: CN118034991A
Application number: CN202410436990.7A
Authority: CN
Inventors: 赵阳洋; 陈明宇; 卢天越; 吴双; 闫世显; 唐丹; 包云岗
Original assignee: Beijing Open Source Chip Research Institute
Current assignee: Beijing Open Source Chip Research Institute
Priority date: 2024-04-11
Filing date: 2024-04-11
Publication date: 2024-05-14
Anticipated expiration: 2044-04-11

Abstract

The application provides a memory data access method, a memory data access device, electronic equipment and a readable storage medium, and relates to the technical field of computers, wherein the memory data access method comprises the following steps: acquiring fault information of a memory component; aiming at fault information, configuring an address space mapping scheme; responding to an initial access instruction sent by a processor, and extracting an access address in the initial access instruction; according to the mapping scheme of the access address and the address space, a plurality of target addresses corresponding to the access address are obtained; the target access instruction corresponds to the target address one by one; executing a target access instruction through the memory controller to write split data obtained after splitting the write data sent by the processor into a target address; the read data read from the target address is spliced and then returned to the processor. Based on the method of the embodiment, the data bit width can be kept and the system is ensured to work at the design frequency under the condition that the memory component fails.

Description

Memory data access method and device, electronic equipment and readable storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and apparatus for accessing memory data, an electronic device, and a readable storage medium.

Background

The memory is used as a key part for storing data of the computer and provides data for the operation of all programs. With the continuous increase of the working frequency of the memory particles, the requirements on the manufacturing level and the like of the process are gradually increased, and after-board-manufacturing testing is often carried out, the whole system cannot be started due to memory faults such as memory unit defects, uneven PCB wiring, particle quality problems and the like, or the stability problem of the memory cannot work at the design frequency, so that the system performance is affected.

In the related art, in the case of memory failure such as a memory cell defect, a PCB wiring unevenness, a particle quality problem, etc., the memory failure is generally solved by the following method: the memory stripes or the memory particles are replaced, or the configuration such as the precision power supply is replaced to improve the memory stability. In the related art, the memory frequency setting directly affects the stability of the memory and the debugging of the memory parameters, and the memory faults can be solved by reducing the working frequency of the memory and adjusting the memory parameters, for example, the industrial grade suggests that the debugging of the memory parameters is carried out from an initial value with the main frequency of 1.2G and the transmission rate of 1.6G of the double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR 4), and the debugging can be improved after the debugging is stable. The memory parameters include performance and specifications of the memory module, such as capacity, speed, timing, and the like.

However, the replacement of the memory strips or the memory particles cannot solve the signal integrity problem caused by the uneven wiring of the PCB, and the on-board memory often exists in the form of particle patches, so that the memory strips are difficult to replace by simply plugging and unplugging as the standard memory strips, and the risk of larger faults such as board card damage is caused by manual welding. The method reduces the working frequency of the memory and adjusts the memory parameters, and part of data lines still can work unstably due to memory unit defects or uneven PCB wiring, and then the subsequent lifting and optimizing needs to manually debug a large amount of memory initialization training parameters, so that the memory is difficult to adjust to stable work in a short period to support system starting, and even through a large amount of debugging, the memory can still only work stably at lower memory frequency, and the system performance is reduced. The memory initialization training is a process of continuously adjusting memory parameters, and is used for ensuring that a memory module can be correctly initialized and stably operated when a system is started. That is, in the related art, a memory access method which can avoid the signal integrity problem caused by uneven wiring of a PCB, avoid the damage of replacing memory particles and board cards and ensure that the memory can work at the design frequency is lacking in the case of the failure of the memory component.

Disclosure of Invention

The embodiment of the application provides a memory data access method, a memory data access device, electronic equipment and a readable storage medium, which are used for solving the problems that in the prior art, under the condition that a memory component fails, the signal integrity problem caused by uneven PCB wiring can be avoided, the damage of a board card caused by replacing memory particles can be avoided, and the memory can be ensured to work at a design frequency.

In a first aspect, an embodiment of the present application provides a method for accessing memory data, including:

acquiring fault information of a memory component; configuring an address space mapping scheme for the fault information; responding to an initial access instruction sent by a processor, and extracting an access address in the initial access instruction; acquiring a plurality of target addresses corresponding to the access address according to the access address and the address space mapping scheme; splitting the initial access instruction into a plurality of target access instructions according to a plurality of target addresses; the target access instruction corresponds to the target address one by one; executing the target access instruction through a memory controller to write split data obtained after splitting write data sent by the processor into the target address; and splicing the read data read from the target address, and returning to the processor.

In a second aspect, an embodiment of the present application provides an apparatus for accessing memory data, where the apparatus includes: the acquisition module is used for acquiring fault information of the memory component; the configuration module is used for configuring an address space mapping scheme aiming at the fault information; the extraction module is used for responding to an initial access instruction sent by the processor and extracting an access address in the initial access instruction; the mapping processing module is used for acquiring a plurality of target addresses corresponding to the access address according to the access address and the address space mapping scheme; the instruction splitting module is used for splitting the initial memory access instruction into a plurality of target memory access instructions according to a plurality of target addresses; the target access instruction corresponds to the target address one by one; the first execution module is used for executing the target access instruction through the memory controller so as to write split data obtained after splitting the write data sent by the processor into the target address; and splicing the read data read from the target address, and returning to the processor. In a third aspect, an embodiment of the present application further provides an electronic device, including a processor; a memory for storing the processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method of the first aspect.

According to the embodiment, the memory component does not need to be replaced, the memory failure is not required to be solved by reducing the working frequency of the memory and adjusting the memory parameters, the signal integrity problem caused by uneven PCB wiring can be avoided under the condition that the memory component fails, the damage of the board card caused by replacing memory particles can be avoided, and the memory can be ensured to work at the design frequency. In addition, based on the method of the embodiment, under the condition that the memory component fails, the memory controller can still provide a linear memory space for the processor core, keep the data bit width, ensure the system to work at the design frequency, support and shield the memory failure, realize the starting of the system and the running of the program, enable the processor verification and the memory optimization to be performed in parallel, and accelerate the verification flow after the plate-making and the plate-returning.

The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is an application scenario schematic diagram of a memory data access method provided by an embodiment of the present application;

FIG. 2 is a flowchart illustrating steps of a method for accessing memory data according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating steps of another method for accessing memory data according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating steps of a method for processing spliced data according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an address space mapping relationship of a memory module with a faulty memory granule according to an embodiment of the present application;

FIG. 6 is a block diagram of a memory access system according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating steps of a method for accessing memory data according to another embodiment of the present application;

FIG. 8 is a block diagram of a method and apparatus for accessing memory data according to an embodiment of the present application;

FIG. 9 is a block diagram of an electronic device provided by an embodiment of the invention;

Fig. 10 is a block diagram of another electronic device in accordance with another embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present application means two or more, and other adjectives are similar.

Fig. 1 is a schematic diagram of an application scenario of a memory access method according to an embodiment of the present application, and referring to fig. 1, the application scenario at least includes a processor 10, a memory controller 20, and a memory 30, where a data line, an address line, and a control line are connected between the memory controller 20 and the memory 30. The memory controller 20 is provided with a memory data access device 201.

When the processor 10 performs a memory access operation on the memory 30, the processor 10 sends a memory access instruction to the memory controller 20. In the case that the memory access instruction is a read operation instruction, the memory controller 20 sends the memory access address to the memory 30 through the address line, and sends the control signal to the memory 30 through the control line, and then reads the data stored in the memory 30 through the data line, and sends the read data to the processor 10. In the case that the memory access instruction is a write operation instruction, the memory controller 20 sends the memory access address and the control signal to the memory 30 through the address line, and sends the data to the memory 30 through the data line, and writes the data into the memory 30 at the memory access address.

In the application, an initial memory access instruction sent by a processor is responded, and a memory access address in the initial memory access instruction is extracted; according to the mapping scheme of the access address and the address space, a plurality of target addresses corresponding to the access address are obtained; splitting the initial memory access instruction into a plurality of target memory access instructions according to a plurality of target addresses; executing a target access instruction through the memory controller to write split data obtained after splitting the write data sent by the processor into a target address; the read data read from the target address are spliced and then returned to the processor, so that under the condition that the memory component fails, the problem of signal integrity caused by uneven PCB wiring can be avoided, the damage of the board card caused by the replacement of memory particles can be avoided, and the memory can be ensured to work at the design frequency.

The memory data access method provided by the embodiment of the application is described in detail below by means of specific embodiments with reference to the accompanying drawings.

Fig. 2 is a flowchart of a memory data access method according to an embodiment of the present application, where, as shown in fig. 2, the method may include:

Step 101, obtaining fault information of the memory component.

For example, the failure information of the memory component may include: memory granule failure, data line failure, memory cell failure, or other memory component failure, the present solution does not specifically limit the failed memory component. The memory granule is a basic unit of the memory device, and the main memory granule type comprises double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR4 SDRAM). A Memory Cell (Memory Cell) is a minimum storage unit in a computer for storing binary data. The processor core runs configuration software, accesses the memory configuration interface through the on-chip bus, and acquires fault information of the memory component.

Step 102, for the fault information, an address space mapping scheme is configured.

For example, the memory components corresponding to the fault information are different, and the address space mapping schemes configured for the fault information are also different.

For example, the failed memory component is a part of memory particles, and access to the failed memory particles can be mapped to available memory particles by reserving a memory address for shielding the failure, so that a system program can operate under shielding the failure of the memory, the system is ensured to work at a design frequency through prefetching and buffering, and fine memory parameter debugging can be performed in parallel with verification of the whole system. The memory failure refers to a problem occurring in the memory of the computer, which causes the computer to be unable to read or write data normally.

For another example, the failed memory component is a portion of a data line, wherein the data line is used to transfer data between the memory granule and the memory controller. The effective data bit width acquired by the processor core is reduced due to the failure of part of the memory data lines, the one-time read-write access memory of the processor core is divided into multiple reads and writes by different address mapping schemes such as address conversion, reserved memory space round-robin access and the like, and the data bit width acquired by the processor core is complemented by the data splicing, so that a system program can shield the failure operation of the memory data lines. Through different address mapping schemes such as address conversion, reserved memory space round-robin access and the like, a system program can shield the fault operation of a memory data line.

For another example, the failed memory component is a partial memory cell. And the matched access requests are split and spliced by recording the address, the particle number, the corresponding reserved memory address, the particle number and other information of the failed memory unit in the address space mapping table, so that the system program can shield the failed operation of the memory unit. And the matched access requests are split and spliced by recording the address, the particle number, the corresponding reserved memory address, the particle number and other information of the failed memory unit in the address space mapping table, so that the system program can shield the failed operation of the memory unit.

Step 103, responding to the initial access instruction sent by the processor, and extracting the access address in the initial access instruction.

Specifically, the memory address is used for performing data access on at least part of the memory components in the memory. The memory component is, for example, memory granules in a memory bank, there are 8 memory granules in the memory bank, and the memory address is used for performing data access on the 8 memory granules in the memory bank. The processor may be a central processing unit (Central Processing Unit, CPU).

Step 104, obtaining a plurality of target addresses corresponding to the access addresses according to the access addresses and the address space mapping scheme.

Specifically, the target address includes a first address and a second address. The first address is used for acquiring data of all normal components in the memory component, and the second address is used for acquiring data of a preset number of normal components in all normal components. The preset number is equal to the number of failed components. The normal component is a memory component in a normal operation state.

Step 105, splitting the initial access instruction into a plurality of target access instructions according to the plurality of target addresses.

The target access instructions and the target addresses are in one-to-one correspondence. For example, the initial access instruction is split into a plurality of target access instructions, the target access instructions include different target addresses, and the target access instructions and the target addresses are in one-to-one correspondence. For example, the target address includes a first address and a second address, and the target memory access instruction includes a target memory access instruction using the first address as a memory access address and a target memory access instruction using the second address as a memory access address.

Step 106, executing the target access instruction through the memory controller to write the split data obtained after splitting the write data sent by the processor into the target address; the read data read from the target address is spliced and then returned to the processor.

In one embodiment, the target access instruction is a read operation instruction, the first execution result is first read data corresponding to the first address, and the second execution result is second read data corresponding to the second address; and splicing the first read data and the second read data to obtain spliced complete read data. The complete read data is returned to the processor. Wherein, there may be one or more second addresses, and correspondingly, there may be one or more second read data.

Specifically, a plurality of read operation instructions are sent to a memory controller, the read operation instructions are received by the memory controller, and each read operation instruction is executed respectively to obtain a plurality of read data. The read data and the read operation instruction are in one-to-one correspondence, and the read operation instruction and the target address are in one-to-one correspondence, so that the read data and the target address are in one-to-one correspondence.

Further, the target address is a first address or a second address, the read operation instruction comprises the first address or the second address, and the memory controller reads data at the first address or the second address of the memory according to the first address or the second address in the read operation instruction, so as to obtain read data. After the memory controller executes one target access instruction, the obtained first read data corresponding to the first address and the obtained second read data corresponding to the second address are stored in the data cache module, after all target access instructions are executed, all the first read data and all the second read data are spliced to obtain complete read data with the data bit width required by the processor, and then the complete read data is returned to the processor.

For example, in the case that the target access instruction is a write operation instruction, the write data is split into the same number of write data as the target access instruction, and the split write data is provided to the corresponding write operation instruction. The memory controller sends the split write data and the write operation instruction to the memory so as to write the split write data into the first address or the second address in the memory respectively, and further obtains the write data written into the first address and the second address respectively.

In the related art, when a memory granule fault or a memory data line fault is encountered, either the memory granule is replaced or the working frequency of the memory is reduced and fine memory parameter debugging is performed, the replacement of the memory granule cannot solve the signal integrity problem caused by uneven PCB wiring and the risk of larger faults such as board damage is caused, the working frequency of the memory is reduced and fine memory parameter debugging is performed, the memory granule cannot work at the design frequency and the memory parameter debugging is most likely to delay the project verification period. When the related art encounters a memory unit fault, a more complex memory error correction scheme is often adopted or a memory fault tolerance technology is integrated in the system, so that the resource cost is high and the optimization is possible. In this embodiment, the memory component does not need to be replaced, the memory failure does not need to be solved by reducing the working frequency of the memory and adjusting the memory parameters, the signal integrity problem caused by uneven PCB wiring can be avoided under the condition that the memory component fails, the board card damage caused by replacing memory particles can be avoided, and the memory can be ensured to work at the design frequency. Based on the method of the embodiment, under the condition that the memory component fails, the memory controller can still provide a linear memory space for the processor core, keep the data bit width, ensure the system to work at the design frequency, support and shield the memory failure, realize the starting of the system and the running of the program, enable the processor verification and the memory optimization to be performed in parallel, and accelerate the verification flow after the plate-making and the plate-returning.

Fig. 3 is a flowchart of steps of another method for accessing memory data according to an embodiment of the present application, and referring to fig. 3, the method may include the following steps:

in step 201, failure information of a memory component is obtained.

The method of this step is described in the foregoing step 101, and will not be described here again.

Step 202, configuring an address space mapping scheme for fault information through a software program;

wherein the software program runs on an embedded processor added in the memory controller or in firmware added in the processor core.

Further, an embedded processor may be added to the memory controller, or a memory configuration interface may be added to communicate with the processor core, which adds firmware to run a software program. The embedded processor or processor core may obtain status information of each memory granule and each data line, and analyze the memory granule, data line, or memory unit that has failed. And determining the memory components with faults as memory components needing shielding, and then selecting an address space mapping scheme corresponding to the memory components with faults for configuring an address space mapping table maintained by hardware according to the determined address space mapping scheme.

Further, the obtained state information may be the state information of the memory granule, the data line, and the memory unit, or may be information of other memory components, and the address space mapping scheme is flexibly configured according to the failed memory component through a software program.

Step 203, write the address space mapping scheme into the address space mapping table through the memory configuration interface.

The address space mapping scheme is illustratively configured by a software program and then written to the address space mapping table by a memory configuration interface.

Step 204, responding to the initial access instruction sent by the processor, and extracting the access address in the initial access instruction.

Step 205, obtaining a plurality of target addresses corresponding to the memory addresses according to the memory addresses and the address space mapping scheme recorded in the address space mapping table.

In step 206, the initial memory access instruction is split into a plurality of target memory access instructions according to the plurality of target addresses.

Specifically, the target access instruction corresponds to the target address one by one;

step 207, executing the target access instruction by the memory controller to write the split data obtained after splitting the write data sent by the processor into the target address; the read data read from the target address is spliced and then returned to the processor.

In this embodiment, the memory component does not need to be replaced, the memory failure does not need to be solved by reducing the working frequency of the memory and adjusting the memory parameters, the signal integrity problem caused by uneven PCB wiring can be avoided under the condition that the memory component fails, the board card damage caused by replacing memory particles can be avoided, and the memory can be ensured to work at the design frequency. In addition, based on the method of the embodiment, under the condition that the memory component fails, the memory controller can still provide a linear memory space for the processor core, keep the data bit width, ensure the system to work at the design frequency, support and shield the memory failure, realize the starting of the system and the running of the program, enable the processor verification and the memory optimization to be performed in parallel, and accelerate the verification flow after the plate-making and the plate-returning.

In one embodiment, referring to fig. 4, the concatenation of read data read from the target address in step 207 and then returned to the processor may include the following sub-steps (sub-steps 2071 through 2073):

in step 2071, the read data read from the target address is spliced to obtain spliced data.

For example, the read data read from the target address may be spliced by the data caching module to obtain spliced data.

And step 2072, performing error checking and correction technology processing on the spliced data to obtain processed spliced data.

For example, the spliced data may be subjected to Error CHECKING AND correction (ECC) processing by a data buffer module, so as to obtain processed spliced data.

In a substep 2073, the processed spliced data is returned to the processor.

By way of example, the quality information of each memory granule and each data line is obtained by a processor core software program, a corresponding address space mapping scheme is selected by the software program according to the fault information, and the address space mapping scheme suitable for the quality of the current memory system is written into an address space mapping table maintained by hardware. When the software program runs, each time the processor core sends a memory access request (i.e. an initial memory access instruction), according to an address space mapping table maintained by hardware, the memory access request is split into a plurality of requests (i.e. into a plurality of target memory access instructions), and then the split plurality of requests are sent to the memory through the request pre-fetching module.

In one embodiment, step 205 may include the following sub-steps (sub-step 2051):

sub-step 2051, in the event of a faulty component in at least a portion of the memory components in the memory, translates the memory address to a first address and a second address according to the memory address and address space mapping scheme.

The first address is used for acquiring data of all normal components in the memory component, and the second address is used for acquiring data of a preset number of normal components in all normal components; the preset number is equal to the number of failed components. Wherein the first address is one, and the second address is one or more. For example, memory failure may be caused by at least one of Memory grain quality problems, data line non-uniformity, and Memory Cell (Memory Cell) defects. The memory particles, the data lines and the memory cells are arranged in order from large to small in the address space affected by the failure. The memory granule is a basic unit for forming the memory device, and the type of the memory granule can be double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), and can also be DDR SDRAM of other types. The memory cell is the smallest memory cell in a computer that can be used to store binary data.

The address space mapping scheme may include: an address conversion method for converting an access address into a target address and a corresponding relation between the target address and a memory component. The address space mapping scheme may be a policy that the processor pre-generates based on the faulty component information. After the processor generates the address space mapping scheme, the address space mapping scheme may be sent to the memory device shown in fig. 1, so that the memory device stores the address space mapping scheme in the address space mapping table of the memory device.

The first address is the memory address in the initial memory access instruction, and the second address is the memory address obtained by performing address conversion on the first address according to the address space mapping scheme. The memory address space is illustratively divided into an address space that is visible to the processor and an address space that is not visible to the processor. In the case where the address space is visible to the processor, when the processor sends an initial memory instruction, the memory address in the initial memory instruction can only be the address in the address space. The first address and the second address are translated addresses corresponding to the memory address obtained according to an address space mapping scheme. The destination address may or may not include the same address as the memory address.

For example, referring to fig. 5, the memory components are memory granules in the memory stripe, and there are 8 memory granules in the memory stripe, where the memory granules with faults are memory granules 3 and 6, and the memory granules in the normal operation state are other memory granules. The first address is an address in the memory address space between 0x00000000 and 0xbfffffff in the initial memory instruction, and is used to obtain the data of other normal memory granules except the memory granule 3 and the memory granule 6. The second address is a memory address obtained by performing address conversion on the first address according to an address space mapping scheme, the second address is in a memory address space between 0xc0000000 and 0xfffffff, and the number of normal memory particles corresponding to the second address is equal to the number of fault memory particles. In the address space mapping scheme of fig. 5, if the memory address in the initial memory access instruction is between 0x00000000 and 0x3ffffff, the memory grain corresponding to the second address is the memory grain 1 and the memory grain 5, and the second address is used for acquiring the data of the memory grain 1 and the memory grain 5.

Under the condition that all the memory components are normal components in a normal running state, the target address is not required to be acquired according to the memory address, and the initial memory access instruction is directly sent to the memory controller so as to execute corresponding memory access operation according to the initial memory access instruction through the memory controller.

For example, the target memory access instruction is sent to the memory controller, the memory controller responds to the received target memory access instruction, and memory access operation is executed on the memory according to the target address in the target memory access instruction, so as to obtain a memory data access result. A memory controller is a hardware intellectual property (Intellectual Property) core for controlling memory access and data transfer in a computer system, including the interface between a processor and memory, and associated processing logic.

For example, the target memory access instruction is a read operation instruction, and the first execution result and the second execution result are read data read from the memory. And acquiring a memory data access result according to the first execution result and the second execution result. For example, the first execution result and the second execution result are spliced to obtain the memory data access result. For another example, the target access instruction is a write operation instruction, and the first execution result and the second execution result are write data written into the memory. Obtaining a memory data access result according to the first execution result and the second execution result, including: and determining write data formed by the first execution result and the second execution result as memory data access results obtained by executing the write operation instruction.

Illustratively, the failed memory component is a portion of memory granules, and access to the failed memory granules is mapped to available memory granules by reserving memory addresses for masking the failure, so that the system program can mask the memory failure operation. The system is guaranteed to work at the design frequency by prefetching and buffering.

For example, referring to fig. 5, in the 8 memory granules, each memory granule corresponds to a data bit width of 8 bits. Under the condition that all memory particles are normal memory particles, based on one memory access instruction, performing one memory access operation on the memory module, wherein the data bit width of the memory data access result can be obtained is as follows: 8×8 bit=64 bit. The normal memory granules corresponding to the first address are respectively memory granule 1, memory granule 2, memory granule 4, memory granule 5, memory granule 7 and memory granule 8, and the data bit width of the obtained memory data access result based on the target memory access instruction including the first address is: 6×8 bit=48 bit.

The number of normal memory particles corresponding to the second address is equal to the number of failed memory particles, and two failed memory particles (memory particles 3 and 6) are provided, so that two normal memory particles corresponding to the second address are provided, namely memory particles 1 and 5 respectively. Based on the target memory access instruction comprising the second address, the data bit width of the memory data access result can be obtained as follows: 2×8 bit=16 bit.

Based on the target memory access instruction including the first address, a first execution result corresponding to the first address can be obtained, wherein the first execution result includes data of all normal memory grains, and the data bit width of the data of all normal memory grains is 48 bits. Based on the target memory access instruction including the second address, a second execution result corresponding to the second address may be obtained, where the second execution result includes data of the memory granule 1 and the memory granule 5, and the data bit width of the data of the two normal memory granules is 16 bits.

According to the first execution result and the second execution result, the total data bit width of the memory access result can be obtained as follows: 48bit+16bit=64 bit. Namely, in the case that the memory grain 3 and the memory grain 6 fail, by splitting the initial memory access instruction into two target memory access instructions, based on the two target memory access instructions, the data of the failed memory grain 3 and the failed memory grain 6 can be shielded, the memory access operations of the two failed memory grains are converted into memory access operations of the normal memory grain 1 and the normal memory grain 5, the data bit width of the finally obtained memory data access result is the same as the data bit width of the available effective memory data access result before the failure (both are 64 bits), and the data integrity of the memory data access result is ensured.

The memory data access method of the present application is further illustrated by the following description in conjunction with more specific embodiments. In one embodiment, where the memory component is a memory granule, the first address is a memory address. Step 205 may include the following substeps (substep 2052 through substep 2053)

Sub-step 2052, a first address space visible to the processor and a second address space invisible to the processor are acquired in the memory address space.

The ratio of the interval size of the first address space to the interval size of the second address space is equal to the ratio of the total memory capacity of all normal memory particles to the total memory capacity of all fault memory particles. The memory address is an address in the first address space.

The first address space is visible to the processor, and indicates that when the processor generates an initial access instruction, the access address in the initial access instruction can only be the address in the first address space. The second address space is invisible to the processor, meaning that when the processor generates an initial memory instruction, the memory address in the initial memory instruction is not an address in the second address space. While the second address space is not visible to the processor, the second address is visible to the memory controller. After converting the first address in the first address space into the second address in the second address space, the memory controller can still execute the memory access operation for the second address based on the address in the second address space.

For example, referring to fig. 5, the memory module includes 8 memory granules, each of which has a memory capacity of 4G. And 6 normal memory particles and 2 fault memory particles are arranged, and the effective data bit width obtained by executing each initial memory access instruction is 48 bits. The effective memory capacity of the memory module is 6×4g=24g, and the effective memory capacity is equal to the total memory capacity of all normal memory particles: 6×4g=24g. If there are two failed memory particles, the total memory capacity of all the failed memory particles is: 2×4g=8g.

The memory address space of 4G is divided into a first address space and a second address space, and according to the method of the present embodiment, the range of the first address space is 0x00000000 to 0xbfffffff, and the interval size of the first address space is 3G. The range of the second address space is 0xc0000000 to 0xfffffff, and the section size of the second address space is 1G.

Sub-step 2053 converts the memory address to a second address according to an address space mapping scheme, the second address being in the second address space.

The ratio of the interval size of the first address space to the interval size of the second address space is equal to the ratio of the total memory capacity of all normal memory particles to the total memory capacity of all fault memory particles. Further, the memory address is an address in the first address space.

For example, the processor obtains the running state information of the memory granule, and when determining that the memory granule 3 and the memory granule 6 are fault memory granules which cannot stably run at the design frequency, calculates the content space visible to the processor of each memory granule as 24G/8=3g. For each of the 6 normal memory granules, the remaining memory capacity is 6× (4G-3G) =6g, which is not visible to the processor, the portion of memory space is allocated to the 2 failed memory granules, an address space mapping scheme is obtained, and stored in an address space mapping table in the memory device for subsequent translation of the first address to the second address according to the address space mapping scheme.

By way of example, further, a preset offset address may be superimposed on the first address to obtain a second address in the second address space.

For example, in the embodiment shown in fig. 5, the address conversion formula for converting the first address a into the second address may be: (A% (0 x 40000000) +0 xc0000000). Where a% (0X 40000000) represents that the remainder of the first address a to the address (0X 40000000) is obtained, for example, the first address a is 0X8000000f, and according to the above address conversion formula, the second address is 0x0000000f+0xc0000000=0xc000000 f.

In one embodiment, the failed memory component is a memory granule, and the number of failed memory granules is less than the number of normal memory granules. Correspondingly, step 205 may further comprise the following sub-steps (sub-step 2054 to sub-step 2056):

sub-step 2054 obtains a plurality of first sub-address spaces included in the first address space.

Specifically, the first sub-address space corresponds to a predetermined number of normal memory particles.

For example, the processor may divide the first address space into a preset number of first sub-address spaces on average, or may divide the first address space into a plurality of first sub-address spaces according to a random address space size. The corresponding normal memory granule can be set for each first sub-address space according to a random allocation method.

For example, referring to fig. 5, the first address space with the memory address range of 0x00000000 to 0 xffffffffff is divided into 3 first sub-address spaces, and the 3 first sub-address spaces are respectively: 0x00000000 to 0x3fffffff,0x40000000 to 0x7fffff, 0x80000000 to 0xbfffffff. The normal memory grains corresponding to the first sub-address spaces 0x00000000 to 0x3fffffff include the memory grain 1 and the memory grain 5, the normal memory grains corresponding to the first sub-address spaces 0x40000000 to 0x7fffff include the memory grain 2 and the memory grain 7, and the normal memory grains corresponding to the first sub-address spaces 0x80000000 to 0xbfffffff include the memory grain 4 and the memory grain 8.

Sub-step 2055, determining a target first sub-address space in which the memory address is located from the plurality of first sub-address spaces.

And comparing the access memory address with each first sub-address space, and determining the first sub-address space where the access memory address is located as a target first sub-address space. For example, in fig. 5, if the address is 0x8000000f, the first sub-address space of the target where the address is located is: 0x80000000 to 0xbfffffff.

Sub-step 2056 determines the normal memory granule corresponding to the target first sub-address space as the normal component corresponding to the second address.

For example, referring to fig. 5, the target first sub-address space in which the access address is located is: and 0x80000000 to 0xbfffffff, wherein the memory granules corresponding to the first sub-address space are the memory granules 4 and 8, and the memory granules 4 and 8 are normal components corresponding to the second address obtained according to the memory access. The number of normal memory particles corresponding to the first address is 6, and the data bit width of the obtained memory data access result is 48 bits based on the target memory access instruction comprising the first address. The number of normal memory particles corresponding to the second address is two, and based on a target memory access instruction comprising the second address, the data bit width of the memory data access result can be obtained to be 16 bits. And splicing the read data based on the two target access instructions to obtain 64-bit complete data, and returning the complete data to the processor.

In one embodiment, the memory component is a data line for transferring data between the memory granule and the memory controller. Correspondingly, step 205 may comprise the following sub-steps (sub-step 2057 to sub-step 2060):

in step 2057, the product of the address and the number of all data lines is obtained.

In the memory access operation process, the data bit number transmitted by one data line can be 1bit for one memory access operation. The first product of the memory access address and the number of all data lines is equal to the sum of the numbers of the data bits corresponding to all the memory addresses before the memory access address when the number of the data bits of the obtained memory data access result is equal to the number of the data bits before the fault for each memory address before the memory access address. The memory address before the memory address is from the initial address in the memory address space to the memory address between the memory addresses.

For example, the memory stripe includes 8 memory particles, and the number of data lines between each memory particle and the memory controller is 8, and then the number of all data lines is: 8×8=64.

If the address is 8, the number of addresses preceding the address is 8. The first product of the memory address and the number of all data lines is: 8X 64. Then, in the case that the number of data bits corresponding to the 8 memory addresses before the memory address is equal to 64, the sum of the number of data bits corresponding to the 8 memory addresses is: 8X 64.

In step 2058, the ratio of the product to the number of all normal data lines is obtained.

Under the condition of continuous storage, the ratio of the product of the memory address and the number of all data lines to the number of normal data lines is equivalent to the number of target addresses required under the condition that the number of data bits of the obtained memory data access result is equal to the number of data bits before failure when each memory address before the memory address performs memory access operation.

For example, there is a fault in the data lines of 3 memory particles in the 8 memory particles, where the number of faulty data lines of each memory particle is 2, and then the number of all faulty data lines is 6, and the number of all normal data lines is 58. The ratio of the product to the number of all normal data lines is: (8×64)% 58= 8.827. In the case of ensuring that the number of data bits of the 8 memory addresses preceding the memory address is equal to the number of data bits preceding the failure, the number of required target addresses is 8.827.

Sub-step 2059, determining a start address of the plurality of target addresses and a normal data line corresponding to the start address according to the ratio.

For example, an integer part of the ratio is determined as a start address of the target address, and a fraction part of the ratio is determined as a duty ratio of the number of data lines allocated to a previous memory address of the access address among normal data lines corresponding to the start address. According to the duty ratio, the number of data lines allocated to the previous memory address of the memory address can be obtained. The number of normal data lines is subtracted by the number of normal data lines to obtain the number of normal data lines corresponding to the initial address, and the data lines with the number equal to the number and positioned at the high position are used as the normal data lines corresponding to the initial address.

For example, in the foregoing embodiment, the calculated ratio is: (8×64)% 58= 8.827, the start address is 8, and the normal data line corresponding to the start address is: 58- (8×64)% 58=10.

In sub-step 2060, the number of all normal data lines corresponding to all target addresses is equal to the number of all data lines in the memory as an allocation policy, and other target addresses and normal data lines corresponding to each other target address are determined according to the starting address and the number of all normal data lines corresponding to the starting address.

And acquiring a first difference value of the number of all the data lines and the number of normal data lines corresponding to the initial address. And under the condition that the first difference value is smaller than or equal to the number of all the normal data lines, taking the next memory address of the initial address as a target address, selecting the normal data lines with the number equal to the first difference value from the normal data lines corresponding to the target address, and taking the normal data lines as the normal data lines corresponding to the target address. And under the condition that the first difference value is larger than the number of all normal data lines, taking the next memory address of the initial address as a target address, taking all normal data lines as normal data lines corresponding to the target address, taking the first difference value and the number of all normal data lines as a second difference value, and continuously determining the target address and the normal data lines corresponding to the target address until the number of all normal data lines corresponding to all target addresses is equal to the number of all data lines.

For example, in the foregoing embodiment, the calculated start address is 8, the number of data lines corresponding to the start address is 10, the number of all data lines in the memory is 64, and the number of normal data lines is 58. The first difference value between the number of all the data lines and the number of the normal data lines corresponding to the initial address is: 64-10=54, the first difference is smaller than the number 58 of normal data lines, and the next memory address (memory address 9) is used as the target address, and 54 normal data lines are selected from 58 normal data lines corresponding to the next memory address (memory address 9) to be used as the normal data lines corresponding to the target address 9. That is, the target addresses corresponding to the memory address 8 are the memory address 8 and the memory address 9, the number of normal data lines corresponding to the memory address 8 is 10, and the number of normal data lines corresponding to the memory address 9 is 54. Correspondingly, when the memory access address is 8, the memory controller acquires 10-bit data based on the memory address 8, acquires 54-bit data based on the memory address 9, splices to obtain 64-bit complete data and returns the 64-bit complete data to the processor.

For another example, the address is 9, the start address corresponding to the address is 9, the number of data lines corresponding to the start address is 4, the next memory address 10 is determined as the target address, 58 data lines are selected as normal data lines corresponding to the target address 10, the next memory address 11 is continuously determined as the target address, and 2 data lines are selected from the 58 data lines corresponding to the target address 11. That is, the target addresses corresponding to the memory address 9 are the memory address 9, the memory address 10 and the memory address 11, 4 normal data lines corresponding to the memory address 9, 58 normal data lines corresponding to the memory address 10, and 2 normal data lines corresponding to the memory address 11. Correspondingly, when the memory access address is 9, the memory controller acquires 4-bit data based on the memory address 9, acquires 58-bit data based on the memory address 10, acquires 2-bit data based on the memory address 11, and splices to obtain 64-bit complete data and returns the 64-bit complete data to the processor.

In one embodiment, the memory component is a data line for transferring data between the memory granule and the memory controller. The first address is a memory access address. Correspondingly, step 205 may further comprise the following sub-steps (sub-steps 2061 to 2062):

Sub-step 2061, obtaining a third address space visible to the processor and a fourth address space invisible to the processor in the memory address space.

When the processor generates the initial access instruction, the access address in the instruction is not allocated to the fourth address space. The fourth address space is visible to the memory controller, and therefore the memory controller may perform memory access operations based on addresses in the fourth address space. The ratio of the interval size of the third address space to the interval size of the fourth address space may be equal to the ratio of the number of normal data lines to the number of failed data lines, and the memory address is in the third address space. The memory address space visible to the processor and the memory address space invisible to the processor are described in the foregoing step 202, and are not described herein.

Sub-step 2062, converting the memory access to a second address according to an address space mapping scheme.

Specifically, the second address is in the fourth address space. For example, a preset address offset may be superimposed on the first address, converting the first address to a second address in the fourth address space.

In one embodiment, the memory component is a data line for transferring data between the memory granule and the memory controller. Step 205 may also include the following substeps (substep 2063 to substep 2064):

Substep 2063, selecting a predetermined number of normal data lines from all normal data lines.

For example, a predetermined number of normal data lines may be randomly selected from the normal data lines. The predetermined number of normal data lines may also be determined in a round robin allocation. For example, the address of the first initial access instruction is a, the second address obtained according to the address a is B, the number of normal data lines is 58, and the number of fault data lines is 6. The normal data lines corresponding to the second address B are determined to be the 1 st normal data line to the 6 th normal data line. And determining that the normal data line corresponding to the second address D is from the 7 th normal data line to the 14 th normal data line based on the second address obtained by the access address C as the access address C. Based on the next initial access instruction, the determined normal data lines corresponding to the second address are from the 15 th normal data line to the 21 st normal data line. And so on, realizing a round-robin distribution mode.

Substep 2064, determining the predetermined number of normal data lines as normal components corresponding to the second address.

For example, in the foregoing embodiment, the address of the first initial access instruction is a, and the normal data lines corresponding to the second address B are determined to be the 1 st normal data line to the 6 th normal data line according to the second address B obtained by the address a. The 1 st normal data line to the 6 th normal data line are based on the normal components corresponding to the second address. Under the condition that the memory component has a fault component, when the correct memory access data cannot be acquired, the memory access operation may fail, and the computer system cannot be started normally; or because the memory has stability problem, the memory can not work at design frequency, thereby affecting the performance of the computer system. The memory component faults may include memory particle faults, and may also include data line faults caused by uneven wiring of a circuit board (Printed Circuit Board, PCB).

In one embodiment, the memory component is a memory cell and the first address is a memory access address. Step 205 may also include the following substeps (substep 2065 to substep 2067):

Sub-step 2065, obtains a fifth address space visible to the processor and a sixth address space invisible to the processor in the memory address space.

Specifically, the size of the sixth address space is equal to the size of the preset address space, and the access address is in the fifth address space. The sixth address space is not visible to the processor, and the memory is not allocated to the sixth address space when the processor generates the initial memory access instruction. However, the sixth geological space is visible to the memory controller, and the memory controller may perform a corresponding memory access operation according to the address allocated to the sixth address space. Compared with the memory grain faults and the data line faults, the memory address range affected by the memory unit faults is relatively smaller. Although the memory address range is smaller, memory read-write errors may still be caused, so that a program running error or a crash phenomenon is caused.

Because the memory address range affected by the memory cell failure is relatively small, the preset address space size may be determined based on empirical data, for example, the preset address space size may be set to 4MB. An address space of a preset address space size is determined as a second address space invisible to the processor, and the address space of the other part is determined as a fifth address space visible to the processor.

The address space visible to the processor and the address space invisible to the processor are described in the foregoing step 202, and are not described herein.

Sub-step 2066, obtaining a failed memory address corresponding to the failed memory cell.

Each memory unit has a corresponding memory address, and after determining the failed memory unit, the corresponding memory address is determined as the failed memory address and stored in the address space mapping table.

Further, the address space mapping table may record the address of the failed memory unit, the granule number of the memory granule where the failed memory unit is located, the reserved memory address corresponding to the failed memory unit, and the granule number of the memory granule.

Sub-step 2067, converting the memory address to a second address according to the address space mapping scheme in the event that the memory address is equal to the failed memory address.

Wherein the second address is in the sixth address space.

Illustratively, the second address in the sixth address space is obtained by superimposing a preset address offset on the first address. For example, there may be multiple faulty memory units, and there may be multiple faulty memory addresses corresponding to the faulty memory units, where the address is equal to any faulty memory address, the address is converted into a second address according to the address space mapping scheme, where the second address is in the sixth address space.

In one embodiment, the memory component is a memory cell and the first address is a memory access address. Step 205 may include the following sub-steps (sub-steps 2068 to 2069):

sub-step 2068, selecting a predetermined number of normal memory cells from the normal memory cells corresponding to the second address. The preset number of normal memory units is a part of normal memory units corresponding to the second address.

Sub-step 2069, determining the selected predetermined number of normal memory cells as normal components corresponding to the second address.

And determining the preset number of normal memory units as normal components corresponding to the second address, wherein when the memory access operation is executed based on the target memory access instruction comprising the second address, the data of the preset number of normal memory units are used as part of the data of the memory access operation. The address of the faulty memory unit, the particle number of the memory particle where the faulty memory unit is located, the reserved memory address corresponding to the faulty memory unit, and the reserved particle number are recorded in an address space mapping table, and when the memory address is matched with the address of the faulty memory unit, the corresponding reserved memory address and reserved particle number are determined based on the information stored in the address space mapping table, the reserved address is determined as the second address, the memory address is determined as the first address, a plurality of target memory access instructions are obtained according to the two addresses, and the memory access operation is performed through the plurality of target memory access addresses. When the target access instruction is a write operation instruction, the write data is split and then written into the memory, and when the target access instruction is a read operation instruction, the read data is spliced and then returned to the processor. So that the system program can run in a state of shielding the memory cell from faults.

By dividing the memory address space into a fifth address space visible to the processor and a sixth address space invisible to the processor, a first address located in the fifth address space is converted into a second address located in the sixth address space in case the memory address is equal to a faulty memory address corresponding to a faulty memory location. And performing access operation based on the second address, which is equivalent to converting access operation of the faulty memory unit into access operation of the normal memory unit. Therefore, normal memory access operation is realized without replacing a fault memory unit, and the system can be ensured to work at the design frequency corresponding to the normal memory unit.

In one embodiment, prior to step 201, further comprising:

and step 208, executing test operation on the memory component in response to the memory component test instruction sent by the processor, and obtaining a test result.

The memory component test instruction may be a memory training instruction, a read-write operation instruction, or other test instructions that can test whether the memory component is in a normal working state.

Step 209, returning the test result to the processor, so that the processor can determine whether the memory component has a fault component according to the test result, and acquire the fault information of the fault component.

By way of example, the processor compares the test result with the expected result to obtain a comparison result, and determines whether a faulty component exists in the memory component according to the comparison result. For example, the fault information may be a component type of the faulty component, and the number of faulty components. For example, the component types may include: memory particles, data lines, memory cells, or other memory component types.

For example, the memory component test instruction is a read operation instruction, the expected result is data written into the memory, the test result is a read value obtained from the memory, the read value and the expected result are compared, and whether a fault component exists in the memory component is determined according to the comparison result.

By the embodiment, the memory controller can still provide a linear memory space for the processor under the condition that the memory particles have faults, the data lines have faults or the memory units have faults, so that the data bit width of the memory access data is ensured to be the same as the data bit width before the faults, and the system can work at the design frequency. The method of the embodiment can shield the memory fault to realize the normal start of the operating system and the normal running of the program, and can realize the parallel running of the processor verification and the memory optimization to accelerate the verification flow after plate making and film returning.

Fig. 6 is a frame diagram of a memory access system according to an embodiment of the present application, and referring to fig. 6, the system includes: processor core, memory controller, memory module, on-chip bus.

The memory controller includes a memory data access device, a control/calibration/physical layer (PHYSICAL LAYER, PHY), and an address resolution module. The memory access device for the memory data comprises: the system comprises a memory configuration interface, an address space mapping table, a request prefetching module and a data caching module. The memory module includes at least one memory particle. And a data line, a control line and an address line are connected between the control/calibration/physical layer and the memory module.

The memory access device for the memory data can still provide a linear memory space for the processor core under the condition that a memory unit is defective, or memory particles are defective, or a data line is defective, keep the data bit wide, ensure that the system works at a design frequency, support and shield the memory faults, realize the starting of an operating system and the running of a program, enable the processor verification and the memory optimization to be performed in parallel, and accelerate the verification flow after the plate-making and the plate-returning.

For example, the memory access device for memory data and its external interface are shown in the dashed box in fig. 6. The portion is integrated in a memory controller (DDRX controller IP), a memory controller hardware intellectual property (Intellectual Property, IP) core for controlling memory access and data transfer in a computer system, including the interface between the processor and the memory and related logic.

The memory access device of the memory data is externally connected with a Network on Chip (NoC) and internally connected with modules such as address analysis, control/calibration/physical layer and the like. The memory configuration interface supports the processor core to acquire quality information of each particle and each data line of the memory through the on-chip bus, and supports the processor core to write an address space mapping scheme capable of shielding memory faults into the address space mapping table. Wherein, the on-chip bus may be: AXI bus, CHI bus, tilelink bus, etc.

The address space mapping table is maintained by hardware, and when the program runs, each time the processor core sends a memory access request, the mapping table is searched through an on-chip bus, one request is split into a plurality of requests, and the requests are sent to the memory through a request pre-fetching module. The request pre-fetch module enables scheduling and pre-fetching of multiple requests. The data caching module splices the data returned by the plurality of read requests, returns the data to the processor core, and provides write data for the write request sent by the request pre-fetching module.

In this embodiment, by selecting the address space mapping scheme, part of the grains or part of the data lines or part of the memory units with poor signal quality are shielded, only the memory which can stably work at the design frequency is reserved, and a small memory system is constructed by using the memory grains or the data lines or the memory units, only the memory capacity is reduced, but the whole system can work at the design frequency. The memory access request sent by the processor core is split by searching the address space mapping table, and the data returned by a plurality of memory reading requests are combined, so that the data bit width of the memory accessed by the processor core is ensured, the whole memory system can stably work without adjusting parameters, and the system can also shield the memory fault operation.

The memory data access method of the present application is further exemplified in the following with reference to fig. 6 and 7. Referring to fig. 7, the method may include the steps of:

Step S1, host software obtains memory particles, data lines or memory unit information through a memory configuration interface, and selects an address space mapping scheme corresponding to a failed memory component.

And acquiring the memory grain, data line or memory unit information through a memory configuration interface to select different address space mapping schemes so as to shield the failed part of the memory grain, part of the data line or part of the memory unit. Specifically, configuration software of the processor is used, and a test result returned by the memory controller when the memory component test instruction is executed on the memory component is obtained through the memory configuration interface. And taking the test result as operation information capable of reflecting the operation state of the memory component, and determining whether the memory component has a fault component according to the test result.

Step S2, running a program through host software or an embedded processor, and filling in an address space mapping table through a memory configuration interface.

This step is described in the foregoing step 203, and will not be described here again.

Step S3, when the program runs, each time the host sends a memory access request, the address space mapping table is searched through the memory access interface, and one request is split into a plurality of requests.

The memory access request in this step corresponds to the initial access instruction in the foregoing embodiment, and the plurality of requests corresponds to the plurality of target access instructions in the foregoing embodiment. Specifically, the method of this step is described in the foregoing steps 204 to 206, and will not be repeated here.

And S4, when the program runs, scheduling and prefetching of a plurality of read-write requests are carried out through the request prefetching module, data returned by the plurality of read requests are spliced through the data caching module and returned to the host, and write data is provided for the write requests sent by the request prefetching module.

For example, the failed memory component is a memory granule, wherein 2 memory granules among 8 memory granules fail and cannot stably work at the design frequency, so that the effective memory capacity of the current memory module is 24G, and the effective data bit width of each access request is 48 bits.

After the software obtains the memory fault information, in order to ensure the data bit width of the memory access request of the processor core, firstly calculating that the visible memory space of the processor core of each particle is 24G/8=3G, the residual memory capacity of 6 available memory particles is (4G-3G) 6=6G, the part of memory capacity is invisible to the processor core, respectively distributing the part of memory space to 2 fault memory particles, calculating the memory address mapping relation and writing the memory address mapping relation into an address space mapping table.

Specifically, the processor checks that one read/write of the memory address (denoted as address a) in the initial memory instruction is converted into N reads/writes after being processed by the address space mapping table, where N is equal to the total number of grains divided by the number of available grains, and in this embodiment, the value of N is 2.

The address a of 6 available memory granules is read and written for the first time, and the address B of 2 available memory granules is read and written for the second time (address B corresponds to the target address in the foregoing embodiment). The calculation formula of the address B is as follows: a% (0 x 40000000) +0 xc0000000).

Meanwhile, to ensure that the write memory request only writes 2 available memory granules, the data mask (dm_n) signal of the other 4 memory granules needs to be configured to be valid, so that the memory granules mask the received write operation data. For memory particles which do not support data masks, more memory space is reserved for shielding faults, so that the accuracy requirement can be met.

It should be noted that, in the embodiment of the present application, a portion of the memory space is used for masking the memory access of the fault, if the memory capacity needs to be utilized to the maximum extent, the memory module is required to support the Data Mask (DM) function, otherwise, a portion of the memory capacity is wasted.

Such as the address space mapping scheme described above, as shown in fig. 5. The memory granules 3 and 6 cannot stably work at the design frequency, and the visible memory address range of the processor core is 0x 00000000-0 x bffffffff.

The processor checks that the first read-write of the address A is changed into the second read-write after being processed by the address space mapping table, and the first read-write of the address A of the memory granules 1, 2, 4, 5, 7 and 8. If the address A belongs to the address range 0x 00000000-0 x3fffffff, the address B of the memory granules 1 and 5 is read and written for the second time. If the address A belongs to the address range of 0x 40000000-0 x7fffffff, reading and writing the address B of the memory particles 2 and 7 for the second time; if the address A belongs to the address range 0x 80000000-0 x bffffffff, the address B of the memory granules 4, 8 is read and written for the second time.

The corresponding relation between the memory address range and the memory particles can be arbitrarily specified and recorded in the address space mapping table. It should be noted that the mapping relationship described in this paragraph is only an example. All data read by the data caching module are spliced and combined to the data bit width required by the processor core, and then returned to the processor core. In this embodiment, the data corresponding to the write-once request of the processor core is split into the data of 2 write-once requests and sent to the memory.

Compared with the memory address corresponding to the memory grain when the memory grain fails, the memory address corresponding to the grain can still be accessed when part of the data lines fail, and the returned effective data bit width is reduced. Assuming that 3 of the 8 memory granules each have 2 data line failures, the effective data bit width of each memory access request is 58 bits.

An address mapping scheme is to consider the data bit width of one memory address storable as 58 bits and store the data continuously, transform each memory address of a processor core, split and splice each memory data. For example, the processor core reads 64 bits of address addr=8, and becomes read memory addresses 8 and 9 after address mapping. The calculation formula of the address mapping is as follows: addr x 64/58 is rounded down again to obtain the memory address of the first read.

The method for calculating the number of times of reading the memory comprises the following steps: if 64- (58- (addr x 64)% 58) >58, then read 3 times memory, otherwise read 2 times memory. The rule of read data splicing is as follows: the high 58- (8 x 64)% 58=10 bits of the read memory address 8 are selected and the low 64- (58- (8 x 64)% 58) =54 bits of the read memory address 9 are concatenated into 64 bits for return to the processor core. Similarly, the 64 bits of the processor core read address 9 are changed into read memory addresses 9, 10 and 11 after address mapping, and the data buffer module splices the upper 4 bits of the read memory address 9, the 58 bits of the read memory address 10 and the lower 2 bits of the read memory address 11 into 64 bits and sends the 64 bits back to the processor core.

Another address mapping scheme is to similarly mask part of the memory grain faults, reserve a memory space invisible to the processor core, read and write access memory each time, and supplement the insufficient data bit width by reading and writing the reserved memory address space once. In order to save the memory space, the allocation of the grain number and the address can be performed in a round-robin manner, that is, the same reserved memory address can be read and written by supplementing the bit width of the read-write data for several times, and only the grain or the data line is selected to be different.

Compared with the memory grain faults and the data line faults, the memory address range which can be affected by partial memory unit faults is relatively smaller, but memory read-write errors are possibly caused, so that program operation errors or processor core halt are caused.

The address space mapping scheme for masking part of the memory unit faults can reserve a smaller memory address space (for example, 4MB of each granule) invisible to the processor core, and the address space mapping table records the addresses of the faulty memory units, the granule numbers, and the reserved memory addresses and the granule numbers corresponding to the addresses. When the processor core sends 1 read-write request, if the corresponding item is matched in the address space mapping table, splitting into 2 read-write requests to access the memory, splitting the written data, and splicing the read-back data; if no corresponding item exists in the address space mapping table, the fault shielding access function is closed, the read-write request of the on-chip bus is directly transmitted to the memory controller IP, and the read-write data is also directly transmitted.

Referring to fig. 8, an apparatus 30 for accessing memory data according to an embodiment of the present application includes: an acquiring module 301, configured to acquire fault information of a memory component; a configuration module 302, configured to configure an address space mapping scheme for fault information; the extracting module 303 is configured to respond to an initial access instruction sent by the processor, and extract an access address in the initial access instruction; the mapping processing module 304 is configured to obtain a plurality of target addresses corresponding to the access addresses according to the access addresses and the address space mapping scheme; the instruction splitting module 305 is configured to split the initial memory access instruction into a plurality of target memory access instructions according to a plurality of target addresses; the target access instruction corresponds to the target address one by one; the first execution module 306 is configured to execute, by using the memory controller, a target access instruction, so as to write split data obtained after splitting the write data sent by the processor, into a target address; the read data read from the target address is spliced and then returned to the processor.

Optionally, the configuration module 302 may include: the first configuration submodule is used for configuring an address space mapping scheme aiming at fault information through a software program; wherein the software program runs on an embedded processor added in the memory controller or in firmware added in the processor core.

Optionally, the apparatus 30 further comprises: and the writing module is used for writing the address space mapping scheme into the address space mapping table through the memory configuration interface after the address space mapping scheme is configured for the fault information. Correspondingly, the mapping processing module 304 may include: the first obtaining sub-module is used for obtaining a plurality of target addresses corresponding to the access memory address according to the access memory address and the address space mapping scheme recorded in the address space mapping table.

Optionally, the first execution module 306 may include: the second acquisition sub-module is used for splicing the read data read from the target address to obtain spliced data; the third acquisition sub-module is used for performing error checking and correction technical processing on the spliced data to obtain processed spliced data; and the return sub-module is used for returning the processed spliced data to the processor.

Alternatively, the mapping processing module 304 may include: a fourth obtaining sub-module, configured to convert, in a case where a faulty component exists in at least a portion of memory components in the memory, the memory address into a first address and a second address according to a memory address and an address space mapping scheme; the first address is used for acquiring data of all normal components in the memory component, and the second address is used for acquiring data of a preset number of normal components in all normal components; the preset number is equal to the number of failed components.

Optionally, in the case that the memory component is a memory granule, the first address is a memory address, and the mapping processing module 304 may include: a fifth acquisition sub-module for acquiring a first address space visible to the processor and a second address space invisible to the processor in the memory address space; the ratio of the interval size of the first address space to the interval size of the second address space is equal to the ratio of the total memory capacity of all normal memory particles to the total memory capacity of all fault memory particles; the access memory address is an address in the first address space; the first conversion sub-module is used for converting the access memory address into a second address according to the address space mapping scheme, and the second address is in the second address space.

Alternatively, in the case where the number of failed memory particles is smaller than the number of normal memory particles, the mapping processing module 304 may include: a sixth obtaining sub-module, configured to obtain a plurality of first sub-address spaces included in the first address space; the first sub-address space corresponds to a preset number of normal memory particles; the first determining sub-module is used for determining a target first sub-address space in which the access address is located from a plurality of first sub-address spaces; and the second determining submodule is used for determining the normal memory particles corresponding to the target first subaddress space as normal components corresponding to the second address.

Optionally, where the memory component is a data line, and the data line is used to transfer data between the memory granule and the memory controller, the mapping processing module 304 may include: a seventh obtaining sub-module, configured to obtain a product of the memory address and the number of all data lines; an eighth obtaining sub-module, configured to obtain a ratio of the product to the number of all normal data lines; the third determining submodule is used for determining a starting address in a plurality of target addresses and a normal data line corresponding to the starting address according to the ratio; and the fourth determining submodule is used for determining other target addresses and normal data lines corresponding to each other target address according to the starting address and the number of all normal data lines corresponding to the starting address by taking the number of all normal data lines corresponding to all target addresses as an allocation strategy, wherein the number of all normal data lines is equal to the number of all data lines in the memory.

Optionally, the memory component is a data line, and the first address is a memory address when the data line is used for transmitting data between the memory granule and the memory controller; the mapping processing module 304 may include: a ninth acquiring submodule, configured to acquire a third address space visible to the processor and a fourth address space invisible to the processor in the memory address space; the ratio of the interval size of the third address space to the interval size of the fourth address space is equal to the ratio of the number of normal data lines to the number of fault data lines, and the memory access is in the third address space; and the second conversion sub-module is used for converting the access memory address into a second address according to the address space mapping scheme, and the second address is in a fourth address space.

Alternatively, the mapping processing module 304 may include: the first selecting sub-module is used for selecting a preset number of normal data lines from all the normal data lines; and a fifth determining sub-module for determining a preset number of normal data lines as normal components corresponding to the second address.

Alternatively, in the case where the memory component is a memory unit in a memory granule, the first address is a memory address, and the mapping processing module 304 may include: a tenth obtaining sub-module, configured to obtain, in a memory address space, a fifth address space visible to the processor, and a sixth address space invisible to the processor, where a size of the sixth address space is equal to a size of a preset address space, and the memory access is in the fifth address space; an eleventh obtaining sub-module, configured to obtain a faulty memory address corresponding to the faulty memory unit; and the third conversion sub-module is used for converting the access memory address into a second address according to the address space mapping scheme under the condition that the access memory address is equal to the fault memory address, and the second address is in a sixth address space.

Alternatively, the mapping processing module 304 may include: the second selecting submodule is used for selecting a preset number of normal memory units from the normal memory units corresponding to the second address; and a sixth determining sub-module, configured to determine the selected preset number of normal memory units as normal components corresponding to the second address.

Optionally, the apparatus 30 further comprises: the second execution module is used for responding to the memory component test instruction sent by the processor and executing read-write operation on the memory component before responding to the initial memory access instruction sent by the processor and extracting the memory access address in the initial memory access instruction to obtain a test result; and the return module is used for returning the test result to the processor so that the processor can determine whether the memory component has the fault component according to the test result and acquire the fault information of the fault component.

According to the embodiment, the memory component does not need to be replaced, the memory failure is not required to be solved by reducing the working frequency of the memory and adjusting the memory parameters, the signal integrity problem caused by uneven PCB wiring can be avoided under the condition that the memory component fails, the damage of the board card caused by replacing memory particles can be avoided, and the memory can be ensured to work at the design frequency.

Fig. 9 is a block diagram of an electronic device 400, according to an example embodiment. For example, electronic device 400 may be a computer, tablet device, personal digital assistant, or the like. Referring to fig. 9, an electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input/output (I/O) interface 412, a sensor component 414, and a communication component 416.

The processing component 402 generally controls the overall operation of the electronic device 400. The processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 402 can include one or more modules that facilitate interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402. Memory 404 is used to store various types of data to support operations at electronic device 400.

The power supply component 406 provides power to the various components of the electronic device 400. The power components 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 400. The multimedia component 408 includes a screen between the electronic device 400 and the user that provides an output interface. The audio component 410 is for outputting and/or inputting audio signals. I/O interface 412 provides an interface between processing component 402 and peripheral interface modules. The sensor assembly 414 includes one or more sensors for providing status assessment of various aspects of the electronic device 400. The communication component 416 is used to facilitate communication between the electronic device 400 and other devices, either wired or wireless. The electronic device 400 may access a wireless network based on a communication standard.

Optionally, a non-transitory computer readable storage medium comprising instructions, such as memory 404 comprising instructions, executable by processor 420 of electronic device 400 to perform the above-described method is also provided. .

Fig. 10 is a block diagram of an electronic device 500, according to an example embodiment. For example, electronic device 500 may be provided as a server. Referring to fig. 10, electronic device 500 includes a processing component 522 that further includes one or more processors and memory resources represented by memory 532 for storing instructions, such as applications, executable by processing component 522. The application programs stored in the memory 532 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform a method for accessing memory data according to an embodiment of the present application.

The electronic device 500 may also include a power component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input output (I/O) interface 555. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.

The embodiment of the application also provides a computer program product, which comprises a computer program, and the memory data access method is realized when the computer program is executed by a processor.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

The foregoing is only illustrative of the present application and is not to be construed as limiting thereof, but rather as various modifications, equivalent arrangements, improvements, etc., within the spirit and principles of the present application. The above detailed description of the memory data access method, the device, the electronic equipment and the readable storage medium provided by the application applies specific examples to illustrate the principles and the implementation of the application, and the above description of the examples is only used to help understand the method and the core idea of the application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the idea of the present application, the present disclosure should not be construed as limiting the present application in summary.

Claims

1. The access method of the memory data is characterized by comprising the following steps:

Acquiring fault information of a memory component;

configuring an address space mapping scheme for the fault information;

Responding to an initial access instruction sent by a processor, and extracting an access address in the initial access instruction;

acquiring a plurality of target addresses corresponding to the access address according to the access address and the address space mapping scheme;

Splitting the initial access instruction into a plurality of target access instructions according to a plurality of target addresses; the target access instruction corresponds to the target address one by one;

executing the target access instruction through a memory controller to write split data obtained after splitting write data sent by the processor into the target address; and splicing the read data read from the target address, and returning to the processor.

2. The method of claim 1, wherein configuring an address space mapping scheme for the fault information comprises:

configuring the address space mapping scheme for the fault information through a software program;

wherein the software program runs on an embedded processor added in the memory controller or in firmware added in a processor core.

3. The method of claim 2, further comprising, after configuring an address space mapping scheme for the fault information:

writing the address space mapping scheme into an address space mapping table through a memory configuration interface;

the obtaining, according to the address and the address space mapping scheme, a plurality of target addresses corresponding to the address includes:

and acquiring a plurality of target addresses corresponding to the access memory address according to the access memory address and the address space mapping scheme recorded in the address space mapping table.

4. The method of claim 1, wherein the concatenating read data read from the target address and then returning to the processor comprises:

splicing the read data read from the target address to obtain spliced data;

Performing error checking and correcting technical treatment on the spliced data to obtain the treated spliced data;

and returning the processed spliced data to the processor.

5. The method of claim 1, wherein the obtaining a plurality of target addresses corresponding to the address according to the address space mapping scheme and the address space mapping scheme comprises:

Under the condition that a fault component exists in at least part of memory components in the memory, converting the memory access into a first address and a second address according to the memory access and the address space mapping scheme;

The first address is used for acquiring data of all normal components in the memory components, and the second address is used for acquiring data of a preset number of normal components in all the normal components; the preset number is equal to the number of the fault components.

6. The method of claim 5, wherein the first address is the address if the memory component is a memory granule, the obtaining a plurality of target addresses corresponding to the address according to the address and the address space mapping scheme comprises:

Acquiring a first address space visible to the processor and a second address space invisible to the processor in a memory address space; the ratio of the interval size of the first address space to the interval size of the second address space is equal to the ratio of the total memory capacity of all normal memory particles to the total memory capacity of all fault memory particles; the access address is an address in the first address space;

And converting the access memory address into the second address according to the address space mapping scheme, wherein the second address is in the second address space.

7. The method of claim 6, wherein, in the case that the number of failed memory particles is smaller than the number of normal memory particles, the obtaining, according to the address and address space mapping scheme, a plurality of destination addresses corresponding to the address includes:

acquiring a plurality of first sub-address spaces included in the first address space; the first sub-address space corresponds to the preset number of normal memory particles;

determining a target first sub-address space in which the access address is located from a plurality of first sub-address spaces;

And determining the normal memory particles corresponding to the target first sub-address space as normal components corresponding to the second address.

8. The method of claim 5, wherein, in the case where the memory component is a data line, the data line is used to transfer data between a memory granule and the memory controller, the obtaining, according to the address and the address space mapping scheme, a plurality of destination addresses corresponding to the address includes:

obtaining the product of the memory access and the number of all the data lines;

Acquiring the ratio of the product to the number of all normal data lines;

determining a starting address in a plurality of target addresses and a normal data line corresponding to the starting address according to the ratio;

and determining other target addresses and normal data lines corresponding to each other target address according to the starting address and the number of all normal data lines corresponding to the starting address by taking the number of all normal data lines corresponding to all target addresses and the number of all data lines which are equal to the number of all data lines in a memory as an allocation strategy.

9. The method of claim 5, wherein the first address is the memory address if the memory component is a data line for transferring data between a memory granule and the memory controller; the obtaining, according to the address and the address space mapping scheme, a plurality of target addresses corresponding to the address includes:

Acquiring a third address space visible to the processor and a fourth address space invisible to the processor in a memory address space; the ratio of the interval size of the third address space to the interval size of the fourth address space is equal to the ratio of the number of normal data lines to the number of fault data lines, and the access address is in the third address space;

And converting the access memory address into the second address according to the address space mapping scheme, wherein the second address is in the fourth address space.

10. The method of claim 9, wherein the obtaining a plurality of target addresses corresponding to the address according to the address space mapping scheme and the address space mapping scheme comprises:

Selecting the normal data lines with the preset number from all the normal data lines;

And determining the normal data lines with the preset number as normal components corresponding to the second address.

11. The method of claim 5, wherein the first address is the address if the memory component is a memory unit in a memory granule, the obtaining a plurality of destination addresses corresponding to the address according to the address and the address space mapping scheme comprises:

Acquiring a fifth address space visible to the processor and a sixth address space invisible to the processor in a memory address space, wherein the size of the sixth address space is equal to the size of a preset address space, and the memory address is in the fifth address space;

acquiring a fault memory address corresponding to a fault memory unit;

and under the condition that the access memory address is equal to the fault memory address, converting the access memory address into the second address according to the address space mapping scheme, wherein the second address is in the sixth address space.

12. The method of claim 11, wherein the obtaining a plurality of target addresses corresponding to the address according to the address space mapping scheme and the address space mapping scheme comprises:

Selecting the normal memory units with the preset number from the normal memory units corresponding to the second address;

And determining the selected normal memory units with the preset number as normal components corresponding to the second address.

13. The method of claim 1, wherein prior to fetching a memory address in an initial memory instruction in response to the initial memory instruction sent by a processor, further comprising:

responding to a memory component test instruction sent by the processor, and executing read-write operation on the memory component to obtain a test result;

And returning the test result to the processor so that the processor can determine whether a fault component exists in the memory component according to the test result and acquire the fault information of the fault component.

14. An apparatus for accessing memory data, the apparatus comprising:

the acquisition module is used for acquiring fault information of the memory component;

The configuration module is used for configuring an address space mapping scheme aiming at the fault information;

the extraction module is used for responding to an initial access instruction sent by the processor and extracting an access address in the initial access instruction;

The mapping processing module is used for acquiring a plurality of target addresses corresponding to the access address according to the access address and the address space mapping scheme;

the instruction splitting module is used for splitting the initial memory access instruction into a plurality of target memory access instructions according to a plurality of target addresses; the target access instruction corresponds to the target address one by one;

The first execution module is used for executing the target access instruction through the memory controller so as to write split data obtained after splitting the write data sent by the processor into the target address; and splicing the read data read from the target address, and returning to the processor.

15. An electronic device, comprising: a processor;

A memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 13.

16. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1 to 13.