JP2014534506A5 - - Google Patents

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Publication number
JP2014534506A5
JP2014534506A5 JP2014534728A JP2014534728A JP2014534506A5 JP 2014534506 A5 JP2014534506 A5 JP 2014534506A5 JP 2014534728 A JP2014534728 A JP 2014534728A JP 2014534728 A JP2014534728 A JP 2014534728A JP 2014534506 A5 JP2014534506 A5 JP 2014534506A5
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JP
Japan
Prior art keywords
interrupt
core
interrupt controller
level
controller
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Application number
JP2014534728A
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English (en)
Japanese (ja)
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JP2014534506A (ja
JP5847949B2 (ja
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Priority claimed from US13/252,670 external-priority patent/US8972642B2/en
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Publication of JP2014534506A publication Critical patent/JP2014534506A/ja
Publication of JP2014534506A5 publication Critical patent/JP2014534506A5/ja
Application granted granted Critical
Publication of JP5847949B2 publication Critical patent/JP5847949B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014534728A 2011-10-04 2012-10-04 マルチスレッドプロセッサとの低待ち時間２レベル割込みコントローラインターフェース Expired - Fee Related JP5847949B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/252,670 2011-10-04
US13/252,670 US8972642B2 (en) 2011-10-04 2011-10-04 Low latency two-level interrupt controller interface to multi-threaded processor
PCT/US2012/058780 WO2013052684A2 (en) 2011-10-04 2012-10-04 Low latency two-level interrupt controller interface to multi-threaded processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2015229471A Division JP6153991B2 (ja) 2011-10-04 2015-11-25 マルチスレッドプロセッサとの低待ち時間２レベル割込みコントローラインターフェース

Publications (3)

Publication Number Publication Date
JP2014534506A JP2014534506A (ja) 2014-12-18
JP2014534506A5 true JP2014534506A5 (enExample) 2015-05-07
JP5847949B2 JP5847949B2 (ja) 2016-01-27

Family

ID=47172881

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2014534728A Expired - Fee Related JP5847949B2 (ja) 2011-10-04 2012-10-04 マルチスレッドプロセッサとの低待ち時間２レベル割込みコントローラインターフェース
JP2015229471A Expired - Fee Related JP6153991B2 (ja) 2011-10-04 2015-11-25 マルチスレッドプロセッサとの低待ち時間２レベル割込みコントローラインターフェース

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2015229471A Expired - Fee Related JP6153991B2 (ja) 2011-10-04 2015-11-25 マルチスレッドプロセッサとの低待ち時間２レベル割込みコントローラインターフェース

Country Status (6)

Country Link
US (1) US8972642B2 (enExample)
EP (1) EP2764442B1 (enExample)
JP (2) JP5847949B2 (enExample)
KR (1) KR101563576B1 (enExample)
CN (1) CN103874990B (enExample)
WO (1) WO2013052684A2 (enExample)

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US9110830B2 (en) * 2012-01-18 2015-08-18 Qualcomm Incorporated Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods
US10394730B2 (en) * 2014-11-14 2019-08-27 Cavium, Llc Distributed interrupt scheme in a multi-processor system
US10067892B2 (en) * 2015-03-06 2018-09-04 Microchip Technology Incorporated Microcontroller or microprocessor with dual mode interrupt
US11630789B2 (en) * 2020-09-11 2023-04-18 Apple Inc. Scalable interrupts
US11507414B2 (en) 2020-11-25 2022-11-22 Cadence Design Systems, Inc. Circuit for fast interrupt handling
US12020066B2 (en) 2021-06-11 2024-06-25 International Busin ess Machines Corporation Asynchronous completion notification in a multi-core data processing system
US11755362B2 (en) 2021-06-11 2023-09-12 International Business Machines Corporation Techniques for handling escalation of interrupts in a data processing system
US11645215B2 (en) 2021-06-11 2023-05-09 International Business Machines Corporation Efficient selection of a particular processor thread for handling an interrupt

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