KR101563576B1 - 다중 스레드 프로세서에 대한 저 레이턴시 2 레벨 인터럽트 제어기 인터페이스 - Google Patents

다중 스레드 프로세서에 대한 저 레이턴시 2 레벨 인터럽트 제어기 인터페이스 Download PDF

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KR101563576B1
KR101563576B1 KR1020147012326A KR20147012326A KR101563576B1 KR 101563576 B1 KR101563576 B1 KR 101563576B1 KR 1020147012326 A KR1020147012326 A KR 1020147012326A KR 20147012326 A KR20147012326 A KR 20147012326A KR 101563576 B1 KR101563576 B1 KR 101563576B1
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interrupt
core
interrupt controller
controller
level
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KR20140082787A (ko
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수레쉬 케이. 벤쿠마한티
루시안 코드레스쿠
에리히 제임스 프론드케
수펑 첸
페이신 총
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Human Computer Interaction (AREA)
KR1020147012326A 2011-10-04 2012-10-04 다중 스레드 프로세서에 대한 저 레이턴시 2 레벨 인터럽트 제어기 인터페이스 Expired - Fee Related KR101563576B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/252,670 2011-10-04
US13/252,670 US8972642B2 (en) 2011-10-04 2011-10-04 Low latency two-level interrupt controller interface to multi-threaded processor
PCT/US2012/058780 WO2013052684A2 (en) 2011-10-04 2012-10-04 Low latency two-level interrupt controller interface to multi-threaded processor

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KR20140082787A KR20140082787A (ko) 2014-07-02
KR101563576B1 true KR101563576B1 (ko) 2015-10-27

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US (1) US8972642B2 (enExample)
EP (1) EP2764442B1 (enExample)
JP (2) JP5847949B2 (enExample)
KR (1) KR101563576B1 (enExample)
CN (1) CN103874990B (enExample)
WO (1) WO2013052684A2 (enExample)

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US10067892B2 (en) * 2015-03-06 2018-09-04 Microchip Technology Incorporated Microcontroller or microprocessor with dual mode interrupt
US11630789B2 (en) * 2020-09-11 2023-04-18 Apple Inc. Scalable interrupts
US11507414B2 (en) 2020-11-25 2022-11-22 Cadence Design Systems, Inc. Circuit for fast interrupt handling
US12020066B2 (en) 2021-06-11 2024-06-25 International Busin ess Machines Corporation Asynchronous completion notification in a multi-core data processing system
US11755362B2 (en) 2021-06-11 2023-09-12 International Business Machines Corporation Techniques for handling escalation of interrupts in a data processing system
US11645215B2 (en) 2021-06-11 2023-05-09 International Business Machines Corporation Efficient selection of a particular processor thread for handling an interrupt

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US20010052043A1 (en) 1997-12-10 2001-12-13 Stephen S. Pawlowski System and apparatus including lowest priority logic to select a processor to receive an interrupt message

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US8972642B2 (en) 2015-03-03
WO2013052684A3 (en) 2013-06-20
JP2014534506A (ja) 2014-12-18
JP2016095855A (ja) 2016-05-26
CN103874990B (zh) 2016-08-17
JP6153991B2 (ja) 2017-06-28
US20130086290A1 (en) 2013-04-04
EP2764442B1 (en) 2016-01-20
EP2764442A2 (en) 2014-08-13
KR20140082787A (ko) 2014-07-02
JP5847949B2 (ja) 2016-01-27
WO2013052684A2 (en) 2013-04-11
CN103874990A (zh) 2014-06-18

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