IT1308343B1 - Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessore - Google Patents
Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessoreInfo
- Publication number
- IT1308343B1 IT1308343B1 IT1999MI000205A ITMI990205A IT1308343B1 IT 1308343 B1 IT1308343 B1 IT 1308343B1 IT 1999MI000205 A IT1999MI000205 A IT 1999MI000205A IT MI990205 A ITMI990205 A IT MI990205A IT 1308343 B1 IT1308343 B1 IT 1308343B1
- Authority
- IT
- Italy
- Prior art keywords
- arbitrate
- peripherals
- procedure
- based system
- microprocessor based
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Hardware Redundancy (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT1999MI000205A IT1308343B1 (it) | 1999-02-03 | 1999-02-03 | Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessore |
US09/490,961 US6470407B1 (en) | 1999-02-03 | 2000-01-24 | Method for arbitrating interrupt priorities among peripherals in a microprocessor-based system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT1999MI000205A IT1308343B1 (it) | 1999-02-03 | 1999-02-03 | Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessore |
Publications (2)
Publication Number | Publication Date |
---|---|
ITMI990205A1 ITMI990205A1 (it) | 2000-08-03 |
IT1308343B1 true IT1308343B1 (it) | 2001-12-11 |
Family
ID=11381735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT1999MI000205A IT1308343B1 (it) | 1999-02-03 | 1999-02-03 | Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessore |
Country Status (2)
Country | Link |
---|---|
US (1) | US6470407B1 (it) |
IT (1) | IT1308343B1 (it) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6738845B1 (en) * | 1999-11-05 | 2004-05-18 | Analog Devices, Inc. | Bus architecture and shared bus arbitration method for a communication device |
US6694398B1 (en) * | 2001-04-30 | 2004-02-17 | Nokia Corporation | Circuit for selecting interrupt requests in RISC microprocessors |
KR100477641B1 (ko) * | 2002-01-15 | 2005-03-23 | 삼성전자주식회사 | 버스 시스템 및 그 데이터 전송경로 결정방법 |
JP4178809B2 (ja) * | 2002-02-21 | 2008-11-12 | ソニー株式会社 | 外部接続機器及びホスト機器 |
US20050021894A1 (en) * | 2003-07-24 | 2005-01-27 | Renesas Technology America, Inc. | Method and system for interrupt mapping |
US7363407B2 (en) * | 2003-09-29 | 2008-04-22 | Microsoft Corporation | Concurrent arbitration of multidimensional requests for interrupt resources |
US20050114415A1 (en) * | 2003-11-24 | 2005-05-26 | Texas Instruments Incorporated | Low-latency circular priority selector |
US20070027485A1 (en) * | 2005-07-29 | 2007-02-01 | Kallmyer Todd A | Implantable medical device bus system and method |
JP2008130056A (ja) * | 2006-11-27 | 2008-06-05 | Renesas Technology Corp | 半導体回路 |
JP5215655B2 (ja) * | 2007-12-27 | 2013-06-19 | ルネサスエレクトロニクス株式会社 | データ処理装置及びデータ処理装置におけるバスアクセス制御方法 |
FI20085050A0 (fi) * | 2008-01-21 | 2008-01-21 | Nokia Corp | Laite ja menetelmä |
US8972642B2 (en) * | 2011-10-04 | 2015-03-03 | Qualcomm Incorporated | Low latency two-level interrupt controller interface to multi-threaded processor |
CN111506531B (zh) * | 2020-03-27 | 2023-06-02 | 上海赛昉科技有限公司 | 一种easy-master微码模块及其配置方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4041469A (en) * | 1974-12-13 | 1977-08-09 | Pertec Corporation | CRT key station which is responsive to centralized control |
DE69114321T2 (de) * | 1990-02-20 | 1996-07-18 | Nippon Electric Co | Zum Durchführen der Unterbrechungsverschachtelungsfunktion geeignetes Unterbrechungssteuerungsgerät. |
US5859623A (en) * | 1996-05-14 | 1999-01-12 | Proxima Corporation | Intelligent display system presentation projection arrangement and method of using same |
-
1999
- 1999-02-03 IT IT1999MI000205A patent/IT1308343B1/it active
-
2000
- 2000-01-24 US US09/490,961 patent/US6470407B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ITMI990205A1 (it) | 2000-08-03 |
US6470407B1 (en) | 2002-10-22 |
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