CN103874990B - 到多线程处理器的低等待时间两级中断控制器接口 - Google Patents

到多线程处理器的低等待时间两级中断控制器接口 Download PDF

Info

Publication number
CN103874990B
CN103874990B CN201280048379.2A CN201280048379A CN103874990B CN 103874990 B CN103874990 B CN 103874990B CN 201280048379 A CN201280048379 A CN 201280048379A CN 103874990 B CN103874990 B CN 103874990B
Authority
CN
China
Prior art keywords
interrupt
core
control unit
interrupt controller
interrupts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280048379.2A
Other languages
English (en)
Chinese (zh)
Other versions
CN103874990A (zh
Inventor
苏雷什·K·文库马汉提
卢西恩·科德雷斯库
埃里克·詹姆斯·普隆迪克
陈旭峰
培鑫·钟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN103874990A publication Critical patent/CN103874990A/zh
Application granted granted Critical
Publication of CN103874990B publication Critical patent/CN103874990B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Human Computer Interaction (AREA)
CN201280048379.2A 2011-10-04 2012-10-04 到多线程处理器的低等待时间两级中断控制器接口 Active CN103874990B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/252,670 2011-10-04
US13/252,670 US8972642B2 (en) 2011-10-04 2011-10-04 Low latency two-level interrupt controller interface to multi-threaded processor
PCT/US2012/058780 WO2013052684A2 (en) 2011-10-04 2012-10-04 Low latency two-level interrupt controller interface to multi-threaded processor

Publications (2)

Publication Number Publication Date
CN103874990A CN103874990A (zh) 2014-06-18
CN103874990B true CN103874990B (zh) 2016-08-17

Family

ID=47172881

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280048379.2A Active CN103874990B (zh) 2011-10-04 2012-10-04 到多线程处理器的低等待时间两级中断控制器接口

Country Status (6)

Country Link
US (1) US8972642B2 (enExample)
EP (1) EP2764442B1 (enExample)
JP (2) JP5847949B2 (enExample)
KR (1) KR101563576B1 (enExample)
CN (1) CN103874990B (enExample)
WO (1) WO2013052684A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8972642B2 (en) * 2011-10-04 2015-03-03 Qualcomm Incorporated Low latency two-level interrupt controller interface to multi-threaded processor
US9110830B2 (en) * 2012-01-18 2015-08-18 Qualcomm Incorporated Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods
US10394730B2 (en) * 2014-11-14 2019-08-27 Cavium, Llc Distributed interrupt scheme in a multi-processor system
US10067892B2 (en) * 2015-03-06 2018-09-04 Microchip Technology Incorporated Microcontroller or microprocessor with dual mode interrupt
US11630789B2 (en) * 2020-09-11 2023-04-18 Apple Inc. Scalable interrupts
US11507414B2 (en) 2020-11-25 2022-11-22 Cadence Design Systems, Inc. Circuit for fast interrupt handling
US12020066B2 (en) 2021-06-11 2024-06-25 International Busin ess Machines Corporation Asynchronous completion notification in a multi-core data processing system
US11755362B2 (en) 2021-06-11 2023-09-12 International Business Machines Corporation Techniques for handling escalation of interrupts in a data processing system
US11645215B2 (en) 2021-06-11 2023-05-09 International Business Machines Corporation Efficient selection of a particular processor thread for handling an interrupt

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4420806A (en) * 1981-01-15 1983-12-13 Harris Corporation Interrupt coupling and monitoring system
US5555420A (en) * 1990-12-21 1996-09-10 Intel Corporation Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management
US5805841A (en) * 1991-07-24 1998-09-08 Micron Electronics, Inc. Symmetric parallel multi-processing bus architeture
US5367689A (en) * 1992-10-02 1994-11-22 Compaq Computer Corporation Apparatus for strictly ordered input/output operations for interrupt system integrity
US5530872A (en) * 1992-12-23 1996-06-25 International Business Machines Corporation Method and system for directing device driver to service multiple sequential interrupt requests generated by I/O device connected thereto
DE19501674A1 (de) * 1994-02-03 1995-08-10 Tektronix Inc Verwaltung der Datenübertragung zwischen Prozessoren
DE4406094C2 (de) 1994-02-25 2000-04-13 Lp Elektronik Gmbh Vorrichtung zum Betrieb einer Steuerungsanwendung
US5745772A (en) 1996-08-02 1998-04-28 Micron Electronics, Inc. Advanced programmable interrupt controller
US5944809A (en) * 1996-08-20 1999-08-31 Compaq Computer Corporation Method and apparatus for distributing interrupts in a symmetric multiprocessor system
US5905897A (en) * 1997-03-20 1999-05-18 Industrial Technology Research Institute Method and apparatus for selecting a nonblocked interrupt request
US6418496B2 (en) * 1997-12-10 2002-07-09 Intel Corporation System and apparatus including lowest priority logic to select a processor to receive an interrupt message
US6356354B1 (en) * 1998-09-18 2002-03-12 Hewlett-Packard Co. System having an arithmetic-logic circuit for determining the maximum or minimum of a plurality of codes
IT1308343B1 (it) * 1999-02-03 2001-12-11 St Microelectronics Srl Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessore
US6477600B1 (en) * 1999-06-08 2002-11-05 Intel Corporation Apparatus and method for processing isochronous interrupts
JP3769428B2 (ja) * 1999-09-30 2006-04-26 富士通株式会社 浮動割込みを保留できる情報処理装置および割込み条件変更命令実行方法
US6662297B1 (en) * 1999-12-30 2003-12-09 Intel Corporation Allocation of processor bandwidth by inserting interrupt servicing instructions to intervene main program in instruction queue mechanism
US6772241B1 (en) * 2000-09-29 2004-08-03 Intel Corporation Selective interrupt delivery to multiple processors having independent operating systems
US20040111593A1 (en) 2002-12-05 2004-06-10 International Business Machines Corporation Interrupt handler prediction method and system
US20040117532A1 (en) * 2002-12-11 2004-06-17 Bennett Steven M. Mechanism for controlling external interrupts in a virtual machine system
US7350005B2 (en) 2003-05-23 2008-03-25 Arm Limited Handling interrupts in a system having multiple data processing units
US7051146B2 (en) * 2003-06-25 2006-05-23 Lsi Logic Corporation Data processing systems including high performance buses and interfaces, and associated communication methods
GB2403822B (en) * 2003-07-07 2006-05-10 Advanced Risc Mach Ltd Data processing apparatus and method for handling interrupts
US7177967B2 (en) * 2003-09-30 2007-02-13 Intel Corporation Chipset support for managing hardware interrupts in a virtual machine system
US7237051B2 (en) * 2003-09-30 2007-06-26 Intel Corporation Mechanism to control hardware interrupt acknowledgement in a virtual machine system
DE10361364B4 (de) * 2003-12-29 2010-07-01 Advanced Micro Devices, Inc., Sunnyvale Vorrichtung zum Behandeln von Interruptereignissen, mit der pegel-sensitive bzw. level-sensitive Interruptanforderungen in flankengetriggerten Interruptnachrichten umgesetzt werden
JP4564011B2 (ja) * 2004-08-27 2010-10-20 パナソニック株式会社 情報処理装置、例外制御回路
US7769937B2 (en) * 2005-02-28 2010-08-03 Koninklijke Philips Electronics N.V. Data processing system with interrupt controller and interrupt controlling method
JP2006331156A (ja) * 2005-05-27 2006-12-07 Renesas Technology Corp 半導体装置
US7424563B2 (en) * 2006-02-24 2008-09-09 Qualcomm Incorporated Two-level interrupt service routine
US7533207B2 (en) * 2006-12-06 2009-05-12 Microsoft Corporation Optimized interrupt delivery in a virtualized environment
JP4249779B2 (ja) * 2006-12-25 2009-04-08 株式会社東芝 デバイス制御装置
US7769938B2 (en) * 2007-09-06 2010-08-03 Intel Corporation Processor selection for an interrupt identifying a processor cluster
US7657683B2 (en) 2008-02-01 2010-02-02 Redpine Signals, Inc. Cross-thread interrupt controller for a multi-thread processor
US8291202B2 (en) * 2008-08-08 2012-10-16 Qualcomm Incorporated Apparatus and methods for speculative interrupt vector prefetching
US7849247B2 (en) 2008-10-14 2010-12-07 Freescale Semiconductor, Inc. Interrupt controller for accelerated interrupt handling in a data processing system and method thereof
US8302109B2 (en) * 2009-02-24 2012-10-30 International Business Machines Corporation Synchronization optimized queuing system
US8234431B2 (en) * 2009-10-13 2012-07-31 Empire Technology Development Llc Interrupt masking for multi-core processors
US8312195B2 (en) * 2010-02-18 2012-11-13 Red Hat, Inc. Managing interrupts using a preferred binding between a device generating interrupts and a CPU
US8458386B2 (en) * 2010-12-07 2013-06-04 Apple Inc. Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements
US8688883B2 (en) * 2011-09-08 2014-04-01 Intel Corporation Increasing turbo mode residency of a processor
US8972642B2 (en) * 2011-10-04 2015-03-03 Qualcomm Incorporated Low latency two-level interrupt controller interface to multi-threaded processor

Also Published As

Publication number Publication date
US8972642B2 (en) 2015-03-03
WO2013052684A3 (en) 2013-06-20
JP2014534506A (ja) 2014-12-18
JP2016095855A (ja) 2016-05-26
JP6153991B2 (ja) 2017-06-28
US20130086290A1 (en) 2013-04-04
KR101563576B1 (ko) 2015-10-27
EP2764442B1 (en) 2016-01-20
EP2764442A2 (en) 2014-08-13
KR20140082787A (ko) 2014-07-02
JP5847949B2 (ja) 2016-01-27
WO2013052684A2 (en) 2013-04-11
CN103874990A (zh) 2014-06-18

Similar Documents

Publication Publication Date Title
CN103874990B (zh) 到多线程处理器的低等待时间两级中断控制器接口
JP5963282B2 (ja) 割り込み分配スキーム
KR101643675B1 (ko) 명령 프로세싱 회로들, 및 관련 프로세서 시스템들, 방법들 및 컴퓨터―판독 가능 매체들에서 반대 컨디션들을 갖는 조건부 기록 명령들의 융합
EP2972787B1 (en) Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media
WO2014085472A1 (en) Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media
US20140122759A1 (en) Edge-Triggered Interrupt Conversion
EP3118738B1 (en) Method and system for processing interruptible instructions in a microcontroller
CN104335167B (zh) 用于处理计算机指令的方法和处理器
CN107015931A (zh) 用于中断处理的方法和加速器单元
CN111752877A (zh) 一种处理器及其中的中断控制器
US9146741B2 (en) Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media
US9552313B2 (en) Delivering real time interrupts with an advanced programmable interrupt controller
JP6066807B2 (ja) 計算機システム、計算機システムの割込み処理プログラム及び計算機システムの割込み処理方法
CN106557441A (zh) 一种基于中断控制器的低速接口中断处理方法及系统
CN115167924A (zh) 指令处理方法、装置、电子设备及计算机可读存储介质
JP2001084143A (ja) 情報処理装置
JP2002312163A (ja) 情報処理装置、情報処理方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant