JP2014523569A5 - - Google Patents

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Publication number
JP2014523569A5
JP2014523569A5 JP2014515970A JP2014515970A JP2014523569A5 JP 2014523569 A5 JP2014523569 A5 JP 2014523569A5 JP 2014515970 A JP2014515970 A JP 2014515970A JP 2014515970 A JP2014515970 A JP 2014515970A JP 2014523569 A5 JP2014523569 A5 JP 2014523569A5
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JP
Japan
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memory
processor
instruction
data
design
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JP2014515970A
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English (en)
Japanese (ja)
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JP2014523569A (ja
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Priority claimed from US13/494,913 external-priority patent/US9430596B2/en
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Publication of JP2014523569A publication Critical patent/JP2014523569A/ja
Publication of JP2014523569A5 publication Critical patent/JP2014523569A5/ja
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JP2014515970A 2011-06-14 2012-06-13 拡張可能な並列プロセッサのためのシステム、方法、および、装置 Pending JP2014523569A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161496900P 2011-06-14 2011-06-14
US61/496,900 2011-06-14
US13/494,913 2012-06-12
US13/494,913 US9430596B2 (en) 2011-06-14 2012-06-12 System, method and apparatus for a scalable parallel processor
PCT/US2012/042322 WO2012174167A1 (en) 2011-06-14 2012-06-13 System, method and apparatus for a scalable parallel processor

Publications (2)

Publication Number Publication Date
JP2014523569A JP2014523569A (ja) 2014-09-11
JP2014523569A5 true JP2014523569A5 (enExample) 2015-07-30

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ID=47354375

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JP2014515970A Pending JP2014523569A (ja) 2011-06-14 2012-06-13 拡張可能な並列プロセッサのためのシステム、方法、および、装置

Country Status (5)

Country Link
US (2) US9430596B2 (enExample)
EP (1) EP2721508A4 (enExample)
JP (1) JP2014523569A (enExample)
KR (1) KR20140068863A (enExample)
WO (1) WO2012174167A1 (enExample)

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US9448777B2 (en) * 2012-09-07 2016-09-20 Samsung Electronics Co., Ltd. Apparatus and method for generating assertion based on user program code, and apparatus and method for verifying processor using assertion
US10552126B2 (en) * 2013-03-15 2020-02-04 Teradata Us, Inc. Transitioning between code-based and data-based execution forms in computing systems and environments
US10564929B2 (en) * 2016-09-01 2020-02-18 Wave Computing, Inc. Communication between dataflow processing units and memories
US10275244B2 (en) * 2016-03-04 2019-04-30 Montana Systems Inc. Event-driven design simulation
US11675681B2 (en) * 2021-09-21 2023-06-13 International Business Machines Corporation Configuration of weighted address pools for component design verification
US20230186003A1 (en) * 2021-12-10 2023-06-15 Metrics Design Automation, Inc. Digital design simulation accelerator
US11868786B1 (en) * 2022-01-14 2024-01-09 Cadence Design Systems, Inc. Systems and methods for distributed and parallelized emulation processor configuration
CN117935901B (zh) * 2024-02-19 2024-09-06 北京中科昊芯科技有限公司 一种用于访问sdram的emif的验证方法

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