JP2014509780A - テクスチャ化表面を金属化するための方法 - Google Patents
テクスチャ化表面を金属化するための方法 Download PDFInfo
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Abstract
- 基板(100、110)を準備するステップ(10)であって、そのステップの間に基板の少なくともテクスチャ化表面が、導電性にされる、ステップ、
- 被覆するステップ(20)であって、その間に、インプリント可能材料(120)の少なくとも1つの被膜が、基板の導電性にされたテクスチャ化表面に置かれる、ステップ、
- パターン(132)を形成するためにモールド(130)のくぼみまたは突出部をインプリント可能材料(120)に転写するために、くぼみまたは突出部を含むモールド(130)をプレスするステップ(30)、
- モールドを引き離してインプリント可能材料(120)の適所にパターン(132)のインプリントを残すステップ(40)、
- パターンの底部において、基板の導電性にされたテクスチャ化表面のいくらかをむき出しにするステップ(50)、
- 導電性または半導電性パターン(140、150)を形成するために導電性または半導電性材料をパターン(132)中に電気的に堆積させるステップ(60)を含むことを特徴とする。
Description
- 基板を準備するステップであって、その間に基板の少なくともテクスチャ化表面が、導電性にされる、ステップ
- 準備するステップであって、その間にインプリント可能材料の層が、導電層上にめっきされる、ステップ
- 金属化すべきパターンを内部に形成するためにモールドの谷部または突出部をインプリント可能材料に転写するように谷部または突出部を含むモールドをプレスするステップ
- 金属化すべきパターンのインプリントをインプリント可能材料に残しながらモールドを除去するステップ
- 導電性または半導電性パターンを形成するためのパターン中への少なくとも1つの導電性または半導電性材料を電着するまたは電気化学的に堆積するステップ。
例えば、導電性または半導電性材料は、金属であり、パターンは、金属製パターンである。
Vlayer=Vmold+Vfill+Vsafety
であり、ただし、
Vmold=モールドパターンによって規定され、プレスするステップの間はレジストで充填されることを目的とする体積、
Vfill=テクスチャ化表面と、基板に平行で、最大振幅を有するレリーフの最高点を通過する平面との間の自由体積、
Vsafety=(基板の表面)×(安全厚さ)、最高レリーフのピークとモールドパターンの端部との間の距離
である。
(es)≦2Hm-(A)
ただし、
Hm=モールドパターンの高さ、
A=レリーフの最大振幅
である。この距離は、テクスチャ化表面の最高レリーフの高さと最低谷部との間の差として定義される。
- 基板を準備するステップであって、そのときに基板のテクスチャ化表面の少なくとも全体が導電性にされる、ステップ
- 被覆するステップであって、その間にインプリント可能材料の少なくとも1つの層が導電性にされたテクスチャ化表面にナノメートルインプリンティングによって直接めっきされる、ステップ
- パターンを内部に形成するためにモールドの谷部または突出部をインプリント可能材料に転写するように谷部または突出部を有するモールドをプレスするステップ
- パターンのインプリントをインプリント可能材料に残したままモールドを除去するステップ
- パターンの底部において、基板のテクスチャ化表面を露出させるステップ
- 導電性または半導電性パターンを形成するために少なくとも導電性または半導電性材料をパターン中に電気的に堆積させるステップ。
- 選択的であり、シリコンの面(1-1-1)の露出、それ故にピラミッドの形成を可能にする、水酸化カリウムを表すKOHまたは水酸化テトラメチルアンモニウムを表すTMAHを使った腐食によるピラミッドの作製
- リソグラフィーのステップの後の化学エッチングによるいわゆる「反転ピラミッド」構造の作製。
- 基板をテクスチャ加工する影響を含む基板の全表面を知り、電着反応の収率が100%に近いことを最初に仮定すると、以下で述べるファラデーの法則は、堆積されるモル数を決定することを可能にする。金属の所望の厚さを得るために必要とされる時間はその時、印加される電流の関数として推定できる。
- もし、反応収率が100%未満であるならば、1つまたは複数の望ましくない反応が、主要な堆積反応を犠牲にして生じることもある。酸性媒質での最も一般的な望ましくない反応の1つは、H+イオンの水素への還元である。電解液の成分に応じて、堆積すべき金属カチオン以外のカチオンが、還元されることもあり得る。付与電位析出(imparted potential deposition)が、この問題を克服するのに役立つこともある。実際、付与電位析出は、対象の反応が生じる値に電位を固定する。それ故に、望ましくない反応の発生のリスクが、制限される。他方で、付与電位析出はまた、堆積物核生成メカニズムのより良好な制御を可能にもする。選択された電位析出システムを通過するクーロン単位で表した電荷数を知り、堆積が順応性であることを考慮すると、堆積される厚さは容易に推定でき、過剰堆積が実行され得る。
- 瞬間的核生成:すべてのサイトが同時に成長し始める。
- 漸進的核生成:発生(germination)がサイトで次第に増加する。
- Franck Van Der Merwe成長または層ごとの成長:これは、めったに観察されない理想的な事例である。堆積物は、均一であり、新しい層は、前の層が完了するときにだけ形成される。この種の成長は、欠陥のない表面にだけ生じ、成長は、二次元的である。材料が高品質のものでない光起電セルの場合には、多くの表面欠陥が、このモードを見込みのないものにする。
- Stranski-Krastanov成長:最初に副層が形成され、次いでクラスターが成長する。この現象は、欠陥をもつ表面の場合に生じ、成長はその時、三次元的である。
- Volmer-Weber成長:この場合には、クラスターが、副層なしに金属表面に直接形成される。
Vlayer=Vmold+Vfill+Vsafety
に等しく、ただし、
Vmold=モールドパターンによって規定される体積。図5では、体積Vmoldは、これらのパターンの幅Lm、高さHmおよび深さ(図示されず)によって規定される個々の体積の合計に等しい。
Vfill=テクスチャ化表面と、基板に平行で、より大きな振幅のレリーフの最高点を通過する平面との間の自由体積。典型的には、この平面は、図5で示す断面の平面に垂直である。実際には、もし、基板が2つの対向面をもつ平板形状を有するならば、その平面は、これらの面に平行である。典型的には、この体積は、原子間力顕微鏡(AFM)によって測定される画像上で基板のテクスチャ化表面のレリーフによって占有される範囲の分析によって決定される。
基板表面は、巨視的表面の範囲である。言い換えれば、これは、基板によって形成される平板の各面の範囲である。
Vsafety=(基板表面)×(安全厚さ)。安全厚さは、図5で参照記号esによって表される。それは、図4での参照記号220に対応する。それは、モールドパターンのピークとテクスチャ化表面のレリーフのピークとの間のレジストの最小厚さに対応する。典型的には、最小安全厚さは、数十ナノメートル(nm=10-9メートル)になる。
ただし、
Hm=モールドパターンの高さ。図5ではモールドパターンの幅は、Lmと参照される。
A=レリーフの最大振幅。この距離は、テクスチャ化表面での最高レリーフのピークと最低谷部との間の高さの差として定義される。この振幅はまた、最高レリーフの「ピークから谷部まで」の振幅とも呼ばれる。AFM顕微鏡を使用すると、テクスチャ化表面の最高レリーフおよびテクスチャ化表面の最低谷部は、容易に決定され、それらの間の高さの差が、容易に決定される。図5では、この最大振幅は、「h」と参照される。
- 電気化学的堆積は、順応性堆積物を作製し、高い粗さまたはテクスチャ加工部を有する表面に一貫した質の電気接点を得ることを可能にする。
- モールドからのパターンのインプリンティングは、基板の強い層化にもかかわらず重要な領域深さ(field depth)をもつ良好な分解能を提供する。
- 粒子の異なる高さに起因して表面段差を生み出す粒界の存在、
- 平板の切断の間に、例えばソーを使用するときに出現する表面の波形、
- 平板が面取りされることもあり得る
というような大きな表面欠陥を有するときでさえ、前記パターンと基板との間の良好な接触を提供する。
20 インプリント可能材料層を堆積させるステップ
30 モールドを適用するステップ
40 モールドを除去するステップ
50 インプリント可能材料層を腐食するステップ
60 電着するステップ
100 基板、ベース基板
102 レリーフ
104 レリーフの振幅
110 導電層、ITO層
120 インプリント可能材料層
122 中間パターン
124 モールドによって圧縮された部分
130 モールド
132 金属化パターン、モールドパターン、トレンチ
134 マスキング被膜
136 露光
140 金属層、テクスチャ面
150 異なる電着レベル、厚い金属層
160 アモルファスシリコン層
220 モールドパターンのピークと基板裂け目のピークとの間の最小厚さ
Claims (25)
基板(100、110)を準備するステップ(10)であって、その間に前記基板の前記テクスチャ化表面全体が、導電性にされる、ステップ、
被覆するステップ(20)であって、その間にインプリント可能材料(120)の少なくとも1つの層が、導電性にされた前記テクスチャ化表面に置かれる、ステップ、
パターン(132)を内部に形成するためにモールド(130)の谷部または突出部を前記インプリント可能材料(120)に転写するため、前記谷部または前記突出部を含む前記モールド(130)をプレスするステップ(30)、
前記パターン(132)のインプリントを前記インプリント可能材料(120)に残しながら前記モールドを除去するステップ(40)、
前記パターンの底部において前記テクスチャ化表面を露出させるステップ(50)、
導電性または半導電性パターン(140、150)を形成するために前記パターン(132)中に少なくとも導電性または半導電性材料を電気的に堆積させるステップ(60)
を含むことを特徴とする、方法。
Vlayer=Vmold+Vfill+Vsafety
であり、ただし、
Vmold=モールドパターンによって規定される体積、
Vfill=前記テクスチャ化表面と、前記基板に平行で、最大振幅を有する前記レリーフの最高点を通過する平面との間の自由体積、
Vsafety=(前記基板の表面)×(安全厚さ)であり、ただし前記安全厚さ(220、es)は、前記テクスチャ化表面の最高レリーフのピークと前記モールドパターンの先端との間の距離である、請求項1から18のいずれか一項に記載の方法。
(es)≦2Hm-(A)
ただし、
A=前記テクスチャ化表面の最高点と最低点との間の距離、
Hm=前記モールドパターンの高さである、
請求項19に記載の方法。
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JP6300712B2 (ja) * | 2014-01-27 | 2018-03-28 | 三菱電機株式会社 | 太陽電池および太陽電池の製造方法 |
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US20140034125A1 (en) | 2014-02-06 |
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EP2681776A2 (fr) | 2014-01-08 |
JP6131196B2 (ja) | 2017-05-17 |
KR101906375B1 (ko) | 2018-10-11 |
EP2681776B1 (fr) | 2020-02-26 |
FR2972298B1 (fr) | 2015-07-31 |
KR20140014220A (ko) | 2014-02-05 |
KR20180069921A (ko) | 2018-06-25 |
FR2972298A1 (fr) | 2012-09-07 |
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