JP2014207334A5 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2014207334A5
JP2014207334A5 JP2013084273A JP2013084273A JP2014207334A5 JP 2014207334 A5 JP2014207334 A5 JP 2014207334A5 JP 2013084273 A JP2013084273 A JP 2013084273A JP 2013084273 A JP2013084273 A JP 2013084273A JP 2014207334 A5 JP2014207334 A5 JP 2014207334A5
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JP
Japan
Prior art keywords
layer
semiconductor device
forward tapered
substrate
gan layer
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JP2013084273A
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JP6198039B2 (ja
JP2014207334A (ja
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Priority to JP2013084273A priority Critical patent/JP6198039B2/ja
Priority claimed from JP2013084273A external-priority patent/JP6198039B2/ja
Priority to US14/250,058 priority patent/US9306030B2/en
Publication of JP2014207334A publication Critical patent/JP2014207334A/ja
Priority to US15/074,014 priority patent/US9627506B2/en
Publication of JP2014207334A5 publication Critical patent/JP2014207334A5/ja
Priority to US15/457,549 priority patent/US10446661B2/en
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Description

本発明は、窒化物半導体を用いた半導体装置に関する。

Claims (2)

  1. 基板と、
    前記基板上に設けられたＡｌＧａＮまたはＩｎＡｌＮからなる第１層と、
    前記第１層上に設けられたＧａＮ層と、
    前記第１層および前記ＧａＮ層の両方に延在する順テーパ形状の内壁を有する電極接触窓と、
    前記電極接触窓の前記第１層および前記ＧａＮ層の両方に延在する順テーパ形状に接触して設けられた電極と、
    を備える半導体装置。
  2. 前記順テーパ形状の内壁の基板面に水平な方向の長さは、０．０３μｍ以上かつ０．１μｍ以下である請求項１に記載の半導体装置。
JP2013084273A 2013-04-12 2013-04-12 半導体装置 Active JP6198039B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2013084273A JP6198039B2 (ja) 2013-04-12 2013-04-12 半導体装置
US14/250,058 US9306030B2 (en) 2013-04-12 2014-04-10 Semiconductor device and method of manufacturing the same
US15/074,014 US9627506B2 (en) 2013-04-12 2016-03-18 Method of manufacturing semiconductor device
US15/457,549 US10446661B2 (en) 2013-04-12 2017-03-13 Semiconductor device comprising slanted slope electrode contact windows

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013084273A JP6198039B2 (ja) 2013-04-12 2013-04-12 半導体装置

Publications (3)

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JP2014207334A JP2014207334A (ja) 2014-10-30
JP2014207334A5 true JP2014207334A5 (ja) 2016-06-02
JP6198039B2 JP6198039B2 (ja) 2017-09-20

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JP2013084273A Active JP6198039B2 (ja) 2013-04-12 2013-04-12 半導体装置

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US (3) US9306030B2 (ja)
JP (1) JP6198039B2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6198039B2 (ja) * 2013-04-12 2017-09-20 住友電工デバイス・イノベーション株式会社 半導体装置
US10923446B1 (en) * 2019-09-11 2021-02-16 United States Of America As Represented By The Administrator Of Nasa Indium bump liftoff process on micro-machined silicon substrates

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100647459B1 (ko) * 2005-11-29 2006-11-23 한국전자통신연구원 티형 또는 감마형 게이트 전극의 제조방법
JP5564790B2 (ja) * 2008-12-26 2014-08-06 サンケン電気株式会社 半導体装置及びその製造方法
JP5625314B2 (ja) * 2009-10-22 2014-11-19 サンケン電気株式会社 半導体装置
JP5714250B2 (ja) 2010-07-14 2015-05-07 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP2011228720A (ja) * 2011-05-30 2011-11-10 Panasonic Corp 半導体装置
US8697505B2 (en) * 2011-09-15 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor structure
JP5777586B2 (ja) * 2012-09-20 2015-09-09 株式会社東芝 半導体装置及びその製造方法
JP2014072377A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 化合物半導体装置及びその製造方法
JP6198039B2 (ja) * 2013-04-12 2017-09-20 住友電工デバイス・イノベーション株式会社 半導体装置

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