JP2014192842A - Waveguide microstrip line converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveguide microstrip line converter capable of dispensing with metal work and improving the positional accuracy of a constituent component.SOLUTION: The waveguide microstrip line converter comprises: a dielectric substrate 1 having an opening formed therein; a waveguide 4A disposed on one surface side of the dielectric substrate 1; a conductor line 1S formed on the other surface side of the dielectric substrate 1; a grounding conductor 2G disposed between the dielectric substrate 1 and the waveguide 4A; dielectric layers 3A-3C having openings continuous to the opening of the dielectric substrate 1 formed therein and layered on the other surface side of the dielectric substrate 1; conductor layers 3a-3c formed on the dielectric layers 3A-3C, respectively; a dielectric layer 3D layered on the dielectric layer 3C; as conductor layer 3d formed on the dielectric layer 3D; and vias 9 disposed around openings (20) in the dielectric layers 3A-3C.

Description

  The present invention relates to a waveguide microstrip line converter.

  FIG. 11 is a cross-sectional view of a conventional waveguide microstrip line converter, and FIG. 12 is a view taken along the line BB in FIG. 11 is a cross-sectional view taken along line AA in FIG.

  The waveguide microstrip line converter guides an electromagnetic wave propagating through the waveguide to the microstrip line. The waveguide microstrip line converter includes a waveguide 101, a ground conductor 102, a dielectric substrate 103, a conductor line 104, and a gap (referred to as a short) 105. The waveguide 101 is formed in the metal plate 100, and its opening is attached to the ground conductor 102 so as to face the conductor line 104. The conductor line 104, the dielectric substrate 103, and the ground conductor 102 constitute a microstrip line, and the tip of the conductor line 104 (referred to as a probe 104A) is disposed so as to overlap the center of the waveguide 101.

  When the electromagnetic wave propagating through the waveguide 101 in the TE10 mode reaches the probe 104A, an electromagnetic field surrounding the probe 104A is generated, and a pseudo TEM mode propagating in a direction away from the probe 104A is generated in the microstrip line.

  In this way, the electromagnetic wave incident from the waveguide 101 is guided to the microstrip line via the probe 104A with low propagation loss. The probe 104A is inserted at a position where the length is λ / 4 (λ: free space wavelength) and the interval between the waveguide 101 and the short 105 is λg / 4 (λg: wavelength in the waveguide). The impedance matching of the probe 104A is taken (see Patent Document 1 and Patent Document 2).

  The short 105 is a structure for impedance matching between the waveguide 101 and the microstrip line.

Japanese Patent Laid-Open No. 2004-22589 JP 2007-318348 A

  In the conventional waveguide microstrip line converter, the short 105 is produced by metal cutting. In order to manufacture the short 105 so as to be matched in the center frequency band to be used, a cutting process for machining the gap from the metal block 105A with high accuracy is necessary, and productivity is low and cost is high.

  Further, since it is necessary to bond the metal block 105A to the dielectric substrate 103 and to be fitted to the metal plate 100, the dielectric substrate 103 and the short 105 are mounted with respect to the waveguide 101. There was a problem that loss was difficult to control.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a waveguide microstrip line converter that does not require metal processing and can improve the positional accuracy of components. is there.

  In order to solve the above problems, a first aspect of the present invention provides a dielectric substrate in which an opening is formed, a waveguide disposed on one side of the dielectric substrate, and the dielectric substrate. A conductor line formed on the other surface, a ground conductor disposed between the dielectric substrate and the waveguide, and an opening connected to the opening are formed on the other surface of the dielectric substrate. One or more first dielectric layers stacked on each other, a conductor layer formed on the first dielectric layer, a second dielectric layer stacked on the first dielectric layer, and the second dielectric A conductor layer formed on the body layer; and a via disposed around the opening of the first dielectric layer and penetrating the first dielectric layer and the second dielectric layer. And

  For example, the via includes a first via that is disposed around the opening of the first dielectric layer and penetrates the first dielectric layer, and a second via that penetrates the second dielectric layer. Is done.

  For example, the waveguide includes one or more dielectric layers in which openings are formed, and vias that are disposed around the openings and penetrate the dielectric layers.

  For example, a notch is formed in at least one of the portion of the first dielectric layer facing the conductor line and the portion of the second dielectric layer facing the conductor line.

  For example, two openings of the first dielectric layer are formed with a portion of the first dielectric layer facing the tip of the conductor line.

  According to the waveguide microstrip line converter of the present invention, metal processing is unnecessary and the positional accuracy of the component parts can be improved.

It is sectional drawing of the MMIC integrated module containing the waveguide microstrip line converter which concerns on 1st Embodiment. It is sectional drawing of the waveguide microstrip line converter which concerns on 1st Embodiment. It is a BB arrow line view of FIG. It is CC arrow line view of FIG. FIG. 3 is a DD arrow view of FIG. 2. It is sectional drawing of the waveguide microstrip line converter which concerns on 2nd Embodiment. It is a BB arrow line view of FIG. It is CC arrow line view of FIG. It is the DD arrow line view of FIG. It is a figure corresponding to FIG. 7 in 3rd Embodiment. It is sectional drawing of the conventional waveguide microstrip line converter. It is a BB arrow line view of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a cross-sectional view of an MMIC integrated module including a waveguide microstrip line converter according to a first embodiment.

  In the MMIC integrated module, the conductor line 1S is formed on the dielectric substrate 1, the ground conductor 2G is formed on the dielectric substrate 2, the conductor layer is formed on the dielectric layers 3A to 3E, and the metal plate 4 is formed. The waveguide 4A is formed, and a laminated dielectric substrate in which the dielectric substrates 1 and 2 and the dielectric layers 3A to 3E are laminated on the metal plate 4 is bonded. The dielectric substrate 1 and the dielectric layers 3 </ b> A to 3 </ b> E are sequentially bonded to the dielectric substrate 2, and the lower surface of the dielectric substrate 2 is bonded to the metal plate 4.

  The materials of the dielectric substrates 1 and 2 and the dielectric layers 3A to 3E are, for example, LTCC (Low Temperature Fired Ceramics) which is a kind of ceramic material.

  The conductor line 1S, the ground conductor 2G, and the conductor layer on the dielectric layer are made of gold, silver, tungsten, copper, etc., and have a thickness of several to several tens of micrometers (microns). Silk screen printing or plating It is formed by.

  Openings are formed in advance in the dielectric layers 3A to 3E, and a package having a rectangular cavity (space) 5 is formed by stacking. The MMIC 6 includes a receiving unit made of a compound semiconductor substrate and is disposed in the cavity 5. Specifically, the MMIC 6 is mounted on the dielectric substrate 1 by flip chip bonding via bumps 7 and sealed with a metal lid 8, for example.

  The via 9 is a metal conductor, and penetrates the dielectric substrates 1 and 2 and the dielectric layer, and conducts the conductor layer of each dielectric layer. On the dielectric substrate 1, there is a wiring pattern for connecting the vias 9, and the signal lines of the connector 10 and the pads on the MMIC 6 are electrically connected.

  A microstrip line is formed by sandwiching the dielectric substrate 1 between the conductor line 1S and the ground conductor 2G. Further, between the waveguide 4A and the microstrip line, the waveguide microstrip line is connected via the tip of the conductor line 1S (referred to as the probe 1P) to couple electromagnetic waves from the waveguide 4A to the microstrip line. A transducer is formed.

  Although not shown, a radiator such as a horn or a lens is connected to the lower end of the waveguide 4A in the drawing, and thereby the waveguide 4A receives radio waves from the outside.

  In addition to the LTCC, the dielectric substrates 1 and 2 and the dielectric layers 3A to 3E may be ceramics, a ceramic mixed material in which ceramics and a glass filler are mixed, a polymer material such as polyimide, and a material with low dielectric loss. Is desirable. When using a ceramic material, firing is performed at a high temperature after lamination.

  The mounting method of the MMIC 6 may be wire bonding instead of flip chip bonding.

  2 is a cross-sectional view of the waveguide microstrip line converter according to the first embodiment, FIG. 3 is a view taken along the line BB in FIG. 2, and FIG. FIG. 5 is a view taken in the direction of arrow C, and FIG. 5 is a view taken in the direction of arrow DD in FIG. FIG. 2 is a cross-sectional view taken along the line AA of FIGS. In FIG. 2, the metal lid 8 is not shown.

  The waveguide microstrip line converter includes a dielectric substrate 1 having an opening 1K, a waveguide 4A disposed on one side (lower side in the figure) of the dielectric substrate 1, and a dielectric Conductor line 1S formed on the other surface of substrate 1 (on the upper surface in the figure), ground conductor 2G disposed on dielectric substrate 1 up to the end of waveguide 4A, and an opening continuous with opening 1K Dielectric layers 3A to 3C formed on the other side of the dielectric substrate 1 on which the portion 3K is formed, conductor layers 3a to 3c respectively formed on the dielectric layers 3A to 3C, and dielectric layers A dielectric layer 3D stacked on 3C, a conductor layer 3d formed on the dielectric layer 3D, and a via 9 disposed around the opening 3K and penetrating the dielectric layers 3A to 3D. The vias 9 are, for example, cylindrical, and have a diameter of 100 μm and a pitch of 200 μm.

  A dielectric layer 3E is laminated on the dielectric layer 3D, and a conductor layer 3e is formed on the dielectric layer 3E. The dielectric substrate 2 and the dielectric layer 3E are not necessarily required, but serve as a structural reinforcing material and reduce the warpage of the substrate.

  The conductor line 1S and the ground conductor 2G constitute a microstrip line. Each opening 3K and via 9 form an air gap (referred to as short 20) for impedance matching between the waveguide 4A and the microstrip line. The short 20 has a size of, for example, 800 μm × 400 μm in accordance with the waveguide 4A, and the thickness thereof can be obtained by electromagnetic field numerical calculation, for example, 50 μm.

  As shown in FIG. 3, the probe 1P is arranged in the center of the waveguide 4A, and openings 1K are formed on both sides thereof. A via 9 and a conductor layer 1d are formed on the dielectric substrate 1 so as to surround the opening 1K and the probe 1P together with the conductor line 1S.

  A via 9 is disposed around the opening 1K, and a pseudo metal wall is formed by the via 9 and the conductor layer 1d. Each via 9 is in contact with the conductor layer 1d and is also electrically connected to the ground conductor 2G.

  The interval between the vias 9 is, for example, 1/4 or less of the wavelength. That is, the vias 9 are arranged at intervals of at least 250 μm or less at a frequency of 300 GHz.

  As shown in FIG. 4, an opening 3K is formed in the dielectric layer 3B. The conductor layer 3b on the dielectric layer 3B is formed on all portions except the opening 3K. The via 9 is arranged in alignment around the opening 3K and contacts the conductor layer 3b. The dielectric layers 3A and 3C have the same configuration.

  In the first embodiment, the four dielectric layers 3A to 3D are sandwiched between the probe 1P and the conductor layer 3d of the dielectric layer 3D, and the total thickness of the four dielectric layers is It becomes the height of the short 20. The impedance of the short 20 can be adjusted by changing the number of layers and the layer thickness. A conductor layer may be formed on the lower surface of the dielectric layer 3D. In this case, the total thickness of the three dielectric layers is the height of the short circuit 20.

  As shown in FIG. 5, no opening is formed in the dielectric layer 3D, and the conductor layer 3d thereon is formed on the entire surface. The via 9 also contacts the conductor layer 3d on the dielectric layer 3D.

  As described above, the waveguide microstrip line converter according to the first embodiment includes the dielectric substrate 1 in which the opening 1K is formed and the conductor disposed on the one surface side of the dielectric substrate 1. A wave tube 4A, a conductor line 1S formed on the other surface of the dielectric substrate 1, a ground conductor 2G disposed between the dielectric substrate 1 and the waveguide 4A, and an opening 3K connected to the opening 1K. And one or more first dielectric layers (3A to 3C) stacked on the other side of the dielectric substrate 1, conductor layers 3a to 3c formed on the first dielectric layer, and first A second dielectric layer (3D) laminated on the dielectric layer; a conductor layer 1d formed on the second dielectric layer; and a first dielectric disposed around the opening of the first dielectric layer And a via 9 penetrating the second dielectric layer. Since the short 20 is formed by such a configuration, metal processing for forming the short 105 as shown in FIGS. 11 and 12 can be made unnecessary. In addition, the substrate and layer formation process can be used, and the positional accuracy of the components can be improved.

  In the first embodiment, the first dielectric layer is three layers, but may be one layer, two layers, or four layers or more. The same applies to the embodiments described later.

[Second Embodiment]
Next, a waveguide microstrip line converter according to a second embodiment will be described. In the second embodiment, the same or similar configuration is used in the first embodiment, and the same or similar components are denoted by the same reference numerals used in the first embodiment, and redundant description is omitted. The description will focus on matters different from those of the first embodiment.

  6 is a cross-sectional view of the waveguide microstrip line converter according to the second embodiment, FIG. 7 is a view taken along the line BB of FIG. 6, and FIG. FIG. 9 is a view taken in the direction of arrow C, and FIG. 9 is a view taken in the direction of arrow D-D in FIG. FIG. 6 is a cross-sectional view taken along the line AA in FIGS. In FIG. 6, the metal lid 8 is omitted.

  As shown in FIG. 6, instead of the metal plate 4 (waveguide 4A), the opening 4K and dielectric layers 41 and 42 having a conductor layer formed on the surface are laminated, and the via 43 and the conductor layer are opened. The pseudo waveguide 4B is formed by disposing it around 4K. Thereby, the process of the metal plate 4 for forming the waveguide 4A can be made unnecessary. Note that the number of layers may be one or three or more. The same applies to a third embodiment described later.

  Further, in place of the via 9 of FIG. 2, a via 9A (corresponding to the first via) disposed around the opening 3K of the dielectric layers 3A to 3C and penetrating the dielectric layers 3A to 3C, and the dielectric layer A via 9B (corresponding to a second via) penetrating 3D is provided. Thereby, the via 9B can be freely arranged without being limited to the position of the via 9A, and thus the impedance of the short 20 can be freely adjusted.

  The impedance of the short 20 can be adjusted by the number of layers such as the dielectric layers 3A to 3C and the distance from the opening 3K to the via. However, if the distance is short, the dielectric layer may be broken. Therefore, a predetermined distance or more is necessary, and a desired impedance may not be obtained. Further, the adjustment by the number of layers can change the impedance only in a stepwise manner, and fine adjustment is difficult.

  In order to solve this problem, the layer above the short circuit 20, that is, the dielectric layer 3D has no opening and the arrangement of the vias is not limited. Therefore, the dielectric layer 3D and the lower dielectric layers 3A to 3C The impedance can be matched by adjusting the arrangement of vias differently.

  In addition, the via 43 can be freely arranged without being limited to the position of the via 9A, and the impedance matching between the waveguide 4B and the short 20 can be adjusted.

  Further, as shown in FIG. 7, the impedance matching unit 1T is inserted between the probe 1P and the microstrip line, that is, the impedance loss between the probe 1P and the microstrip line is performed, so that the reflection loss can be reduced. Here, for example, a λ / 4 matching line with different line widths is used.

  Further, a notch is formed in the portion of the dielectric layer 3B facing the conductor line 1S, and as a result, a notch 31b is also formed in the conductor layer 3b as shown in FIG. In addition, similar notches are formed in the same positions in the dielectric layers 3A and 3C.

  Further, a notch is formed in the portion of the dielectric layer 3D facing the conductor line 1S, and as a result, a notch 31d is also formed in the conductor layer 3d as shown in FIG. In addition, a similar notch is formed at the same position in the dielectric layer 3E.

  As a result, in the second embodiment, the volume of the portion of the dielectric layers 3A to 3E facing the conductor line 1S is small, and therefore the propagation loss due to the dielectric loss of the dielectric layer can be reduced.

  Note that the cutouts may not be formed in all of the dielectric layers 3A to 3E, but may be formed in any one or more layers. It is preferable to form the dielectric 3A in contact with the conductor line 1S.

  Further, as shown in FIG. 8, two openings 3K of the dielectric layer 3B are formed with a portion of the dielectric layer 3B facing the probe 1P interposed therebetween. The dielectric layers 3A and 3C have the same configuration.

  The thickness of the portion of the probe 1P on the dielectric substrate 1 is determined by the impedance design of the microstrip line. If the thickness is reduced, the insertion loss can be reduced, but if it is thin, there is a possibility of breaking due to stress.

  Therefore, in the dielectric layers 3A to 3C, the portion facing the probe 1P is not used as an opening, and the dielectric layer is left. Thereby, the intensity | strength of the part of the probe 1P can be raised. Such a configuration may include only the dielectric layer 3A or only the dielectric layers 3A and 3B.

  In the second embodiment, a waveguide 4A obtained by processing the metal plate 4 may be used instead of the pseudo waveguide 4B. The same applies to a third embodiment described later.

[Third Embodiment]
Next, a waveguide microstrip line converter according to a third embodiment will be described. In the third embodiment, the same or similar configuration is used in the first and second embodiments, and the same or similar components are redundantly described by using the reference numerals used in the first and second embodiments. The description will focus on matters different from the first and second embodiments.

  FIG. 10 is a diagram corresponding to FIG. 7 and shows the same part in the third embodiment.

  As described above, the impedance of the short 20 may not be adjusted depending on the number of dielectric layers and the distance from the opening to the via. That is, the impedance of the short 20 can be adjusted by the number of dielectric layers 3A to 3C and the distance from the opening 3K to the via. However, if the distance is short, the dielectric layer may be broken.

  Therefore, in the third embodiment, by adjusting the size of the opening 3K, the distance from the opening 1K to the via 9A is not changed, and the arrangement of the via 9A is adjusted, thereby matching the impedance. Can do.

  The size of the opening 3K can be adjusted not only in the third embodiment but also in the first and second embodiments.

DESCRIPTION OF SYMBOLS 1, 2 ... Dielectric board | substrate 1K, 3K, 4K ... Opening 1P ... Probe 1S ... Conductor line 1T ... Impedance matching part 1d, 3a, 3b, 3c, 3d ... Conductor layer 2G ... Grounding conductor 3A, 3A, 3C, 3D 3E, 41, 42 ... Dielectric layer 4 ... Metal plate 4A, 4B ... Waveguide 5 ... Cavity 6 ... MMIC
7 ... Bump 8 ... Metal lid 9, 9A, 9B, 43 ... Via 10 ... Connector 20 ... Short

In order to solve the above problems, a first aspect of the present invention provides a dielectric substrate in which an opening is formed, a waveguide disposed on one side of the dielectric substrate, and the dielectric substrate. A conductor line formed on the other surface, a ground conductor disposed between the dielectric substrate and the waveguide, and an opening connected to the opening are formed on the other surface of the dielectric substrate. One or more first dielectric layers stacked on each other, a conductor layer formed on the first dielectric layer, a second dielectric layer stacked on the first dielectric layer, and the second dielectric comprising a conductor layer formed on the body layer, and a via penetrating the first arranged around the opening of the dielectric layer and the first dielectric layer and a second dielectric layer, said via Includes a first via disposed around the opening of the first dielectric layer and penetrating through the first dielectric layer, and the second dielectric layer. It is composed of a second via for passing to said Rukoto.

Claims (5)

A dielectric substrate having an opening formed thereon;
A waveguide disposed on one side of the dielectric substrate;
A conductor line formed on the other surface of the dielectric substrate;
A ground conductor disposed between the dielectric substrate and the waveguide;
One or more first dielectric layers formed on the other side of the dielectric substrate by forming an opening continuous with the opening; and
A conductor layer formed on the first dielectric layer;
A second dielectric layer stacked on the first dielectric layer;
A conductor layer formed on the second dielectric layer;
A waveguide microstrip line converter, comprising: a via disposed around an opening of the first dielectric layer and penetrating the first dielectric layer and the second dielectric layer.   The via is composed of a first via disposed around the opening of the first dielectric layer and penetrating the first dielectric layer, and a second via penetrating the second dielectric layer. The waveguide microstrip line converter according to claim 1. The waveguide is
One or more dielectric layers having openings formed therein;
The waveguide microstrip line converter according to claim 1, further comprising: a via disposed around the opening and penetrating the dielectric layer.   4. A notch is formed in at least one of the portion of the first dielectric layer facing the conductor line and the portion of the second dielectric layer facing the conductor line. A waveguide microstrip line converter according to claim 1.   5. The opening portion of the first dielectric layer is formed with two portions sandwiching a portion of the first dielectric layer facing the tip of the conductor line. 6. Waveguide microstrip line converter.

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