JP2014158010A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board including a via and capable of coping with miniaturization.SOLUTION: A method for manufacturing a wiring board comprises the steps of: forming a via hole in an insulating layer; forming a via conductor in the via hole; forming a catalyst layer on the insulating film; forming a desired pattern mask on the catalyst layer; forming a conductor layer on the catalyst layer by electroless plating; peeling the mask; and removing a catalyst layer in the portion exposed as a result of peeling the mask.

Description

  The present invention relates to a method for manufacturing a wiring board.

  2. Description of the Related Art Miniaturization of wiring on a wiring board has progressed conventionally. In order to cope with the miniaturization of wiring, in a conventional wiring board, after forming an electroless copper plating layer on an insulating layer, a predetermined pattern is formed on the electroless copper plating layer with a dry film to perform electrolysis. A semi-additive method for forming a copper plating layer is often used.

  In the semi-additive method, after the dry film is peeled off, wet etching is performed to remove the electroless copper plating layer exposed by the peeling. However, this wet etching causes an undercut in which the lower portion of the wiring is etched and a wiring thinning that makes the wiring itself narrow. As a result, further miniaturization of the wiring is difficult.

  Therefore, after applying a photoresist containing an electroless plating catalyst (Pd) on the insulating layer and patterning it to a desired shape, electroless plating is performed in a state where the catalyst is left only in a region where wiring is formed, It has been proposed to form wiring (see, for example, Patent Document 1).

JP 05-206121 A

  However, although the method proposed in Patent Document 1 discloses a method for forming a wiring, it does not disclose any method for forming a via that connects a wiring layer and a wiring layer. For this reason, with the method proposed in Patent Document 1, only a wiring substrate having a single wiring layer can be obtained.

  The present invention has been made in response to the above-described circumstances, and an object thereof is to provide a method of manufacturing a wiring board having vias corresponding to miniaturization.

  To achieve the above object, the present invention includes a step of forming a via hole in an insulating layer, a step of forming a via conductor by filling the via hole with a conductive material, and forming a main catalyst layer on the insulating layer. A step of forming a mask having a first opening having a desired pattern on the main catalyst layer, and a main conductor layer on the main catalyst layer exposed from the first opening by an electroless plating method. , A step of peeling the mask, and a step of removing the main catalyst layer in a portion exposed by peeling of the mask.

  According to the present invention, when the main catalyst layer is removed, it is possible to suppress the occurrence of undercut in which the lower portion of the main conductor layer to be a wiring is etched and the thinning of the wiring itself. In addition, since the via conductor is formed prior to the formation of the main conductor layer, it is possible to suppress the filling failure of the via conductor.

  In one aspect of the present invention, a step of forming a via hole in the insulating layer, a step of filling the via hole with a conductive material to form a via conductor, a step of forming a main catalyst layer on the insulating layer, Forming a mask having a second opening having a desired pattern on the main catalyst layer; removing a portion of the main catalyst layer exposed from the mask; and peeling the mask; And a step of forming a main conductor layer on the main catalyst layer by an electroless plating method in this order.

  According to one embodiment of the present invention, when the main catalyst layer is removed, it is possible to suppress the occurrence of undercut in which the lower portion of the wiring is etched, or wiring thinning in which the wiring itself is thinned.

  In another aspect of the present invention, the step of forming the via conductor includes a step of forming a sub-catalyst layer on the insulating layer including an inner wall surface of the via hole, and an electroless plating method on the sub-catalyst layer Forming a sub conductor layer, and removing the sub conductor layer formed in a region excluding the inside of the via hole to form the via conductor in the via hole.

  According to another aspect of the present invention, it is possible to reliably form a via conductor having no filling failure.

  In another aspect of the present invention, the step of forming the via conductor is formed in a region other than the step of forming a sub catalyst layer on the insulating layer including the inner wall surface of the via hole and the inner wall surface of the via hole. Removing the secondary catalyst layer, and forming the via conductor on the secondary catalyst layer formed on the inner wall surface of the via hole by an electroless plating method. .

  According to another aspect of the present invention, since the sub-catalyst layer is removed before forming the via conductor, there is no possibility that the via conductor is etched.

  In another aspect of the present invention, in the step of forming the via hole, the via hole is formed by forming a through hole penetrating the protective layer and the insulating layer in a state having a protective layer on the insulating layer. In the step of forming the sub catalyst layer, the sub catalyst layer is formed on the inner wall surface of the via hole and the surface of the protective layer, and the protective layer is removed, so that the region other than the inner wall surface of the via hole is formed. The formed sub catalyst layer is removed.

  According to another aspect of the present invention, a via hole is formed by forming a through hole penetrating the protective layer and the insulating layer in a state having the protective layer on the insulating layer, and the inner wall surface of the via hole and the protective layer After forming the secondary catalyst layer on the surface, the protective layer is removed to remove the secondary catalyst layer formed in the region other than the inner wall surface of the via hole, so that it is formed in the region other than the inner wall surface of the via hole. The secondary catalyst layer can be easily removed. Further, since etching is not necessary for removing the sub catalyst layer, it is possible to suppress the via conductor from being etched.

  In another aspect of the present invention, the step of forming the via conductor is formed in a region excluding the inside of the via hole and the step of forming a sub-conductor layer on the insulating layer including the inside of the via hole by a printing method. And removing the sub conductor layer and forming the via conductor in the via hole.

  According to another aspect of the present invention, after the sub-conductor layer is formed by a printing method, the sub-conductor layer formed in a region other than the inside of the via hole is removed to form a via conductor in the via hole. For this reason, it is not necessary to form a catalyst layer for forming the via conductor, and the process can be simplified.

  In another aspect of the present invention, in the step of forming the via hole, the via hole is formed by forming a through hole penetrating the protective layer and the insulating layer in a state having a protective layer on the insulating layer. In the step of forming the sub-conductor layer, the sub-conductor layer is formed on the inner wall surface of the via hole and the surface of the protective layer, and the protective layer is removed, so that the sub-conductor layer is formed in a region excluding the inside of the via hole. The sub conductor layer is removed.

  According to another aspect of the present invention, the via hole is formed by forming a through hole penetrating the protective layer and the insulating layer in a state having the protective layer on the insulating layer, and the inner wall surface of the via hole and the protective layer After forming the sub-conductor layer on the surface, the sub-conductor layer formed in the region excluding the inside of the via hole is removed by removing the protective layer, so the sub-conductor formed in the region excluding the inside of the via hole The layer can be easily removed.

  In another aspect of the present invention, the step of forming the via conductor includes a step of filling the via hole with a conductive paste and forming the via conductor in the via hole by an inkjet method. .

  According to another aspect of the present invention, the via paste is filled in the via hole by the ink jet method, and the via conductor is formed in the via hole. For this reason, it is not necessary to form a catalyst layer for forming the via conductor, and the process can be simplified.

  In another aspect of the present invention, the main catalyst layer is formed by depositing Pd particles on the insulating layer.

  According to another aspect of the present invention, since the Pd particles are adhered on the insulating layer as the main catalyst layer, the main conductor layer can be more reliably formed on the insulating layer using electroless plating.

  In another aspect of the present invention, the main catalyst layer is removed with a chemical solution.

  According to the other aspect of the present invention, the main catalyst layer is removed by the chemical solution, so that there is no possibility that the wiring and via conductor are etched by the etching solution.

  As described above, according to the present invention, it is possible to provide a method for manufacturing a wiring board having vias corresponding to miniaturization.

Sectional drawing of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on the other example of embodiment. The manufacturing process figure of the wiring board which concerns on the other example of embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
FIG. 1 is a cross-sectional view of a wiring board 100 in the embodiment. As shown in FIG. 1, the wiring board 100 includes resin insulating layers 101 and 103, main conductor layers 102 and 104 including a wiring pattern, and filled vias 105 (hereinafter referred to as vias 105). The resin insulating layers 101 and 103 are made of, for example, a thermosetting insulating resin material mainly composed of an epoxy resin. The main conductor layers 102 and 104 are made of a conductive material, for example, a metal such as copper (Cu).

  The via 105 includes a via hole 105a formed in the resin insulating layer 103 and a via conductor 105b made of a conductive material (for example, copper (Cu)) filled inside the via hole 105a. The via 105 electrically connects the main conductor layer 102 and the main conductor layer 104.

  2-6 is a figure which shows the manufacturing process of the wiring board 100 which concerns on embodiment. Hereinafter, the manufacturing process of the wiring board 100 will be described with reference to FIGS.

  First, the main catalyst layer 201 is formed on the resin insulating layer 101 (see FIG. 2A). The main catalyst layer 201 is formed, for example, by depositing palladium (Pd) particles, which are a catalyst for electroless plating, on the resin insulating layer 101. Next, after laminating a photosensitive dry film on the surface of the main catalyst layer 201, exposure and development are performed to form a mask M1 having an opening K1 forming a desired pattern (see FIG. 2B). Next, electroless copper plating is performed on the main catalyst layer 201 exposed from the opening K1 of the mask M1, thereby forming a copper plating layer C1 to be the main conductor layer 102 (see FIG. 2C).

  Next, after peeling off the mask M1, the main catalyst layer 201 in a portion exposed by peeling off the mask M1 is removed (see FIG. 3A). For the removal of the main catalyst layer 201, it is preferable to use a chemical that can remove only the main catalyst layer 201. This is for preventing undercutting or thinning of the wiring pattern of the main conductor layer 102. For example, as the chemical solution that can remove only the main catalyst layer 201, a cyan aqueous solution such as a sodium cyanide aqueous solution can be used. In addition, as shown to Fig.3 (a), the main conductor layer 102 is comprised by the main catalyst layer 201 and the copper plating layer C1.

  Next, on the resin insulating layer 101 on which the main conductor layer 102 is formed in a state in which a film-shaped insulating resin material mainly composed of an epoxy resin to be the resin insulating layer 103 has a protective film HF (protective layer) on the surface. It arrange | positions and pressurizes and heats with a vacuum press-bonding hot press machine, and it crimps | bonds, heat-curing a film-form insulating resin material, and forms the resin insulating layer 103 (refer FIG.3 (b)). Next, laser irradiation is performed using a conventionally known laser processing apparatus to form a through hole that penetrates the protective film HF and the resin insulating layer 103, thereby forming a via hole 105a (see FIG. 3C).

  Next, the sub catalyst layer 202 is formed on the resin insulating layer 103 including the inner wall surface of the via hole 105a (see FIG. 4A). The sub-catalyst layer 202 is formed, for example, by depositing palladium (Pd) particles, which are a catalyst for electroless plating, on the inner wall surface of the via hole 105a and the protective film HF. Next, the protective film HF is peeled off, and the sub-catalyst layer 202 formed in a region other than the inner wall surface of the via hole 105a is removed (see FIG. 4B). Next, electroless copper plating is performed to form a copper plating layer C2 (sub conductor layer) to be the via conductor 105b in the via hole 105a, thereby obtaining the via 105 (see FIG. 4C). As shown in FIG. 4C, the via conductor 105b is composed of the sub catalyst layer 202 and the copper plating layer C2.

  In the above description, the method for forming the sub-catalyst layer 202 with the protective film HF (protective layer) is described. However, the protective film HF (protective layer) is formed on the resin insulating layer 103 when the sub-catalyst layer 202 is formed. ) May not be included. In this case, the sub-catalyst layer 202 is formed on the surface of the resin insulating layer 103 including the inner wall surface of the via hole 105a, and a copper plating layer is formed on the surface of the resin insulating layer 103 including the inner wall surface of the via hole 105a by performing electroless copper plating. (Sub conductor layer) will be formed, but the copper plating layer formed in the region excluding the inside of the via hole 105a may be removed by polishing or the like.

  The via conductor 105b may be formed by electroless copper plating, or by filling the via hole 105a with a conductive paste by a printing method and then peeling off the protective film HF to form the via conductor 105b. . Further, after peeling off the protective film HF, the conductor paste may be filled in the via hole 105a by a printing method, and then the conductor paste other than the conductor paste filled in the via hole 105a may be removed. When the via conductor 105b is formed by a printing method, it is not necessary to form the sub catalyst layer 202 for forming the via conductor 105b.

  Alternatively, the via conductor 105b may be formed by filling the via hole 105a with a conductive paste by an ink jet method. When the inkjet method is used, the conductor paste is filled only in the via hole 105a. For this reason, even if the conductive paste is filled in the via hole 105a after the protective film HF is peeled off, it is not necessary to remove the excess conductive paste. As a result, the manufacturing process of the wiring board 100 can be simplified. Even when the via conductor 105b is formed by the inkjet method, it is not necessary to form the sub-catalyst layer 202 in order to form the via conductor 105b.

  Next, the main catalyst layer 203 is formed on the resin insulating layer 103 including the surface of the via conductor 105b (see FIG. 5A). The main catalyst layer 203 is formed, for example, by depositing palladium (Pd) particles, which are a catalyst for electroless plating, on the resin insulating layer 103 including the surface of the via conductor 105b. Next, after laminating a photosensitive dry film on the surface of the main catalyst layer 203, exposure and development are performed to form a mask M2 having an opening K2 (first opening) of a desired pattern (FIG. 5B). )reference). Next, electroless copper plating is performed on the main catalyst layer 203 exposed from the opening K2 of the mask M2 to form a copper plating layer C3 to be the main conductor layer 104 (see FIG. 5C).

  Next, after peeling off the mask M2, the main catalyst layer 203 exposed by peeling off the mask M2 is removed to obtain the wiring board 100 shown in FIG. Here, the main conductor layer 104 shown in FIG. 1 includes the main catalyst layer 203 and the copper plating layer C3. In addition, it is preferable to use the chemical | medical solution which can remove only the main catalyst layer 201 for the removal of this main catalyst layer 203. FIG. This is to prevent undercutting or thinning of the wiring pattern of the main conductor layer 104.

  In the step of forming the main conductor layer 102, after forming the main catalyst layer 201 on the resin insulating layer 101, a mask M1 having an opening K1 having a desired pattern is formed, and the main catalyst exposed from the mask M1 is formed. Electroless copper plating is performed on the layer 201 to form a copper plating layer C1 to be the main conductor layer 102, thereby forming the main conductor layer 102. However, the formation of the main conductor layer 102 is not limited to the above method.

  6 and 7 are diagrams showing a manufacturing process of the wiring board 100 according to another example of the embodiment. Hereinafter, with reference to FIGS. 6 and 7, a manufacturing process of the wiring substrate 100 according to another example will be described. In addition, the same code | symbol is attached | subjected to the structure same as the structure of the wiring board 100 demonstrated with reference to FIGS. 1-5, and the overlapping description is abbreviate | omitted.

  First, the main catalyst layer 201 is formed on the resin insulating layer 101 (see FIG. 6A). Next, after laminating a photosensitive dry film on the surface of the main catalyst layer 201, exposure and development are performed to form a mask M3 having an opening K3 (second opening) of a desired pattern (FIG. 6B). )reference). Next, the main catalyst layer 201 exposed from the opening K3 of the mask M3 is removed using a chemical solution (see FIG. 6C).

  Next, the mask M3 is peeled off (see FIG. 7A). Next, electroless copper plating is performed on the main catalyst layer 201 exposed by peeling off the mask M3 to form an electroless copper plating layer C1, thereby obtaining the main conductor layer 102 (see FIG. 7B). The main conductor layer 104 can also be formed by the above-described method described with reference to FIGS. Note that the method described with reference to FIGS. 6 and 7 differs in the position of the opening of the mask to be formed.

  As described above, according to the method for manufacturing the wiring substrate 100 according to the present embodiment, it is not necessary to perform wet etching in order to remove the electroless copper plating layers C1 and C3 as in the related art. Further, a chemical solution that removes only palladium (Pd), which is an electroless plating catalyst, is used to remove the main catalyst layers 201 and 203 and the sub catalyst layer 202. For this reason, there is no possibility of undercut or thinning of the wiring in which the lower portions of the wiring patterns of the main conductor layers 102 and 104 are etched. For this reason, it is suitable for manufacturing a wiring board having a fine wiring pattern, particularly a wiring board having a wiring pattern with a wiring width of 5 μm or less.

  Also in the process of forming the via conductor 105b, it is not necessary to perform wet etching in order to remove the electroless copper plating layer. For this reason, there is no possibility that the via conductor 105b is etched, and the connection reliability between the main conductor layer 102 and the main conductor layer 104 is improved. Further, after forming the resin insulating layer 103 by pressurizing and heating the film-like insulating resin material with the protective film HF (protective layer) on the surface, the sub catalyst layer 202 is formed with the protective film HF. Therefore, the secondary catalyst layer 202 formed in the region other than the inner wall surface of the via hole 105a can be easily removed by simply removing the protective film HF.

  Further, when the via conductor 105b is formed by the ink jet method, it is not necessary to remove the sub conductor layer C2 formed in a region other than the inside of the via hole 105a, and the manufacturing process of the wiring board 100 can be simplified.

  In the wiring substrate 100 manufactured by the manufacturing method of the present embodiment, as described above, the main catalyst layer 203 formed of palladium (Pd) particles remains between the copper plating layer C3 and the via conductor 105b. (See FIG. 5C). For the main catalyst layer 203 formed of the palladium (Pd) particles, EDX (energy dispersive X-ray analysis), EPMA (electron probe microanalysis), AES (Auger electron spectroscopy), SIMS (secondary ion mass) It can be confirmed by performing an analysis such as (Analysis).

(Other embodiments)
The present invention has been described in detail with reference to specific examples. However, the present invention is not limited to the above contents, and various modifications and changes can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 100 ... Wiring board, 101, 103 ... Resin insulation layer, 102, 104 ... Main conductor layer, 105 ... Filled via, 105a ... Via hole, 105b ... Via conductor, 201, 203 ... Main catalyst layer, 202 ... Sub catalyst layer, K1- K3 ... opening, M1 to M3 ... mask, HF ... protective film.

Claims (10)

Forming a via hole in the insulating layer;
Filling the via hole with a conductive material to form a via conductor;
Forming a main catalyst layer on the insulating layer;
Forming a mask having a first opening in a desired pattern on the main catalyst layer;
Forming a main conductor layer on the main catalyst layer exposed from the first opening by an electroless plating method;
Peeling the mask;
Removing the portion of the main catalyst layer exposed by peeling of the mask;
A method of manufacturing a wiring board, comprising: Forming a via hole in the insulating layer;
Filling the via hole with a conductive material to form a via conductor;
Forming a main catalyst layer on the insulating layer;
Forming a mask having a second opening in a desired pattern on the main catalyst layer;
Removing a portion of the main catalyst layer exposed from the mask;
Peeling the mask;
Forming a main conductor layer on the main catalyst layer by an electroless plating method;
A method of manufacturing a wiring board, comprising: The step of forming the via conductor includes
Forming a sub-catalyst layer on the insulating layer including the inner wall surface of the via hole;
Forming a sub-conductor layer on the sub-catalyst layer by an electroless plating method;
Removing the sub-conductor layer formed in a region excluding the inside of the via hole, and forming the via conductor in the via hole;
The method for manufacturing a wiring board according to claim 1, wherein: The step of forming the via conductor includes
Forming a sub-catalyst layer on the insulating layer including the inner wall surface of the via hole;
Removing the sub-catalyst layer formed in a region other than the inner wall surface of the via hole;
Forming the via conductor on the sub-catalyst layer formed on the inner wall surface of the via hole by an electroless plating method;
The method for manufacturing a wiring board according to claim 1, wherein: In the step of forming the via hole, the via hole is formed by forming a through hole penetrating the protective layer and the insulating layer in a state having a protective layer on the insulating layer,
In the step of forming the sub catalyst layer, the sub catalyst layer is formed on the inner wall surface of the via hole and the surface of the protective layer,
The method of manufacturing a wiring board according to claim 4, wherein the sub catalyst layer formed in a region other than the inner wall surface of the via hole is removed by removing the protective layer. The step of forming the via conductor includes
Forming a sub conductor layer on the insulating layer including the inside of the via hole by a printing method;
Removing the sub-conductor layer formed in a region excluding the inside of the via hole, and forming the via conductor in the via hole;
The method for manufacturing a wiring board according to claim 1, wherein: In the step of forming the via hole, the via hole is formed by forming a through hole penetrating the protective layer and the insulating layer in a state having a protective layer on the insulating layer,
In the step of forming the sub conductor layer, the sub conductor layer is formed on the inner wall surface of the via hole and the surface of the protective layer,
The method for manufacturing a wiring board according to claim 6, wherein the sub-conductor layer formed in a region excluding the inside of the via hole is removed by removing the protective layer. The step of forming the via conductor includes
3. The method for manufacturing a wiring board according to claim 1, further comprising a step of filling the via hole with a conductive paste and forming the via conductor in the via hole by an inkjet method.   The method for manufacturing a wiring board according to claim 1, wherein the main catalyst layer is formed by attaching Pd particles on the insulating layer.   The method for manufacturing a wiring board according to claim 1, wherein the main catalyst layer is removed with a chemical solution.

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