JP2014093488A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows avoiding an increase in chip size while enabling analysis using a TEG even after product shipment.SOLUTION: A semiconductor device 1 includes an active region A1 having a semiconductor layer including, for example, a base diffusion layer 13 and an emitter diffusion layer 14. TEGs 21, which are structures for evaluation including constituent elements of the active region A1, are provided at outside corner portions of a primary surface of the active region A1.

Description

  The present invention relates to a semiconductor device.

  As a semiconductor device evaluation method, an evaluation method using TEG (Test Element Group) is known. TEG is used to investigate the causes of problems that occur at various stages such as process development, design, and manufacturing of semiconductor devices. It is an evaluation element or an evaluation structure that can be investigated early by configuring a suitable dedicated circuit or structure.

  FIG. 1A and FIG. 1B are plan views showing the arrangement of conventional TEGs in a semiconductor wafer. As shown in FIG. 1A, the TEG 100 indicated by hatching in the drawing may be formed in the surface of the wafer 200 at the expense of some of the mass production chips 110. However, in this case, the number of mass production chips obtained from one wafer is reduced. Therefore, at the stage where the manufacturing process is stabilized and the improvement in yield is confirmed, it is common to form the TEG only on the dicing line (scribe line) L as shown in FIG.

  In Patent Document 1, an accessory pattern (TEG) is formed in a scribe line region through which a dicing blade passes in a dicing process when solidifying a semiconductor wafer into a plurality of chips, and the accessory pattern is cut during dicing. Is described.

JP 2010-129695 A

  When a TEG is formed on a dicing line (scribe line) as described in Patent Document 1, the TEG is removed by cutting with a dicing blade during dicing. On the semiconductor chip separated by dicing, the TEG fragments cut and removed may remain at the edge portion of the semiconductor chip, but these no longer function effectively as a TEG. Therefore, for example, when a defect occurs in the semiconductor device after product shipment, analysis using the TEG cannot be performed, and the actual product in which the defect has occurred is analyzed. However, in the analysis of the semiconductor device itself in which a failure has occurred, it may be difficult to isolate the root cause of the failure because only complex data including a plurality of circuit elements and a plurality of structural elements can be obtained. . In addition, when the semiconductor device is subjected to relatively large damage such as burnout, it is difficult to obtain appropriate electrical characteristics from the actual product in which a defect has occurred. On the other hand, according to failure analysis using TEG, detailed evaluation and analysis for each component of the semiconductor device can be performed. Therefore, by incorporating a TEG in a semiconductor device for mass production shipment, various evaluations and analyzes using the TEG can be performed even after product shipment. However, in this case, it is necessary to secure an area for forming the TEG in the semiconductor chip formation area, which may increase the size of the semiconductor chip. Since semiconductor chips are manufactured on a limited area called a wafer, an increase in the size of the semiconductor chips reduces the number of semiconductor chips manufactured from a single wafer, which in turn increases the cost of the semiconductor chips. .

  The present invention has been made in view of the above points, and provides a semiconductor device capable of avoiding an increase in chip size while enabling analysis using TEG even after product shipment. With the goal.

  In order to achieve the above object, a semiconductor device according to the present invention includes a main surface having a rectangular shape, an active region provided in the main surface and including at least one semiconductor layer, and an outer periphery of the active region. And a structure for evaluation including a component for evaluating the active region, which is provided at a corner portion of the main surface outside the pressure-resistant structure.

  Another semiconductor device according to the present invention includes a main surface having a rectangular shape, an active region provided in the main surface and including at least one semiconductor layer, and the main surface outside the active region. An evaluation structure provided in a corner portion and including a component for evaluating the active region, and arranged in a direction inclined with respect to a side defining the main surface in the corner portion of the main surface and the evaluation A plurality of electrode pads connected to the structural body.

  According to the semiconductor device of the present invention, it is possible to provide a semiconductor device capable of avoiding an increase in chip size while enabling analysis using TEG even after product shipment.

FIG. 1A and FIG. 1B are plan views showing the arrangement of conventional TEGs. 2A is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line 2b-2b in FIG. 2A. . It is a top view which shows the partial structure of the semiconductor wafer containing multiple semiconductor devices which concern on embodiment of this invention. It is a top view which shows the 1st example of a structure of TEG which concerns on embodiment of this invention. It is a top view which shows the 2nd example of a structure of TEG which concerns on embodiment of this invention. It is sectional drawing which shows the 3rd example of a structure of TEG which concerns on embodiment of this invention. It is a top view which shows the structure of the semiconductor device which concerns on embodiment of this invention. FIG. 8A is a plan view showing a corner portion of the semiconductor device according to the second embodiment of the present invention. FIG. 8B is a plan view showing a corner portion of the semiconductor device according to the comparative example.

  As described above, the TEG is used in various stages such as process development, design, and manufacture of a semiconductor device and is not used after shipment. The placement of the TEG in the chip area increases the chip size. It was. However, the inventor overcame the conventional fixing concept, and obtained the idea that the TEG is formed in the semiconductor region without increasing the chip size, and that the TEG is utilized even after product shipment.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

[First embodiment]
2A is a plan view showing the configuration of the semiconductor device 1 according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line 2b-2b in FIG. 2A. is there. In the present embodiment, the semiconductor device 1 constitutes a planar bipolar transistor having a rectangular main surface.

  The collector layer 11 is an n-type semiconductor layer formed by doping a semiconductor substrate with an additive impurity such as antimony at a high concentration, and constitutes a collector region of the transistor. The collector layer 11 is formed on the back side of the semiconductor device 1. The epitaxial layer 12 is a relatively low concentration n-type semiconductor layer formed on the surface of the collector layer 11 by, for example, a vapor phase growth method in which a silane compound and a phosphorus compound are decomposed at a high temperature.

  The base diffusion layer 13 is a p-type semiconductor layer formed by thermally diffusing impurities after adding boron or the like to the surface of the epitaxial layer 12 via a patterning mask (not shown). Configure the base area. The emitter diffusion layer 14 is a relatively high concentration n-type semiconductor layer formed by thermally diffusing an additive impurity such as phosphorus on the surface of the base diffusion layer 13 through a patterning mask (not shown). . When viewed from above, the base diffusion layer 13 is formed so as to surround the entire emitter diffusion layer 14. The base diffusion layer 13 and the emitter diffusion layer 14 have a polygonal shape having sides along the sides of the semiconductor device 1 having a rectangular shape. For the purpose of alleviating electric field concentration during reverse bias, Curved to draw a gentle arc.

The emitter electrode 15 is made of a conductor such as aluminum and is formed so as to cover the surface of the emitter diffusion layer 14. Similarly to the emitter electrode 15, the base electrode 16 is made of a conductor such as aluminum and is formed so as to cover the surface of the base diffusion layer 15. An insulating film 17 such as SiO ₂ is provided between the emitter electrode 15 and the base electrode 16, and the emitter electrode 15 and the base electrode 16 are electrically separated.

As shown in FIG. 2A, in the semiconductor device 1, the emitter electrode 15 and the base electrode 16 are exposed on the rectangular main surface. The emitter electrode 15 has substantially the same shape as that of the emitter diffusion layer 14, and each corner portion is curved so as to draw a gentle arc. The emitter electrode 15 itself constitutes a bonding pad for connecting a bonding wire. On the other hand, the base electrode 16 is formed along the outer edge of the base diffusion layer 13, has an annular pattern surrounding the entire emitter electrode 15, and a bonding pad 16a for connecting a bonding wire connected to the annular pattern. Have Similarly to the emitter electrode 15, the base electrode 16 is curved so that each corner portion forms a gentle arc. An insulating film 17 such as SiO ₂ extends outside the base electrode 16.

  In the semiconductor device 1 according to the present embodiment, a region inside the base diffusion layer 13 and the base electrode 16 is an active region A1 in which transistor operation is performed, and a region outside the base diffusion layer is an inactive region A2. . Note that in this specification, an active region refers to a region where an operation for performing a main function of a semiconductor device is performed. In the semiconductor device 1 according to the present embodiment, the base diffusion layer 13 and the base electrode 16 that define the outer edge of the active region A1 are curved so that each corner portion is rounded as described above. Therefore, the corner portion of the active region A1 is surrounded by the dicing line and has a relatively wide area between each corner portion of the base electrode 16 and the side of the semiconductor device 1 having a rectangular shape cut out by dicing. In addition, a substantially triangular region 20 (shown by hatching in FIG. 2A) is formed in the inactive region A2. The tangent line of the corner portion of the active region A1 is, for example, a straight line inclined by 45 ° with respect to the side of the semiconductor device 1, and the area of the active region A1 is preferably maximized. In the semiconductor device 1 according to the present embodiment, the TEG 21 is formed in the region 20 located at the corner portion of the semiconductor device 1.

  FIG. 3 is a plan view showing a partial configuration of a semiconductor wafer 50 including a plurality of semiconductor devices 1 according to the embodiment of the present invention. As shown in FIG. 3, in the semiconductor device 1 according to the present embodiment, the TEG 21 provided on the conventional dicing line (scribe line) L is incorporated in the semiconductor device 1. That is, even if the semiconductor wafer 50 is diced to separate the semiconductor device 1, the TEG 21 is not cut off.

  The TEG 21 includes an element included in the active region A1 of the semiconductor device 1, and is an evaluation element or an evaluation structure configured to be able to quantitatively evaluate the characteristics and structure performance of each element. It is. The specific configuration of the TEG 21 varies depending on the characteristics (parameters) to be acquired, but some examples are given below.

  FIG. 4 is a plan view showing a first example of the configuration of the TEG 21. The TEG 21 includes a first resistance element R1 for evaluating the resistance value of the base diffusion layer 13 provided in the active region A1, and a second resistance element R2 for evaluating the resistance value of the emitter diffusion layer 14. Contains. The first resistance element R1 is composed of a p-type semiconductor formed by the same process as the base diffusion layer 13 provided in the active region A1, and is preferably formed simultaneously with the base diffusion layer 13. A contact portion 211 connected to an electrode pad (not shown) is provided at both ends of the first resistance element R1, and a resistance of the first resistance element R1 is obtained by bringing a probe (probe) into contact with the electrode pad. The value can be measured. An n-type semiconductor layer 212 extends around the first resistance element R1. The n-type semiconductor layer 212 is preferably composed of an n-type semiconductor formed by the same process as the epitaxial layer 12 and is formed simultaneously with the epitaxial layer 12. On the other hand, the second resistance element R2 is made of an n-type semiconductor formed by the same process as the emitter diffusion layer 14 provided in the active region A1, and is formed simultaneously with the emitter diffusion layer 14. A contact portion 213 connected to an electrode pad (not shown) is provided at both ends of the second resistance element R2, and the resistance of the second resistance element R2 is brought into contact with the electrode pad by contacting a probe (probe). The value can be measured. A p-type semiconductor layer 214 extends around the second resistance element R2. The p-type semiconductor layer 214 is preferably composed of a p-type semiconductor formed by the same process as the base diffusion layer 13 and is formed simultaneously with the base diffusion layer 13.

  According to the configuration of the TEG 21 as shown in FIG. 4, the resistance value of the first resistance element R <b> 1 is equivalent to that of the base diffusion layer 13, and the resistance value of the second resistance element R <b> 2 is equivalent to that of the emitter diffusion layer 14. The resistance value becomes. Therefore, when a problem occurs in the semiconductor device 1, the resistance values of the base diffusion layer 13 and the emitter diffusion layer 14 can be estimated by measuring the first resistance element R1 and the second resistance element R2. This makes it possible to determine whether or not there is an abnormality in the base diffusion layer 13 and the emitter diffusion layer 14 at the initial stage of failure analysis.

  FIG. 5 is a plan view showing a second example of the configuration of the TEG 21. In the example shown in FIG. 5, the TEG 21 forms a so-called contact chain. That is, the TEG 21 includes a plurality of diffusion layers 221 and conductor wirings 223 connected to the diffusion layers 221 at the contact portions 222 at both ends of each diffusion layer 221. The contact part 222 is formed by the same process as the contact part formed in the active region A1. An insulating film (not shown) is provided between the diffusion layer 221 and the conductor wiring 223, and the conductor wiring 223 is connected to the diffusion layer 221 through a contact hole provided in the insulating film. The plurality of diffusion layers 221 are connected in series via the conductor wiring 223. An electrode pad 224 is connected to a terminal portion of the diffusion layer 221 connected in series, and a total value of contact resistance in the contact portion 222 can be obtained by bringing a probe (probe) into contact with the electrode pad 224. It is possible. Each of the plurality of diffusion layers 221 is made of, for example, an n-type semiconductor formed by the same process as the emitter diffusion layer 14 and is formed simultaneously with the emitter diffusion layer 14. On the other hand, the conductor wiring 223 is made of a conductor such as aluminum formed by the same process as the emitter electrode 15 and the base electrode 16, and is formed simultaneously with the emitter electrode 15 and the base electrode 16. That is, the contact chain constituting the TEG 21 includes a plurality of contact portions 222 having the same structure as the contact portion between the emitter diffusion layer 14 and the emitter electrode 15 in the active region A1.

  According to the configuration of the TEG 21 as shown in FIG. 5, when a failure occurs in the semiconductor device 1, the contact between the emitter diffusion layer 14 and the emitter electrode 15 is measured by measuring the resistance value between the electrode pads 224. Resistance can be estimated. This makes it possible to determine whether or not there is an abnormality in the electrical connection between the emitter diffusion layer 14 and the emitter electrode 15 at the initial stage of failure analysis. In the TEG 21, the contact resistance between the base diffusion layer 13 and the base electrode 16 can be estimated by configuring the plurality of diffusion layers 221 with a p-type semiconductor formed by the same process as the base diffusion layer 13. May be. Further, the contact portion 222 does not need to have the same structure as the contact portion provided in the active region A1. For example, in consideration of variations occurring in the manufacturing process, the contact portion 222 may be formed with an area smaller than the area of the contact portion provided in the active region A1 (that is, a small opening diameter). Thereby, it can be set as the structure which detects a malfunction with sufficient sensitivity.

  FIG. 6 is a cross-sectional view showing a third example of the configuration of the TEG 21. In the example shown in FIG. 6, the TEG 21 has a layer structure for performing a spreading resistance analysis (SRA) of the semiconductor layer in the active region A1. The spreading resistance analysis is a technique for analyzing the carrier concentration distribution in the depth direction of each layer constituting the semiconductor device. In the example shown in FIG. 6, the TEG 21 has the same layer configuration as each semiconductor layer in the active region A <b> 1 of the semiconductor device 1. That is, the n-type semiconductor layer 231 corresponds to the collector layer 11 in the active region A1, is formed by the same process as the collector layer 11, and is formed at the same depth position as the collector layer 11. The n-type semiconductor layer 232 corresponds to the epitaxial layer 12 in the active region A1, is formed by the same process as the epitaxial layer 12, and is formed at the same depth position as the epitaxial layer 12. The p-type semiconductor layer 233 corresponds to the base diffusion layer 13 in the active region A1, is formed by the same process as the base diffusion layer 13, and is formed at the same depth as the base diffusion layer 13. The n-type semiconductor layer 234 corresponds to the emitter diffusion layer 14 in the active region A1, is formed by the same process as the emitter diffusion layer 14, and is formed at the same depth position as the emitter diffusion layer 14.

  According to the configuration of the TEG 21 as shown in FIG. 6, the depth of the n-type semiconductor layer 231, the n-type semiconductor layer 232, the p-type semiconductor layer 233, and the n-type semiconductor layer 234 formed by the same process as that of the active region A1. The carrier concentration distribution in the direction is equivalent to the carrier concentration distribution in the depth direction of the active region A1. Equivalent means that the carrier concentration distribution is equal within the range of differences due to manufacturing variations. When a failure occurs in the semiconductor device 1, the carrier concentration distribution in the depth direction of each layer in the active region A1 of the semiconductor device 1 can be estimated by measuring the spreading resistance of the TEG 21. Therefore, it is possible to determine whether or not there is an abnormality in the carrier concentration distribution of each semiconductor layer of the semiconductor device 1 at the initial stage of failure analysis. The spreading resistance can be measured by bringing a probe (probe) into contact with each of the layers 231 to 234 exposed by polishing the TEG 21 in an oblique direction. It is possible to determine the resistivity and carrier concentration of each layer 231 to 234 from the resistance value obtained by the spreading resistance measurement.

  In addition to the above, the TEG 21 has a structure evaluation pattern including a structure portion equivalent to or corresponding to the structure portion formed in the active region A1 for the purpose of evaluating the performance of the structure of the semiconductor device 1. May be included. For example, the thickness and patterning shape of the insulating film 17, the emitter electrode 15 and the base electrode 16 formed in the active region A <b> 1 of the semiconductor device 1, the size and shape of the contact opening or etching portion formed in the insulating film 17, etc. A standard structure for determining whether or not it is appropriate may be included as the structure evaluation pattern. This standard structure may have substantially the same shape and dimensions as the constituent parts of the semiconductor device 1 to be evaluated, or may have different shapes and dimensions. Even if the standard structure formed as the TEG has a shape and dimensions different from those of the constituent parts of the semiconductor device 1 to be evaluated, it is possible to determine whether or not the target process has been appropriately executed. . In any case, it is preferable to simultaneously form each structural portion of the TEG 21 using the same process as each corresponding structural portion in the active region A1.

  As described above, according to the semiconductor device 1 according to the embodiment of the present invention, since the TEG 21 having the elements and structure constituting the semiconductor device 1 is incorporated in the semiconductor device 1, the semiconductor device 1 is cut out from the wafer. Even when a failure occurs in the semiconductor device 1 later, the cause of the failure that occurred in the semiconductor device 1 can be quickly and accurately investigated by analyzing the TEG 21. That is, the conventional TEG is provided only on the dicing line (scribe line), and is cut and removed when the semiconductor wafer is diced, and the TEG does not exist in the separated semiconductor device. For this reason, when a malfunction occurs in the semiconductor device, the actual product in which the malfunction has occurred is analyzed. For example, the electrical characteristics of the semiconductor device are analyzed through electrode pads (for example, a base electrode pad and an emitter electrode pad) provided in the semiconductor device in which the problem has occurred. However, the characteristics obtained by such a measurement are complex including the characteristics of a plurality of components included in the semiconductor device, and thus it is difficult to isolate the root cause of the failure. In addition, when the semiconductor device is subjected to relatively large damage such as burnout, it is difficult to obtain appropriate electrical characteristics from the actual product in which a defect has occurred. On the other hand, according to the semiconductor device 1 according to the embodiment of the present invention, since the TEG 21 is attached to each semiconductor device 1, it is possible to perform analysis using the TEG 21 even after dicing. By analyzing the TEG 21, it is possible to directly and quantitatively obtain the performance and characteristics of each component of the semiconductor device 1. Further, since the TEG 21 is electrically separated from the active region A1, it is possible to obtain the electrical characteristics of the TEG 21 even when the active region A1 is burned out.

  Further, in the semiconductor device 1 according to the embodiment of the present invention, each corner portion of the base diffusion layer 13 and the base electrode 16 that defines the outer edge of the active region A1 is a gentle arc in order to reduce electric field concentration during reverse bias. Curved to draw. Therefore, a substantially triangular region 20 having a relatively wide area is formed in the inactive region A2 between each corner portion of the base electrode 16 and the side of the semiconductor device 1 having a rectangular shape cut out by dicing. The Since the TEG 21 is provided in the region 20 located in the corner portion of the semiconductor device 1, the TEG 21 can be incorporated into the semiconductor device 1 without increasing the area of the semiconductor device 1. As described above, according to the semiconductor device 1 according to the embodiment of the present invention, it is possible to perform an analysis using the TEG even after product shipment, and to avoid an increase in chip size.

  In the above-described embodiment, the TEG 21 is provided in each of the four corner portions of the semiconductor device 1. However, the TEG 21 may be provided in at least one corner portion of the semiconductor device 1. In the above embodiment, one TEG is disposed in the region 20 disposed in the corner portion of the semiconductor device 1. However, a plurality of types of TEGs having different evaluation purposes are disposed in the region 20. Also good. Further, a plurality of types of TEGs having different evaluation purposes may be distributed to the four corner portions of the semiconductor device 20. In the above embodiment, the TEG is not provided on the dicing line (scribe line) L. However, the TEG may be provided on the dicing line (scribe line) L.

  In the above-described embodiment, the case where the present invention is applied to a planar bipolar transistor has been exemplified. However, the present invention is not limited to this. For example, other discrete semiconductors such as a diode, a thyristor, a MOS FET, and an IGBT are used. Alternatively, the present invention can be applied to an integrated circuit (IC) including a plurality of semiconductor elements. Note that a TEG for an integrated circuit (IC) may include a circuit element such as a transistor, a resistor, or a capacitor included in the integrated circuit, or a functional block having a predetermined function. The case where the present invention is applied to a MOS FET will be described below.

  FIG. 7 is a plan view showing a configuration of a MOS FET as the semiconductor device 1a according to the embodiment of the present invention. The semiconductor device 1a includes a gate pad 31, a gate bus line 32, and an emitter pad 33 in an active region A1 where a transistor operation is performed. The active region A1 includes a plurality of MOS FET cells (not shown). Since the structure of the MOS FET cell is known, a detailed description is omitted. In the inactive region A2 outside the active region A1, a rectangular annular pressure-resistant structure portion 34 is provided so as to surround the outer periphery of the active region A1. The pressure | voltage resistant structure part 34 comprises the well-known FLR (Field Limiting Ling), for example. The FLR is composed of a plurality of concentric rectangular diffusion layers that are spaced apart from each other so as to surround the active region A1. The breakdown voltage structure 34 has a rectangular shape having sides substantially parallel to the sides of the semiconductor device 1 having a rectangular shape, but each corner portion has a gentle arc for the purpose of suppressing electric field concentration during reverse bias. Curved to draw. For this reason, a tangent and a dicing line of a corner portion of the pressure-resistant structure portion 34 having a relatively wide area between each corner portion of the pressure-resistant structure portion 34 and the side of the semiconductor device 1a having a rectangular shape cut out by dicing. A substantially triangular-shaped region 20 (shown by hatching in FIG. 7) surrounded is formed in the inactive region A2. The tangent line of the corner portion of the breakdown voltage structure portion 34 is, for example, a straight line inclined by 45 ° with respect to the side of the semiconductor device 1, and the area of the active region A1 is preferably maximized. In the semiconductor device 1a according to the present embodiment, the TEG 21 is formed in the region 20 located at the corner portion of the semiconductor device 1a. By disposing the TEG 21 at the corner of the semiconductor device 1a, the chip size can be increased while enabling analysis using the TEG even after product shipment, as in the case of the planar bipolar transistor described above. It can be avoided.

  As described above, particularly in discrete semiconductors, the corner portion at the outer edge of the breakdown voltage structure portion such as the FLR surrounding the active region and the active region has a curved shape for the purpose of preventing breakdown voltage drop due to local electric field concentration. A relatively large space is easily secured in the corner portion of the semiconductor device. In the semiconductor device according to the embodiment of the present invention, this chip corner portion is effectively used as a region for arranging the TEG.

[Second Embodiment]
The semiconductor device according to the second embodiment of the present invention will be described below. FIG. 8A is a plan view showing a corner portion of the semiconductor device 2 according to the second embodiment of the present invention. Similar to the semiconductor devices 1 and 1a according to the first embodiment, the semiconductor device 2 constitutes a discrete semiconductor such as a bipolar transistor, a MOS FET, or an IGBT, or an integrated circuit (IC). The TEG 21 is provided in the region 20 located in The TEG 21 has a plurality of electrode pads 22 electrically connected to an evaluation element such as a resistance element on the main surface of the semiconductor device 1 having a rectangular shape, and the TEG 21 is interposed via the electrode pads 22. It is possible to measure the electrical characteristics of the constituent element for evaluation.

  Each of the plurality of electrode pads 22 has a quadrangular shape having sides inclined by 45 ° with respect to the sides of the semiconductor device 2. Furthermore, the arrangement direction of the plurality of electrode pads 22 is a direction inclined by 45 ° with respect to the side of the semiconductor device 2 (a direction indicated by a broken-line arrow in FIG. 8A). Here, the arrangement direction means a direction in which the interval between the electrode pads 22 adjacent to each other is the shortest among the directions in which the electrode pads 22 are arranged. By arranging the plurality of electrode pads 22 in a direction inclined by 45 ° with respect to the side of the semiconductor device 2, the distance between the electrode pads 22 and the size of the electrode pads 22 are changed in the corner portion of the semiconductor device 1. Thus, it becomes possible to provide more electrode pads 22.

  Here, FIG. 8B is a plan view showing a corner portion of the semiconductor device 300 according to the comparative example in which the arrangement direction of the electrode pads 22 is directed in a direction different from the embodiment of the present invention described above. In the semiconductor device 300, the arrangement direction of the electrode pads 22 is a direction parallel to (or perpendicular to) the sides of the semiconductor device 300 (the direction indicated by the broken line arrow in FIG. 8B). As described above, when the arrangement direction of the electrode pads 22 is parallel (or perpendicular) to the sides of the semiconductor device 300, the electrode pads can be accommodated in the substantially triangular region 20 located at the corner portion of the semiconductor device 300. The number of 22 decreases compared to the case shown in FIG. That is, in the arrangement shown in FIG. 8B, the number of electrode pads 22 that can be arranged in the region 20 is 10, whereas according to the embodiment of the present invention shown in FIG. In the semiconductor device 2, twelve electrode pads 22 can be arranged in the region 20.

  FIG. 8A illustrates an arrangement of TEGs. For example, the TEG can be provided on a line that is inclined by 45 ° with respect to the side of the semiconductor device 2 and that is along the arrangement direction of the electrode pads 22, which is indicated by a broken-line arrow in FIG. In this case, for example, TEGs may be arranged between the sides of the two electrode pads 22 like TEG21 (A) and TEG21 (B). Moreover, you may arrange | position TEG between the vertexes of the two electrode pads 22, like TEG21 (C) and TEG21 (D).

  Thus, according to the semiconductor device 2 according to the second embodiment of the present invention, when the TEG 21 is provided in the corner portion of the semiconductor device 2, the electrode pads 22 of the TEG 21 can be efficiently arranged. Usually, since the size of the element or the structure constituting the TEG body is sufficiently small with respect to the size of the electrode pad 22, by providing more electrode pads 22, more TEG patterns can be formed in the corner portion of the semiconductor device. It can be provided. In the above embodiment, the electrode pad 22 has a quadrangular shape. However, the electrode pad 22 may have a polygonal shape other than the quadrangular shape, a circular shape, or an elliptical shape.

1, 1a, 2 Semiconductor device 11 Collector layer 13 Base diffusion layer 14 Emitter diffusion layer 15 Emitter electrode 16 Base electrode 17 Insulating film 21 TEG
22 Electrode pad 50 Semiconductor wafer

Claims (13)

A main surface having a rectangular shape;
An active region provided in the main surface and including at least one semiconductor layer;
A pressure-resistant structure surrounding the outer periphery of the active region;
An evaluation structure provided at a corner portion of the main surface outside the pressure-resistant structure portion and including a component for evaluating the active region;
A semiconductor device including:   The semiconductor device according to claim 1, wherein the evaluation structure includes a resistor made of a semiconductor layer formed by the same process as the semiconductor layer included in the active region. In the active region, the semiconductor layer and a conductor has a contact portion connected,
The semiconductor device according to claim 1, wherein the evaluation structure has a contact chain including a plurality of contact portions formed by the same process as the contact portion in the active region.   The semiconductor device according to claim 1, wherein the evaluation structure includes a semiconductor layer having a carrier concentration distribution equivalent to a carrier concentration distribution in a depth direction of the semiconductor layer in the active region.   2. The semiconductor device according to claim 1, wherein the evaluation structure has a structure evaluation pattern having a structure portion equivalent to or corresponding to a structure portion constituting the active region as a component for evaluating the active region. A main surface having a rectangular shape;
An active region provided in the main surface and including at least one semiconductor layer;
An evaluation structure provided at a corner portion of the main surface outside the active region and including a component for evaluating the active region;
A plurality of electrode pads arranged in a direction inclined with respect to a side defining the main surface at a corner portion of the main surface and connected to the evaluation structure;
A semiconductor device including:   The semiconductor device according to claim 6, wherein the plurality of electrode pads are arranged in a direction inclined by 45 ° with respect to a side defining the main surface.   The semiconductor device according to claim 6, wherein the evaluation structure is disposed between the plurality of electrode pads.   9. The semiconductor device according to claim 6, wherein the evaluation structure includes a resistor made of a semiconductor layer formed by the same process as the semiconductor layer included in the active region. In the active region, the semiconductor layer and a conductor has a contact portion connected,
9. The semiconductor device according to claim 6, wherein the evaluation structure includes a contact chain including a plurality of contact portions formed by the same process as the contact portion in the active region.   9. The semiconductor device according to claim 6, wherein the evaluation structure includes a semiconductor layer having a carrier concentration distribution equivalent to a carrier concentration distribution in a depth direction of the semiconductor layer in the active region.   The semiconductor device according to claim 1, wherein the evaluation structure is provided in each corner portion of the main surface.   The semiconductor device according to claim 12, wherein the evaluation structures provided at each corner portion of the main surface have different structures.