JP5540808B2 - Semiconductor wafer - Google Patents

Description

  The present invention relates to a semiconductor wafer provided with a test pad for evaluating characteristics of a semiconductor device.

  A plurality of semiconductor devices and test pads connected to the terminals of the semiconductor devices are formed on the semiconductor wafer. Then, by applying a voltage from the test probe to the test pad, a characteristic evaluation test of the semiconductor device is performed in the wafer state. In addition, it has been proposed to test a plurality of semiconductor devices at the same time by commonly connecting one test pad to terminals of the plurality of semiconductor devices (see, for example, Patent Document 1).

JP 2002-33360 A

  One semiconductor device may include a plurality of transistors. For example, a two-stage amplifier includes two transistors. In such a case, if test pads are individually provided on the base and collector of each transistor, the area of the test pad occupying the area of the semiconductor device increases, and the chip size increases. In the case of a test in which a voltage is applied between the base and the emitter to apply stress to the transistor, it is not necessary to individually apply a voltage to the base and collector of each transistor.

  Therefore, it is conceivable to connect a base test pad to the bases of a plurality of transistors in common and connect a collector test pad to the collectors of the plurality of transistors in common. However, with such a configuration, the number of test pads can be reduced, but each transistor cannot be individually tested in the wafer state.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor wafer in which the number of test pads can be reduced and each transistor can be individually tested in a wafer state. To get.

The present invention provides a plurality of semiconductor devices arranged in a matrix, a dicing line for separating the plurality of semiconductor devices, a plurality of transistors included in each semiconductor device, and a first terminal of the plurality of transistors. A plurality of first test pads individually connected, a ground electrode commonly connected to a second terminal of the plurality of transistors, a wiring passing through the dicing line, and the plurality of transistors via the wiring A second test pad commonly connected to a control terminal of the semiconductor device, wherein the second test pad is disposed in the semiconductor device, the wiring and the second test pad are connected by an air bridge, and the air A semiconductor wafer characterized in that a notch is provided in a bridge .

  According to the present invention, the number of test pads can be reduced, and each transistor can be individually tested in a wafer state.

1 is a plan view showing a semiconductor wafer according to a first embodiment. It is an enlarged plan view which shows the part enclosed with the broken line of FIG. 1 is an enlarged cross-sectional view showing a semiconductor wafer according to a first embodiment. FIG. 6 is an enlarged plan view showing a semiconductor wafer according to a second embodiment. FIG. 6 is an enlarged plan view showing the vicinity of a base test pad according to a second embodiment. FIG. 10 is an enlarged plan view showing the vicinity of a base test pad according to a modification of the second embodiment. FIG. 6 is an enlarged perspective view showing a semiconductor wafer according to a third embodiment. FIG. 6 is an enlarged plan view showing a semiconductor wafer according to a fourth embodiment. FIG. 10 is an enlarged plan view showing a semiconductor wafer according to a fifth embodiment. FIG. 10 is an enlarged plan view showing a semiconductor wafer according to a sixth embodiment.

  A semiconductor wafer according to an embodiment of the present invention will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view showing a semiconductor wafer according to the first embodiment. FIG. 2 is an enlarged plan view showing a portion surrounded by a broken line in FIG.

  A plurality of semiconductor devices 2 are arranged in a matrix in the semiconductor wafer 1. Adjacent semiconductor devices 2 are isolated by a dicing line 3. The dicing line 3 is used for separating a plurality of semiconductor devices 2 in a later process.

  Each semiconductor device 2 includes a plurality of transistors 4. A plurality of test pads 5 (first test pads) are individually connected to collectors (first terminals) of the plurality of transistors 4. One test pad 7 (second test pad) is commonly connected to the bases (control terminals) of the plurality of transistors 4 via wiring 6. The wiring 6 passes through the dicing line 3. The test pad 7 is disposed on the dicing line 3. Specifically, the test pad 7 is disposed at an intersection where two dicing lines 3 intersect.

  FIG. 3 is an enlarged cross-sectional view showing the semiconductor wafer according to the first embodiment. An epitaxial layer 9 is formed on a non-conductive semiconductor substrate 8. A transistor 4 is formed in the epitaxial layer 9. The emitters (second terminals) of the plurality of transistors 4 are connected in common to the ground electrode 11 on the back surface of the semiconductor substrate 8 via via holes 10 penetrating the semiconductor substrate 8. The ground electrode 11 is made of gold or the like. The emitter of each transistor 4 is grounded via the via hole 10 and the ground electrode 11.

  Next, the semiconductor wafer test will be described. A test probe is brought into contact with the test pad 7, and a plurality of transistors 4 are simultaneously tested by applying a voltage between the base and the emitter to apply stress to the transistors 4. Further, a test probe is brought into contact with any one of the test pads 5 to supply a collector voltage, and each transistor 4 is individually tested.

  After the test, the semiconductor wafer 1 is diced along the dicing line 3 and separated into individual semiconductor devices 2. Since the wiring 6 passing through the dicing line 3 is disconnected by this dicing, the base of each transistor 4 is separated. Therefore, in the individual chip after dicing, the potential generated by the bias circuit can be supplied to the base of each transistor 4. In addition, although the test pad 7 is arrange | positioned on the dicing line 3, since it is not necessarily arrange | positioned continuously, the test pad 7 does not prevent dicing.

  As described above, in the present embodiment, one test pad 7 is commonly connected to the bases of the plurality of transistors 4 of each semiconductor device 2. Thereby, the number of test pads can be reduced. Therefore, the chip size can be reduced. If a test probe is brought into contact with one test pad 7, a test for applying a voltage between the base and the emitter and applying stress to the transistor 4 can be performed simultaneously on the plurality of transistors 4. As a result, the test time can be reduced.

  A plurality of test pads 5 are individually connected to the collectors of the plurality of transistors 4. Thereby, a voltage can be individually supplied from the test probe to the collector of each transistor 4. Therefore, each transistor 4 can be individually tested in the wafer state.

  Further, since the test pad 7 is disposed on the dicing line 3, the chip size can be reduced. Furthermore, since the test pad 7 is regularly arranged at the intersection where the two dicing lines 3 intersect, the test probe can be easily applied to the test pad 7 even if the test probe moves.

Embodiment 2. FIG.
FIG. 4 is an enlarged plan view showing a semiconductor wafer according to the second embodiment. FIG. 5 is an enlarged plan view showing the vicinity of the test pad 7 according to the second embodiment.

  In the second embodiment, the test pad 7 is arranged in the semiconductor device 2 as shown in FIG. In this case, when the wiring 6 in the dicing line 3 and the test pad 7 are connected by a normal wiring, the wiring in the chip is exposed on the side surface of the chip after dicing. As a result, there is a possibility of short-circuiting with GND at the time of die bonding.

  Therefore, in the second embodiment, the wiring 6 and the test pad 7 are connected by the air bridge 12 as shown in FIG. Thereby, the air bridge 12 is scattered during dicing, and wiring in the chip is not exposed on the side surface of the chip after dicing. In addition, since the parasitic capacitance can be reduced, the capacitance of the transistor 4 portion can be accurately measured.

  FIG. 6 is an enlarged plan view showing the vicinity of the test pad 7 according to a modification of the second embodiment. Unlike the configuration of FIG. 5, the air bridge 12 is provided with a notch 13. Thereby, the air bridge 12 can be reliably scattered at the time of dicing.

Embodiment 3 FIG.
FIG. 7 is an enlarged perspective view showing a semiconductor wafer according to the third embodiment. As shown in FIG. 7, the insulating region 14 is formed by selectively injecting or etching the epitaxial layer 9 on the semiconductor substrate 8. Other than the insulating region 14 is a conductive region 15. Instead of the air bridge 12 of the second embodiment, the wiring 6 and the test pad 7 are connected by the conductive region 15 of the epitaxial layer 9. Other configurations are the same as those of the second embodiment. Thus, as in the second embodiment, the wiring in the chip is not exposed on the side surface of the chip after dicing.

  Further, since the vapor deposition wiring is formed relatively thick on the compound semiconductor, if the vapor deposition wiring is formed on the dicing line 3, dicing becomes difficult. In contrast, since the conductive region 15 of the epitaxial layer 9 is not metal, dicing is easy.

Embodiment 4 FIG.
FIG. 8 is an enlarged plan view showing a semiconductor wafer according to the fourth embodiment. The wiring 6 in the dicing line 3 is disposed obliquely with respect to the center line 16 so as to intersect the center line 16 of the dicing line 3.

  If the wiring 6 in the dicing line 3 is arranged in parallel with the dicing line 3, the wiring 6 is not completely separated when the dicing is deviated from the center line 16 of the dicing line 3. For this reason, the base of each transistor 4 remains commonly connected in the chip pieces after dicing.

  In contrast, in the fourth embodiment, the wiring 6 is disposed obliquely with respect to the center line so as to intersect with the center line of the dicing line 3. Thereby, even when the dicing is deviated from the center line 16 of the dicing line 3, the wiring 6 can be reliably cut. Therefore, the base of each transistor 4 can be reliably separated in the chip piece after dicing.

Embodiment 5 FIG.
FIG. 9 is an enlarged plan view showing a semiconductor wafer according to the fifth embodiment. In the fifth embodiment, the test pad 7 is shared by the semiconductor devices 2 adjacent to each other with the dicing line 3 interposed therebetween. Thereby, the test pad 7 can be further reduced.

  When a test probe is brought into contact with one test pad 7, a plurality of transistors 4 included in the adjacent semiconductor device 2 are simultaneously tested by applying a voltage between the base and the emitter to stress the transistors 4. be able to. As a result, the test time can be further reduced. In addition, the same effects as those of the first embodiment can be obtained.

Embodiment 6 FIG.
FIG. 10 is an enlarged plan view showing a semiconductor wafer according to the sixth embodiment. In the sixth embodiment, the test pad 7 is shared by a certain region on the wafer or all the semiconductor devices 2. Thereby, the number of test pads 7 can be further reduced as compared with the fifth embodiment.

  When a test probe is brought into contact with one test pad 7, a voltage is applied between the base and emitter of a plurality of transistors 4 included in a certain region or all of the semiconductor devices 2 on the wafer to stress the transistors 4. Can be tested simultaneously. As a result, the test time can be further reduced. In addition, the same effects as those of the first embodiment can be obtained.

  In the first to sixth embodiments, a bipolar transistor has been described as an example of the transistor 4. The present invention is not limited to this, and an FET (Field Effect Transistor) may be used as the transistor 4.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor device 3 Dicing line 4 Transistor 5 Test pad (1st test pad)
6 Wiring 7 Test pad (second test pad)
9 Epitaxial layer 11 Ground electrode 12 Air bridge 13 Notch 15 Conductive region 16 Center line

Claims (6)

A plurality of semiconductor devices arranged in a matrix;
A dicing line for separating the plurality of semiconductor devices;
A plurality of transistors included in each semiconductor device;
A plurality of first test pads individually connected to first terminals of the plurality of transistors;
A ground electrode commonly connected to second terminals of the plurality of transistors;
Wiring passing through the dicing line;
A second test pad commonly connected to the control terminals of the plurality of transistors via the wiring ,
The second test pad is disposed in the semiconductor device,
The wiring and the second test pad are connected by an air bridge,
A semiconductor wafer, wherein the air bridge is provided with a notch .   A plurality of semiconductor devices arranged in a matrix;
  A dicing line for separating the plurality of semiconductor devices;
  A plurality of transistors included in each semiconductor device;
  A plurality of first test pads individually connected to first terminals of the plurality of transistors;
  A ground electrode commonly connected to second terminals of the plurality of transistors;
  Wiring passing through the dicing line;
  A second test pad commonly connected to the control terminals of the plurality of transistors via the wiring,
  The semiconductor wafer according to claim 1, wherein the wiring is disposed obliquely with respect to the center line so as to intersect the center line of the dicing line. The semiconductor wafer according to claim 2 , wherein the second test pad is disposed on the dicing line. The semiconductor wafer according to claim 3 , wherein the second test pad is arranged at an intersection where the two dicing lines intersect. The second test pad is disposed in the semiconductor device,
The semiconductor wafer according to claim 2 , wherein the wiring and the second test pad are connected by a conductive region of an epitaxial layer. 6. The semiconductor wafer according to claim 1 , wherein the second test pad is shared by a part or all of the plurality of semiconductor devices.

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