JP2013187402A - Semiconductor wafer and inspection method of the same - Google Patents

Semiconductor wafer and inspection method of the same Download PDF

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JP2013187402A
JP2013187402A JP2012051884A JP2012051884A JP2013187402A JP 2013187402 A JP2013187402 A JP 2013187402A JP 2012051884 A JP2012051884 A JP 2012051884A JP 2012051884 A JP2012051884 A JP 2012051884A JP 2013187402 A JP2013187402 A JP 2013187402A
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semiconductor wafer
semiconductor
terminals
pad
dicing line
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Jun Takaai
純 高相
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to US13/602,784 priority patent/US8896339B2/en
Publication of JP2013187402A publication Critical patent/JP2013187402A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor wafer and an inspection method of the same, which can reduce a wafer measurement time without making a dicing line thick.SOLUTION: A semiconductor wafer comprises a plurality of semiconductor chips 3 divided by dicing lines 2. Each semiconductor chip 3 includes a plurality of terminals 4a, 4b, 4c having the same potential. The plurality of terminals 4a, 4b, 4c are connected by interconnection lines 5 through the dicing lines 2. The semiconductor wafer composes a pad 6a connected to the terminal 4a. The pad 6a is provided on the semiconductor chip 3 and does not exist on the dicing lines 2.

Description

本発明は、ダイシングラインによって分割された複数の半導体チップを備える半導体ウェハ及びその検査方法に関する。   The present invention relates to a semiconductor wafer including a plurality of semiconductor chips divided by dicing lines and an inspection method thereof.

複数の半導体チップの１つに含まれる複数の端子をダイシングライン上の配線で接続し、テスト用パッドをダイシングライン上に設けた半導体ウェハが提案されている（例えば、特許文献１参照）。この場合には、１つのテスト用パッドにプローブを接触させて複数の端子に同一電位を同時に印加することができる。これにより同時測定が可能となり、ウェハ測定時間を短縮することができる。   There has been proposed a semiconductor wafer in which a plurality of terminals included in one of a plurality of semiconductor chips are connected by wiring on a dicing line, and a test pad is provided on the dicing line (see, for example, Patent Document 1). In this case, the probe can be brought into contact with one test pad and the same potential can be simultaneously applied to a plurality of terminals. This enables simultaneous measurement and shortens the wafer measurement time.

特開平３−２１４６３８号公報JP-A-3-214638

しかし、従来の半導体ウェハでは、ダイシングライン上にテスト用パッドを設けるため、ダイシングラインを太くしなければならなかった。   However, in the conventional semiconductor wafer, since the test pad is provided on the dicing line, the dicing line has to be thickened.

本発明は、上述のような課題を解決するためになされたもので、その目的はダイシングラインを太くすることなく、ウェハ測定時間を短縮することができる半導体ウェハ及びその検査方法を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor wafer and an inspection method thereof that can shorten the wafer measurement time without increasing the dicing line. .

本発明に係る半導体ウェハは、ダイシングラインによって分割された複数の半導体チップと、前記複数の半導体チップの１つに含まれる同一電位の複数の端子を前記ダイシングラインを通って接続する配線と、前記複数の端子に接続されたパッドとを備え、前記パッドは、前記半導体チップ上に設けられ、ダイシングライン上には存在しないことを特徴とする。   A semiconductor wafer according to the present invention includes a plurality of semiconductor chips divided by a dicing line, a wiring connecting a plurality of terminals of the same potential included in one of the plurality of semiconductor chips through the dicing line, A pad connected to a plurality of terminals, wherein the pad is provided on the semiconductor chip and does not exist on the dicing line.

本発明により、ダイシングラインを太くすることなく、ウェハ測定時間を短縮することができる。   According to the present invention, it is possible to shorten the wafer measurement time without increasing the thickness of the dicing line.

本発明の実施の形態に係る半導体ウェハを示す上面図である。It is a top view which shows the semiconductor wafer which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体ウェハを示す拡大上面図である。It is an enlarged top view which shows the semiconductor wafer which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体ウェハの変形例を示す拡大上面図である。It is an enlarged top view which shows the modification of the semiconductor wafer which concerns on embodiment of this invention.

図１は、本発明の実施の形態に係る半導体ウェハを示す上面図である。半導体ウェハ１上において、ダイシングライン２によって複数の半導体チップ３が分割されている。   FIG. 1 is a top view showing a semiconductor wafer according to an embodiment of the present invention. On the semiconductor wafer 1, a plurality of semiconductor chips 3 are divided by dicing lines 2.

図２は、本発明の実施の形態に係る半導体ウェハを示す拡大上面図である。半導体チップ３は同一電位の複数の端子４ａ，４ｂ，４ｃを含む。配線５がダイシングライン２を通って複数の端子４ａ，４ｂ，４ｃを互いに接続している。パッド６ａ，６ｂ，６ｃがそれぞれ端子４ａ，４ｂ，４ｃに接続されている。パッド６ａ，６ｂ，６ｃは、半導体チップ３上に設けられ、ダイシングライン２上には存在しない。   FIG. 2 is an enlarged top view showing the semiconductor wafer according to the embodiment of the present invention. The semiconductor chip 3 includes a plurality of terminals 4a, 4b, 4c having the same potential. A wiring 5 connects the plurality of terminals 4a, 4b, 4c to each other through the dicing line 2. Pads 6a, 6b and 6c are connected to terminals 4a, 4b and 4c, respectively. The pads 6a, 6b and 6c are provided on the semiconductor chip 3 and do not exist on the dicing line 2.

続いて、上記の半導体ウェハを検査する方法を説明する。１つのパッド６ａにプローブ７を接触させて複数の端子４ａ，４ｂ，４ｃに同一電位を配線５を介して同時に印加して半導体チップ３の検査を行なう。これにより複数の端子４ａ，４ｂ，４ｃの同時測定が可能となり、ウェハ測定時間を短縮することができる（本実施の形態では測定回数を３回から１回に短縮できる）。   Next, a method for inspecting the semiconductor wafer will be described. The probe 7 is brought into contact with one pad 6a, and the same potential is simultaneously applied to the plurality of terminals 4a, 4b, 4c through the wiring 5, and the semiconductor chip 3 is inspected. This enables simultaneous measurement of a plurality of terminals 4a, 4b, and 4c and shortens the wafer measurement time (in this embodiment, the number of measurements can be reduced from 3 to 1).

また、パッド６ａ，６ｂ，６ｃは、半導体チップ３上に設けられ、ダイシングライン２上には存在しない。このため、ダイシングライン２を太くする必要が無い。そして、配線５はウェハテスト後のダイシングにより除去されるため、配線５が半導体チップ３に影響を与えることはない。また、単一チップでレイアウトがクローズされているため、複数の半導体チップ３の全体のレイアウトを変更する必要は無い。   The pads 6a, 6b, 6c are provided on the semiconductor chip 3 and do not exist on the dicing line 2. For this reason, it is not necessary to make the dicing line 2 thick. Since the wiring 5 is removed by dicing after the wafer test, the wiring 5 does not affect the semiconductor chip 3. Further, since the layout is closed by a single chip, it is not necessary to change the entire layout of the plurality of semiconductor chips 3.

図３は、本発明の実施の形態に係る半導体ウェハの変形例を示す拡大上面図である。端子４ｂ，４ｃは配線５を介してパッド６ａに接続されているため、変形例ではパッド６ｂ，６ｃを省略している。これにより、パッド６ｂ，６ｃのレイアウトが不要となり、レイアウト面積を縮小でき、コストを低減できる。また、ウェハテスト時に用いられるパッド６ｂ，６ｃ用の２本のプローブを削減できるため、プローブカードのコストも低減できる。   FIG. 3 is an enlarged top view showing a modification of the semiconductor wafer according to the embodiment of the present invention. Since the terminals 4b and 4c are connected to the pad 6a via the wiring 5, the pads 6b and 6c are omitted in the modification. Thereby, the layout of the pads 6b and 6c becomes unnecessary, the layout area can be reduced, and the cost can be reduced. In addition, since the two probes for the pads 6b and 6c used during the wafer test can be reduced, the cost of the probe card can be reduced.

１ 半導体ウェハ
２ ダイシングライン
３ 半導体チップ
４ａ，４ｂ，４ｃ 端子
５ 配線
６ａ，６ｂ，６ｃ パッド
７ プローブ DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Dicing line 3 Semiconductor chip 4a, 4b, 4c Terminal 5 Wiring 6a, 6b, 6c Pad 7 Probe

Claims (2)

ダイシングラインによって分割された複数の半導体チップと、
前記複数の半導体チップの１つに含まれる同一電位の複数の端子を前記ダイシングラインを通って接続する配線と、
前記複数の端子に接続されたパッドとを備え、
前記パッドは、前記半導体チップ上に設けられ、ダイシングライン上には存在しないことを特徴とする半導体ウェハ。 A plurality of semiconductor chips divided by dicing lines;
Wiring connecting a plurality of terminals of the same potential included in one of the plurality of semiconductor chips through the dicing line;
A pad connected to the plurality of terminals,
The semiconductor wafer according to claim 1, wherein the pad is provided on the semiconductor chip and does not exist on a dicing line. 請求項１に記載の半導体ウェハを検査する方法であって、
前記パッドにプローブを接触させて前記複数の端子に同一電位を同時に印加して前記半導体チップの検査を行なうことを特徴とする半導体ウェハの検査方法。 A method for inspecting a semiconductor wafer according to claim 1, comprising:
A method of inspecting a semiconductor wafer, wherein a probe is brought into contact with the pad and the same potential is simultaneously applied to the plurality of terminals to inspect the semiconductor chip.
JP2012051884A 2012-03-08 2012-03-08 Semiconductor wafer and inspection method of the same Pending JP2013187402A (en)

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JP2012051884A JP2013187402A (en) 2012-03-08 2012-03-08 Semiconductor wafer and inspection method of the same
US13/602,784 US8896339B2 (en) 2012-03-08 2012-09-04 Method for testing semiconductor wafer

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JP2012051884A JP2013187402A (en) 2012-03-08 2012-03-08 Semiconductor wafer and inspection method of the same

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CN108831841A (en) * 2018-06-14 2018-11-16 上海华力集成电路制造有限公司 The wafer of aluminum steel resistance permits Acceptance Tests figure

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JP2000286315A (en) * 1999-03-29 2000-10-13 Sanyo Electric Co Ltd Pad arrangement method for semiconductor chip
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