JPH04342151A - Evaluation of semiconductor wafer - Google Patents

Abstract

PURPOSE:To improve operativity of measurement by connecting a plurality of source electrodes and a plurality of gate electrodes, respectively. CONSTITUTION:A measurement wafer 6 is mounted on a stage 11 which is movable to a drain electrode measuring needle 14. Measurement terminals 12, 13 fixed to the stage 11 are brought into contact with gate voltage applicating electrode 8 and a source voltage application electrode 10 provided to a periphery of the wafer 6, and a drain electrode measuring needle 14 is brought into contact with a drain electrode of a field effect transistor(FET) to measure FET characteristics (threshold value voltage, etc.) of the drain electrode measuring needle 14. In this case, it is desirable to use a material of good conductivity such as gold for a wiring conductor between gate electrodes and between source electrodes to lower a resistance of a wiring. Thereby, operativity of measurement can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating semiconductor wafers, particularly compound semiconductor wafers.

0002

2. Description of the Related Art Conventionally, when an active layer is formed on the surface of a semiconductor wafer and the uniformity of this active layer is evaluated, FIG.
As shown in FIG.
A plurality of layers) 4 and active layers (n+ layers) 5) are prepared, and a total of 3 layers are formed on each of the source electrode 1, drain electrode 2, and gate electrode 3.
Apply the measurement needle of a book to the FE such as threshold voltage (Vth).
The characteristics of T were being measured. After the measurement of one FET is completed, the wafer or three measurement needles are moved to measure the next FET.

By repeating this operation and measurement, variations in the characteristics of FETs fabricated on a semiconductor wafer are evaluated.

However, the conventional measurement method requires three movable measurement needles with respect to the wafer, and has the disadvantage that measurement cannot be performed unless any one of them is in contact with the wafer.

[0005]

OBJECTS OF THE INVENTION It is an object of the present invention to provide an advantageous evaluation method that overcomes the drawbacks of the prior art described above and can easily measure the characteristics of semiconductor wafers.

[0006]

[Summary of the Invention] The gist of the present invention is to
The method of manufacturing the evaluation element consists in connecting a plurality of source electrodes and a plurality of gate electrodes, respectively, thereby greatly improving the workability of measurement.

[0007]

[Embodiment] FIG. 3 is a structural diagram showing an embodiment of the present invention, in which gate electrodes 2 of a plurality of FETs in the conventional example shown in FIG.
A conductor 7 was used to wire between the measurement electrodes 8 for applying voltage between the FETs and the gates, and a conductor 9 was used for wiring between the source electrodes 1 of the plurality of FETs and measurement electrodes 10 for applying voltage to the sources. It is a structure.

The measurement method in this case is as shown in FIG.
A wafer 6 to be measured is placed on top of the wafer 1 .

Next, the measurement terminals 12 and 13 fixed to the stage are brought into contact with the gate voltage application electrode 8 and the source voltage application electrode 10 provided around the wafer, and the measurement needle for the drain electrode is connected to the drain of the FET. In contact with the electrode, F
Measure ET characteristics (threshold voltage, etc.).

FIG. 2 shows a modification of the present invention, which has a structure in which the source electrodes are all n+ layers and electrodes, and has the advantage that the wiring resistance between the electrodes can be significantly reduced. .

In this embodiment, it is desirable to use a material with excellent conductivity, such as gold (Au), as the wiring conductor between the gate electrodes and between the source electrodes, and to lower the resistance of the wiring.

The sheet carrier concentration of the n+ layer is equal to or higher than that of the n layer.

[0013]

Effects of the Invention As explained above, according to the present invention, only one movable measuring needle is required for the wafer, compared to the conventional measuring needle 3.
Compared to books, the frequency and replacement cost of needles can be reduced to 1/3.

[0014] ■ Poor contact between the needle and the electrode can be significantly reduced.

It has the following effects and has great industrial value.

[Brief explanation of drawings]

FIG. 1 is a structural diagram showing an example of an evaluation FET of the present invention, in which (A) is a top view and (B) is a cross-sectional view.

FIG. 2 is a structural diagram showing a modified example of the present invention, in which (A) is a top view and (B) is a cross-sectional view.

FIG. 3 shows a circuit diagram of the invention.

FIG. 4 shows the measuring method of the present invention, in which (A) is a top view and (B) is a front view.

FIG. 5 is a structural diagram showing an example of manufacturing a conventional evaluation FET, in which (A) is a top view and (B) is a cross-sectional view.

FIG. 6 is a structural diagram showing an example of manufacturing a conventional evaluation FET, in which (A) is a top view and (B) is a cross-sectional view.

[Explanation of symbols]

1 Source electrode 2 Gate electrode 3 Drain electrode 4 Active layer (n layer) 5 Active layer (n+ layer) 6 Semiconductor wafer 7 Wiring between gate electrodes 8 Gate voltage application electrode 9 Wiring between source electrodes 10 Source voltage application electrode 11 Movable stage for wafer fixation 12 Gate voltage application electrode 13 Source voltage application electrode 14 Measuring needle for drain voltage application

Claims (1)

[Claims] Claim 1: After ion implantation into the wafer surface, an active layer is formed by an annealing treatment or an epitaxial method, and when the uniformity of this active layer is evaluated using a field effect transistor (FET), a layer surrounding the drain electrode is used. A gate electrode is provided outside the drain electrode, and a source electrode is further provided to surround this gate electrode, and each source electrode and each gate electrode are connected with metal to serve as a common fixed electrode, and the drain electrode is sequentially connected to the drain electrode. A semiconductor wafer evaluation method characterized by performing measurement between electrodes brought into moving contact.