JP2014072468A - Wiring board - Google Patents

Wiring board Download PDF

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JP2014072468A
JP2014072468A JP2012218940A JP2012218940A JP2014072468A JP 2014072468 A JP2014072468 A JP 2014072468A JP 2012218940 A JP2012218940 A JP 2012218940A JP 2012218940 A JP2012218940 A JP 2012218940A JP 2014072468 A JP2014072468 A JP 2014072468A
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semiconductor element
wiring conductor
element connection
tin plating
plating layer
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Japanese (ja)
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Seiichi Takami
征一 高見
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Priority to JP2012218940A priority Critical patent/JP2014072468A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which prevents short circuits from being caused by melting objects of a solder bump and tin plating between adjacent semiconductor element connection pads and achieves excellent electric insulation reliability.SOLUTION: A wiring board 10 includes: an insulation substrate 1; a wiring conductor 3 which is formed on an upper surface of the insulation substrate 1 and is made of copper; a solder resist layer 6 which is deposited on the insulation substrate 1 and the wiring conductor 3 and has an opening 6a exposing a part of the wiring conductor 3 as a semiconductor element connection pad 4; and a tin plating layer 7 deposited on a surface of the wiring conductor 3 which is exposed in the opening 6a. The tin plating layer 7 is deposited only on an upper surface of the wiring conductor 3.

Description

本発明は、半導体素子を搭載するために用いられる配線基板に関するものである。   The present invention relates to a wiring board used for mounting a semiconductor element.

従来、図４に示すように、下面外周部に電極端子Ｔがペリフェラル配置された半導体素子Ｓをフリップチップ接続により搭載する配線基板２０として、多数のスルーホール１２を有する樹脂系絶縁材料から成る絶縁基板１１の上面の中央部に半導体素子Ｓを搭載するための搭載部１１ａを設けるとともに、絶縁基板１１の上面からスルーホール１２内を介して下面に導出する銅から成る複数の配線導体１３を被着させ、この配線導体１３の一部を搭載部１１ａの外周部において半導体素子Ｓの電極端子Ｔに接続するための半導体素子接続パッド１４として配置するとともに絶縁基板１１の下面において外部電気回路基板と接続するための外部接続パッド１５として配置し、さらに絶縁基板１１の上下面およびスルーホール１２内に半導体素子接続パッド１４および外部接続パッド１５を露出させる開口部１６ａおよび１６ｂを有する樹脂系絶縁材料から成るソルダーレジスト層１６を被着させてなる配線基板２０が知られている。なお、半導体素子Ｓの電極端子Ｔの下端には半導体素子接続パッド１４と接続するための鉛フリー半田から成る半田バンプＢが被着されており、半導体素子接続パッド１４の露出する表面には半田バンプＢとの濡れ性を向上させるための錫めっき層１７が被着されている。   Conventionally, as shown in FIG. 4, as a wiring board 20 on which a semiconductor element S having peripherally disposed electrode terminals T on the outer periphery of a lower surface is mounted by flip chip connection, an insulating material made of a resin-based insulating material having a large number of through holes 12 is used. A mounting portion 11 a for mounting the semiconductor element S is provided at the center of the upper surface of the substrate 11, and a plurality of wiring conductors 13 made of copper led out from the upper surface of the insulating substrate 11 to the lower surface through the through holes 12 are covered. A part of the wiring conductor 13 is disposed as a semiconductor element connection pad 14 for connecting to the electrode terminal T of the semiconductor element S on the outer peripheral portion of the mounting portion 11a, and is connected to the external electric circuit board on the lower surface of the insulating substrate 11. The semiconductor element is arranged as an external connection pad 15 for connection, and further in the upper and lower surfaces of the insulating substrate 11 and in the through hole 12 Continued pads 14 and external connection wiring board 20 formed by depositing the solder resist layer 16 made of a resin-based insulating material having openings 16a and 16b to expose the pad 15 is known. A solder bump B made of lead-free solder for connecting to the semiconductor element connection pad 14 is applied to the lower end of the electrode terminal T of the semiconductor element S, and the exposed surface of the semiconductor element connection pad 14 is soldered. A tin plating layer 17 for improving wettability with the bump B is applied.

このような配線基板２０においては、図５（ａ）に示すように、半導体素子接続パッド１４上に半導体素子Ｓの電極端子Ｔを載置し、その状態で図５（ｂ）に示すように、半田バンプＢを加熱溶融することによって半導体素子Ｓが配線基板２０上に実装される。   In such a wiring board 20, as shown in FIG. 5A, the electrode terminal T of the semiconductor element S is placed on the semiconductor element connection pad 14, and in this state, as shown in FIG. 5B. The semiconductor element S is mounted on the wiring board 20 by heating and melting the solder bumps B.

しかしながら、この従来の配線基板２０においては、半導体素子接続パッド１４の側面にも錫めっき層１７が被着されているため、半導体素子Ｓの電極端子Ｔを半導体素子接続パッド１４上に載置して半田バンプＢを加熱溶融させた際に、この錫めっき１７が半田バンプＢとともに溶融し、その溶融物が半導体素子接続パッド１４の側面にも回り込んでしまう。その結果、例えば隣接する半導体素子接続パッド１４同士の間隔が２０μｍ以下の狭いものである場合、隣接する半導体素子接続パッド１４の間で半田バンプＢと錫めっき１７との溶融物同士が接触して電気的な短絡を起こしてしまいやすいという問題が発生する。   However, in this conventional wiring substrate 20, since the tin plating layer 17 is also deposited on the side surface of the semiconductor element connection pad 14, the electrode terminal T of the semiconductor element S is placed on the semiconductor element connection pad 14. When the solder bumps B are heated and melted, the tin plating 17 is melted together with the solder bumps B, and the melted material also wraps around the side surfaces of the semiconductor element connection pads 14. As a result, for example, when the distance between adjacent semiconductor element connection pads 14 is a narrow one of 20 μm or less, the melted solder bump B and tin plating 17 are in contact with each other between adjacent semiconductor element connection pads 14. There arises a problem that an electrical short circuit is likely to occur.

特開２００２−２８９６５２号公報Japanese Patent Laid-Open No. 2002-289652 特開２００５−５７２２３号公報JP 2005-57223 A

本発明は、隣接する半導体素子接続パッド同士の間隔が２０μｍ以下の狭いものであったとしても、隣接する半導体素子接続パッド同士の間で半田バンプと錫めっきとの溶融物による短絡が発生することがなく、電気的な絶縁信頼性に優れる配線基板を提供することを目的とする。   In the present invention, even if the distance between adjacent semiconductor element connection pads is as narrow as 20 μm or less, a short circuit occurs between adjacent semiconductor element connection pads due to a melt of solder bumps and tin plating. It is an object of the present invention to provide a wiring board that is excellent in electrical insulation reliability.

本発明の配線基板は、絶縁基板と、該絶縁基板の上面に形成された銅から成る配線導体と、前記絶縁基板および前記配線導体上に被着されており、前記配線導体の一部を半導体素子接続パッドとして露出させる開口部を有するソルダーレジスト層と、前記開口部内に露出する前記配線導体の表面に被着された錫めっき層とを備えた配線基板であって、前記錫めっき層は、前記配線導体の上面のみに被着されていることを特徴とするものである。   A wiring board according to the present invention includes an insulating substrate, a wiring conductor made of copper formed on an upper surface of the insulating substrate, and is deposited on the insulating substrate and the wiring conductor. A part of the wiring conductor is a semiconductor. A wiring board comprising a solder resist layer having an opening exposed as an element connection pad, and a tin plating layer deposited on the surface of the wiring conductor exposed in the opening, wherein the tin plating layer is The wiring conductor is attached only to the upper surface of the wiring conductor.

本発明の配線基板によれば、ソルダーレジスト層の開口部内に露出した配線導体の上面のみに錫めっき層が被着されていることから、この開口部内に露出した配線導体の一部である半導体素子接続パッド上に半導体素子の電極を半田バンプを介して接続する際に半田バンプと錫めっき層との溶融物は半導体素子接続パッドの上面のみに形成され、半導体素子接続パッドの側面に回りこむことはない。したがって、隣接する半導体素子接続パッド同士の間隔が２０μｍ以下の狭いものであったとしても、隣接する半導体素子接続パッド同士の間で半田バンプと錫めっきとの溶融物による短絡が発生することがなく、電気的な絶縁信頼性に優れる配線基板を提供することができる。   According to the wiring board of the present invention, since the tin plating layer is deposited only on the upper surface of the wiring conductor exposed in the opening of the solder resist layer, the semiconductor which is a part of the wiring conductor exposed in the opening When the electrodes of the semiconductor element are connected to the element connection pads via the solder bumps, the melt of the solder bumps and the tin plating layer is formed only on the upper surface of the semiconductor element connection pads and wraps around the side surfaces of the semiconductor element connection pads. There is nothing. Therefore, even if the distance between adjacent semiconductor element connection pads is 20 μm or less, a short circuit due to a melt of solder bumps and tin plating does not occur between adjacent semiconductor element connection pads. In addition, it is possible to provide a wiring board having excellent electrical insulation reliability.

図１は、本発明の配線基板における実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の要部拡大概略断面図である。2 is an enlarged schematic cross-sectional view of a main part of the wiring board shown in FIG. （ａ）〜（ｈ）は、図１に示す配線基板を製造する方法を説明するための工程毎の概略断面図である。(A)-(h) is a schematic sectional drawing for every process for demonstrating the method to manufacture the wiring board shown in FIG. 図４は、従来の配線基板を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing a conventional wiring board. 図５は、図４に示す配線基板の要部拡大概略断面図である。FIG. 5 is an enlarged schematic cross-sectional view of a main part of the wiring board shown in FIG.

次に、本発明の配線基板について図１〜図３を基にして説明する。図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。図１に示すように、本例の配線基板１０は、主として絶縁基板１と配線導体３とソルダーレジスト層６とから構成されており、その上面中央部に半導体素子Ｓを搭載するための搭載部１ａを有している。絶縁基板１は、例えばガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた厚みが３０〜２００μｍ程度の単層または多層の絶縁層を熱硬化させた樹脂系電気絶縁材料から成り、その上面から下面にかけては直径が５０〜３００μｍ程度のスルーホール２が形成されている。   Next, the wiring board of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. As shown in FIG. 1, the wiring substrate 10 of this example is mainly composed of an insulating substrate 1, a wiring conductor 3, and a solder resist layer 6, and a mounting portion for mounting a semiconductor element S on the center of the upper surface thereof. 1a. The insulating substrate 1 is, for example, a resin-based electric material obtained by thermosetting a single-layer or multilayer insulating layer having a thickness of about 30 to 200 μm in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. A through hole 2 made of an insulating material and having a diameter of about 50 to 300 μm is formed from the upper surface to the lower surface.

絶縁基板１の内部および上下面およびスルーホール２の内壁には、厚みが１０〜２０μｍ程度の銅箔や銅めっき層等の銅から成る配線導体３が被着形成されている。これらの配線導体３のうち絶縁基板１の内部および上下面の所定のもの同士がスルーホール２を介して互いに電気的に接続されている。また、絶縁基板１の上面における配線導体３の一部は、半導体素子Ｓの電極端子Ｔが接続される半導体素子接続パッド４を形成しており、絶縁基板１の下面における配線導体３の一部は外部電気回路基板に接続するための外部接続パッド５を形成している。そして、半導体素子接続パッド４には、半導体素子Ｓの電極端子Ｔが半田を介して接続され、外部接続パッド５は外部電気回路の配線導体に半田ボールを介して接続される。なお、半導体素子Ｓの電極端子Ｔには半導体素子接続パッド４と接続するための鉛フリー半田から成る半田バンプＢが被着されており、半導体素子接続パッド４の上面には半田バンプＢとの濡れ性を向上させるための錫めっき層７が被着されている。   A wiring conductor 3 made of copper such as a copper foil or a copper plating layer having a thickness of about 10 to 20 μm is deposited on the inside and upper and lower surfaces of the insulating substrate 1 and the inner wall of the through hole 2. Among these wiring conductors 3, predetermined ones on the inside and upper and lower surfaces of the insulating substrate 1 are electrically connected to each other through the through holes 2. Further, a part of the wiring conductor 3 on the upper surface of the insulating substrate 1 forms a semiconductor element connection pad 4 to which the electrode terminal T of the semiconductor element S is connected, and a part of the wiring conductor 3 on the lower surface of the insulating substrate 1. Form external connection pads 5 for connection to an external electric circuit board. The electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 4 via solder, and the external connection pad 5 is connected to the wiring conductor of the external electric circuit via solder balls. A solder bump B made of lead-free solder for connecting to the semiconductor element connection pad 4 is attached to the electrode terminal T of the semiconductor element S. The upper surface of the semiconductor element connection pad 4 is connected to the solder bump B. A tin plating layer 7 for improving wettability is applied.

さらに、絶縁基板１の上下面およびスルーホール２の内部には、配線導体３を覆うようにしてソルダーレジスト層６が被着されている。ソルダーレジスト層６は、例えばアクリル変性エポキシ樹脂等の感光性熱硬化性樹脂から成り、絶縁基板１の上下面での厚みが１０〜３０μｍ程であり、スルーホール２の内部を充填している。そして上面側のソルダーレジスト層６には、半導体素子接続パッド４を露出させる開口部６ａが形成されているとともに、下面側のソルダーレジスト層６には外部接続パッド５を露出させる開口部６ｂが形成されている。   Further, a solder resist layer 6 is deposited on the upper and lower surfaces of the insulating substrate 1 and inside the through hole 2 so as to cover the wiring conductor 3. The solder resist layer 6 is made of, for example, a photosensitive thermosetting resin such as an acrylic-modified epoxy resin, has a thickness on the upper and lower surfaces of the insulating substrate 1 of about 10 to 30 μm, and fills the inside of the through hole 2. An opening 6a for exposing the semiconductor element connection pad 4 is formed in the solder resist layer 6 on the upper surface side, and an opening 6b for exposing the external connection pad 5 is formed in the solder resist layer 6 on the lower surface side. Has been.

そして、本例の配線基板１０においては、図２（ａ）に示すように、半導体素子接続パッド４上に半導体素子Ｓの電極端子Ｔを載置し、その状態で図２（ｂ）に示すように、半田バンプＢを加熱溶融することによって半導体素子Ｓが配線基板１０上に実装される。このとき、半導体素子接続パッド４の露出する上面に被着させた錫めっき層７も半田バンプＢとともに溶融して電極端子Ｔと半導体素子接続パッド４とを接続するための半田Ｂ＋７となる。   In the wiring board 10 of this example, as shown in FIG. 2A, the electrode terminal T of the semiconductor element S is placed on the semiconductor element connection pad 4, and the state shown in FIG. Thus, the semiconductor element S is mounted on the wiring board 10 by heating and melting the solder bumps B. At this time, the tin plating layer 7 deposited on the exposed upper surface of the semiconductor element connection pad 4 is also melted together with the solder bump B to become solder B + 7 for connecting the electrode terminal T and the semiconductor element connection pad 4.

ところで、本例の配線基板においては、ソルダーレジスト層６の開口部６ａ内に露出する配線導体３の上面のみに錫めっき層７が被着されていることが重要である。このように、ソルダーレジスト層６の開口部６ａ内に露出した配線導体３の上面のみに錫めっき層７が被着されていることから、この開口部６ａ内に露出した配線導体３の一部である半導体素子接続パッド４上に半導体素子Ｓの電極Ｔを半田バンプＢを介して接続する際に半田バンプＢと錫めっき層７との溶融物は半導体素子接続パッド４の上面のみに形成され、半導体素子接続パッド４の側面に回りこむことはない。したがって、隣接する半導体素子接続パッド４同士の間隔が２０μｍ以下の狭いものであったとしても、隣接する半導体素子接続パッド４同士の間で半田バンプＢと錫めっき層７との溶融物による短絡が発生することがなく、電気的な絶縁信頼性に優れる配線基板１０を提供することができる。   By the way, in the wiring board of this example, it is important that the tin plating layer 7 is deposited only on the upper surface of the wiring conductor 3 exposed in the opening 6 a of the solder resist layer 6. Thus, since the tin plating layer 7 is deposited only on the upper surface of the wiring conductor 3 exposed in the opening 6a of the solder resist layer 6, a part of the wiring conductor 3 exposed in this opening 6a. When the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4 via the solder bump B, the melt of the solder bump B and the tin plating layer 7 is formed only on the upper surface of the semiconductor element connection pad 4. The semiconductor element connection pad 4 does not wrap around the side surface. Therefore, even if the distance between adjacent semiconductor element connection pads 4 is as narrow as 20 μm or less, a short circuit due to the melt of solder bump B and tin plating layer 7 is caused between adjacent semiconductor element connection pads 4. It is possible to provide a wiring substrate 10 that does not occur and has excellent electrical insulation reliability.

次に、上述した配線基板１０の製造方法の一例を説明する。先ず、図３（ａ）に示すように、絶縁基板１の上面に下地金属層３ａを被着させる。下地金属層３ａは例えば厚みが０．１〜２μｍ程度の無電解銅めっき層や厚みが１〜５μｍ程度の銅箔から成る。下地金属層３ａが無電解銅めっき層から成る場合であれば、周知の無電解銅めっき法により被着させればよく、下地金属層３ａが銅箔から成る場合であれば、プライマー樹脂と呼ばれる接着剤を介して銅箔を貼り付けることにより被着させればよい。   Next, an example of a method for manufacturing the wiring board 10 described above will be described. First, as shown in FIG. 3A, a base metal layer 3a is deposited on the upper surface of the insulating substrate 1. The base metal layer 3a is made of, for example, an electroless copper plating layer having a thickness of about 0.1 to 2 μm or a copper foil having a thickness of about 1 to 5 μm. If the base metal layer 3a is made of an electroless copper plating layer, it may be deposited by a known electroless copper plating method. If the base metal layer 3a is made of a copper foil, it is called a primer resin. What is necessary is just to make it adhere by sticking copper foil through an adhesive agent.

次に、図３（ｂ）に示すように、下地金属層３ａの上面に第１のめっきレジスト層２１を被着する。第１のめっきレジスト層２１には半導体素子接続パッド４となる部位を一部に含む配線導体３に対応するパターンの開口部２１ａが形成されている。このようなめっきレジスト層２１は、感光性を有するドライフィルムレジストを下地金属層３ａ上に貼着するとともに周知のフォトリソグラフィー技術を採用して所定のパターンに露光および現像した後、熱硬化させることにより形成される。   Next, as shown in FIG. 3B, a first plating resist layer 21 is deposited on the upper surface of the base metal layer 3a. In the first plating resist layer 21, an opening 21 a having a pattern corresponding to the wiring conductor 3 partially including a portion to be the semiconductor element connection pad 4 is formed. Such a plating resist layer 21 is formed by sticking a photosensitive dry film resist on the underlying metal layer 3a, and using a well-known photolithography technique to expose and develop a predetermined pattern, and then thermally cure. It is formed by.

次に、図３（ｃ）に示すように、開口部２１ａ内に露出する下地金属層３ａ上に電解銅めっき層３ｂを被着する。電解銅めっき層３ｂの厚みは、例えば１０〜２０μｍ程度である。このような電解銅めっき層３ｂは周知の電解銅めっき法により被着される。   Next, as shown in FIG.3 (c), the electrolytic copper plating layer 3b is adhere | attached on the base metal layer 3a exposed in the opening part 21a. The thickness of the electrolytic copper plating layer 3b is, for example, about 10 to 20 μm. Such an electrolytic copper plating layer 3b is applied by a known electrolytic copper plating method.

次に、図３（ｄ）に示すように、第１のめっきレジスト層２１および電解銅めっき層３ｂ上に、第２のめっきレジスト層２２を被着する。第２のめっきレジスト層２２は、配線導体３のうち半導体素子接続パッド４となる部位のみを露出させるように第１のめっきレジスト層２１および電解銅めっき層３ｂを覆っている。このような第２のめっきレジスト層２２は上述した第１のめっきレジスト層２１と実質的に同一の材料および実質的に同一の方法で形成される。   Next, as shown in FIG. 3D, a second plating resist layer 22 is deposited on the first plating resist layer 21 and the electrolytic copper plating layer 3b. The second plating resist layer 22 covers the first plating resist layer 21 and the electrolytic copper plating layer 3b so as to expose only a portion of the wiring conductor 3 that becomes the semiconductor element connection pad 4. Such a second plating resist layer 22 is formed by substantially the same material and substantially the same method as the first plating resist layer 21 described above.

次に、図３（ｅ）に示すように、第１および第２のめっきレジスト層２１，２２から露出する半導体素子接続パッド４となる部位の電解銅めっき層３ｂ上に電解錫めっき層７を被着する。電解錫めっき層７の厚みは２〜５μｍ程度である。このような電解錫めっき層７は、周知の電解錫めっき法により被着される。   Next, as shown in FIG. 3 (e), an electrolytic tin plating layer 7 is formed on the electrolytic copper plating layer 3 b at a portion to be the semiconductor element connection pad 4 exposed from the first and second plating resist layers 21 and 22. Adhere. The thickness of the electrolytic tin plating layer 7 is about 2 to 5 μm. Such an electrolytic tin plating layer 7 is applied by a known electrolytic tin plating method.

次に、図３（ｆ）に示すように、第１および第２のめっきレジスト層２１，２２を除去する。めっきレジスト層２１，２２の除去は、周知のレジスト剥離液を用いて剥離する方法により行なわれる。   Next, as shown in FIG. 3F, the first and second plating resist layers 21 and 22 are removed. The plating resist layers 21 and 22 are removed by a method of peeling using a known resist stripping solution.

次に、図３（ｇ）に示すように、電解銅めっき層３ｂから露出する下地金属層３ａをエッチング除去する。これにより上面に錫めっき層７が被着された半導体素子接続パッド４を一部に有する配線導体３が絶縁基板１の上面に形成される。なお、下地金属層３ａの除去には周知の銅エッチング液を用いる。この際、電解銅めっき層３ｂも若干エッチングされるので、錫めっき層７で覆われていない部分の厚みがエッチングにより薄くなり、錫めっき層７で覆われている半導体素子接続パッド４と錫めっき層７で覆われていない部分との間に１〜５μｍ程度の段差が形成される。   Next, as shown in FIG. 3G, the base metal layer 3a exposed from the electrolytic copper plating layer 3b is removed by etching. As a result, the wiring conductor 3 having a part of the semiconductor element connection pad 4 having the tin plating layer 7 deposited on the upper surface is formed on the upper surface of the insulating substrate 1. A known copper etching solution is used for removing the base metal layer 3a. At this time, since the electrolytic copper plating layer 3b is also slightly etched, the thickness of the portion not covered with the tin plating layer 7 is reduced by etching, and the semiconductor element connection pad 4 covered with the tin plating layer 7 and the tin plating are formed. A step of about 1 to 5 μm is formed between the portion not covered with the layer 7.

最後に、図３（ｈ）に示すように、絶縁基板１および配線導体３上に、錫めっき層７が被着された半導体素子接続パッド４を露出させる開口部６ａを有するソルダーレジスト層６を被着する。これより、図１に示した配線基板１０が完成する。   Finally, as shown in FIG. 3 (h), a solder resist layer 6 having an opening 6a exposing the semiconductor element connection pad 4 on which the tin plating layer 7 is deposited is formed on the insulating substrate 1 and the wiring conductor 3. Adhere. Thereby, the wiring board 10 shown in FIG. 1 is completed.

１ 絶縁基板
３ 配線導体
３ａ 下地金属層
３ｂ 電解銅めっき層
４ 半導体素子接続パッド
６ ソルダーレジスト層
６ａ ソルダーレジスト層の開口部
７ 錫めっき層 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 3 Wiring conductor 3a Base metal layer 3b Electrolytic copper plating layer 4 Semiconductor element connection pad 6 Solder resist layer 6a Opening part of solder resist layer 7 Tin plating layer

Claims (1)

絶縁基板と、該絶縁基板の上面に形成された銅から成る配線導体と、前記絶縁基板および前記配線導体上に被着されており、前記配線導体の一部を半導体素子接続パッドとして露出させる開口部を有するソルダーレジスト層と、前記開口部内に露出する前記配線導体の表面に被着された錫めっき層とを備えた配線基板であって、前記錫めっき層は、前記配線導体の上面のみに被着されていることを特徴とする配線基板。   An insulating substrate, a wiring conductor made of copper formed on the upper surface of the insulating substrate, and an opening that is deposited on the insulating substrate and the wiring conductor and exposes a part of the wiring conductor as a semiconductor element connection pad A solder resist layer having a portion and a tin plating layer deposited on the surface of the wiring conductor exposed in the opening, wherein the tin plating layer is formed only on the upper surface of the wiring conductor. A wiring board characterized by being attached.
JP2012218940A 2012-09-29 2012-09-29 Wiring board Pending JP2014072468A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283853A (en) * 1992-04-03 1993-10-29 Furukawa Electric Co Ltd:The Printed-circuit board
JP2005057223A (en) * 2003-07-31 2005-03-03 Ngk Spark Plug Co Ltd Wiring board, and method for manufacturing wiring board
JP2007073617A (en) * 2005-09-05 2007-03-22 Tamura Seisakusho Co Ltd Electrode structure, substrate for packaging, projection electrode, and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283853A (en) * 1992-04-03 1993-10-29 Furukawa Electric Co Ltd:The Printed-circuit board
JP2005057223A (en) * 2003-07-31 2005-03-03 Ngk Spark Plug Co Ltd Wiring board, and method for manufacturing wiring board
JP2007073617A (en) * 2005-09-05 2007-03-22 Tamura Seisakusho Co Ltd Electrode structure, substrate for packaging, projection electrode, and manufacturing method thereof

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