JP2007150358A - Process for producing wiring board with solder bump and electronic device - Google Patents

Process for producing wiring board with solder bump and electronic device Download PDF

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Publication number
JP2007150358A
JP2007150358A JP2007046114A JP2007046114A JP2007150358A JP 2007150358 A JP2007150358 A JP 2007150358A JP 2007046114 A JP2007046114 A JP 2007046114A JP 2007046114 A JP2007046114 A JP 2007046114A JP 2007150358 A JP2007150358 A JP 2007150358A
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solder
bonding pad
wiring board
solder bonding
insulating substrate
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JP2007046114A
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Japanese (ja)
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Takeshi Sunada
砂田  剛
Osamu Akashi
理 明石
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board with solder bumps in which a void is not formed easily in the solder bump, and the electrode of an electronic component can be bonded firmly to a solder bonding pad through the solder bump. <P>SOLUTION: In the wiring board with solder bumps comprising an insulating substrate 1 where solder bonding pads 3 are formed on the surface, a solder-resistant resin layer 4 deposited on the surface of the insulating substrate 1 while having openings 4a for exposing the central portion of the solder bonding pads 3 and covering the outer circumferential part of the solder bonding pads 3, and solder bumps 5 bonded onto the solder bonding pads 3 exposed in the openings 4a, the solder bonding pad 3 has a protrusion formed integrally such that the surface to which the solder bump 5 is bonded becomes convex, a via conductor having an area in plan view smaller than that of the convex surface is formed integrally on the surface on the opposite side to the convex surface, and the outer circumferential part of the solder bonding pad 3 is extending to the outside of the protrusion and the via conductor in the plan view. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子や抵抗器等の電子部品を搭載するための半田バンプ付き配線基板およびそれを用いた電子装置に関するものである。   The present invention relates to a wiring board with solder bumps for mounting electronic components such as semiconductor elements and resistors, and an electronic device using the wiring board.

近年、半導体素子や抵抗器等の電子部品を搭載するために用いられる配線基板には、ガラス基材および熱硬化性樹脂から成る絶縁板と銅箔等から成る配線導体層とを交互に複数積層して成るプリント基板や、絶縁板上に熱硬化性樹脂およびフィラーから成る絶縁層と銅めっき層から成る配線導体層とを複数積層して成るビルドアップ基板が用いられてきている。   In recent years, a wiring board used for mounting electronic components such as semiconductor elements and resistors is laminated with a plurality of wiring conductor layers made of a glass substrate and a thermosetting resin and copper foil and the like alternately. A printed circuit board formed in this manner, and a build-up board in which a plurality of insulating layers made of a thermosetting resin and filler and a wiring conductor layer made of a copper plating layer are laminated on an insulating plate have been used.

そして、このようなプリント基板やビルドアップ基板等の配線基板の上面には、半導体素子等の電子部品の電極を接続するための半田接合パッドおよびこの半田接合パッドの中央部を露出させる耐半田樹脂層が被着形成されており、さらに、耐半田樹脂層から露出した半田接合パッド上には電子部品と半田接合パッドとを接合するための半田バンプが形成されている。   And on the upper surface of the wiring board such as a printed board or a build-up board, a solder bonding pad for connecting an electrode of an electronic component such as a semiconductor element and a solder-resistant resin that exposes a central portion of the solder bonding pad A layer is deposited, and solder bumps are formed on the solder joint pads exposed from the solder-resistant resin layer for joining the electronic component and the solder joint pads.

そして、このような半田バンプ付きの配線基板においては、電子部品をその各電極がそれぞれ対応する半田バンプに当接するようにして配線基板の上面に載置するとともに、これらを例えば電気炉等の加熱装置で加熱して半田バンプを溶融させて半田バンプと電子部品の電極とを接合させることによって、電子部品が配線基板上に実装される。   In such a wiring board with solder bumps, the electronic component is placed on the upper surface of the wiring board so that each electrode abuts the corresponding solder bump, and these are heated by, for example, an electric furnace or the like. The electronic component is mounted on the wiring board by heating the device to melt the solder bump and bonding the solder bump and the electrode of the electronic component.

なお、このような半田バンプ付きの配線基板は、内部および/または表面に複数の配線導体を有する絶縁基板の表面に、配線導体に接続された略円形の複数の半田接合パッドおよびこの半田接合パッドの中央部を露出させる開口部を有する耐半田樹脂層を被着させ、次に半田接合パッド上にフラックスおよび半田粉末から成る半田ペーストを従来周知のスクリーン印刷法を採用して印刷塗布するとともにこれを加熱して半田ペースト中のフラックスを気化除去するとともに半田ペースト中の半田粉末を溶融させて半田接合パッド上に半田バンプを形成することによって製作されている。
特開2000−124591号公報
Such a wiring board with solder bumps includes a plurality of substantially circular solder bonding pads connected to the wiring conductors on the surface of the insulating substrate having a plurality of wiring conductors inside and / or on the surface, and the solder bonding pads. A solder-resistant resin layer having an opening that exposes the central portion of the solder is applied, and then a solder paste composed of flux and solder powder is printed and applied onto the solder bonding pad using a conventionally known screen printing method. Is heated to evaporate and remove the flux in the solder paste and melt the solder powder in the solder paste to form solder bumps on the solder joint pads.
JP 2000-125991 A

しかしながら、従来の半田バンプ付き配線基板によれば、半田接合パッド上に印刷塗布した半田ペースト中のフラックスを気化除去するとともに半田ペースト中の半田粉末を溶融させて半田接合パッド上に半田バンプを形成する際に、半田ペースト中に含有されるフラックスの一部が溶融した半田中に取り残されて半田バンプ中に大きなボイドを発生させてしまいやすく、半田バンプ中にそのような大きなボイドが多量に発生すると、電子部品の電極と半田接合パッドとを半田バンプを介して接合する際に、電子部品の電極と半田接合パッドとの接合がボイドにより阻害されたり、半田バンプの強度が弱いものとなって、電子部品の電極と半田接合パッドとを半田バンプを介して強固に接合することができなくなってしまうという問題点を有していた。   However, according to the conventional wiring board with solder bumps, the flux in the solder paste printed and applied on the solder bonding pad is vaporized and removed, and the solder powder in the solder paste is melted to form the solder bump on the solder bonding pad. When soldering, some of the flux contained in the solder paste is left behind in the melted solder and easily generates large voids in the solder bumps, and a large amount of such large voids are generated in the solder bumps. Then, when the electrode of the electronic component and the solder bonding pad are bonded via the solder bump, the bonding between the electrode of the electronic component and the solder bonding pad is obstructed by the void, or the strength of the solder bump becomes weak. There is a problem that it becomes impossible to firmly bond the electrode of the electronic component and the solder bonding pad via the solder bump. Which was.

本発明は、かかる従来の問題点に鑑み案出されたものであり、その目的は、半田接合パッド上に形成された半田バンプ中に大きなボイドが形成されにくく、電子部品の電極と半田接合パッドとを半田バンプを介して強固に接合することが可能な半田バンプ付き配線基板を提供することにある。   The present invention has been devised in view of such conventional problems, and an object of the present invention is to prevent formation of large voids in the solder bumps formed on the solder bonding pads, and the electrodes of the electronic components and the solder bonding pads. It is an object of the present invention to provide a wiring board with solder bumps that can be firmly joined to each other via solder bumps.

本発明の半田バンプ付き配線基板は、表面に半田接合パッドが形成された絶縁基板と、該絶縁基板の表面に被着されており、前記半田接合パッドの中央部を露出させる開口部を有するとともに前記半田接合パッドの外周部を被覆する耐半田樹脂層と、前記開口部内に露出した前記半田接合パッド上に接合された半田バンプとを具備して成る半田バンプ付き配線基板であって、前記半田接合パッドは、前記半田バンプが接合された表面が凸面となるように突出部が一体的に形成されているとともに、前記凸面と反対側の表面に前記凸面の平面視面積よりも小さな平面視面積を有するビア導体が一体的に形成されており、さらに前記半田接合パッドの外周部が平面視して前記突出部および前記ビア導体よりも外側に延在していることを特徴とする。   The wiring board with solder bumps of the present invention has an insulating substrate having a solder bonding pad formed on the surface thereof, and is attached to the surface of the insulating substrate, and has an opening that exposes the central portion of the solder bonding pad. A wiring board with solder bumps, comprising: a solder-resistant resin layer covering an outer periphery of the solder bonding pad; and a solder bump bonded onto the solder bonding pad exposed in the opening. The bonding pad is integrally formed with a protruding portion so that the surface to which the solder bump is bonded becomes a convex surface, and has a planar view area smaller than the planar view area of the convex surface on the surface opposite to the convex surface. The solder conductor pad is integrally formed, and the outer periphery of the solder joint pad extends outward from the protrusion and the via conductor in plan view.

本発明の半田バンプ付き配線基板において好ましくは、前記凸面の高さが1〜10μmであることを特徴とする。   In the wiring board with solder bumps of the present invention, preferably, the height of the convex surface is 1 to 10 μm.

本発明の半田バンプ付き配線基板において好ましくは、前記半田接合パッドはめっきにより形成されていることを特徴とする。   In the wiring board with solder bumps of the present invention, preferably, the solder joint pad is formed by plating.

本発明の半田バンプ付き配線基板において好ましくは、前記絶縁基板は樹脂を含むことを特徴とする。   In the wiring board with solder bumps of the present invention, preferably, the insulating substrate contains a resin.

本発明の半田バンプ付き配線基板において好ましくは、前記半田バンプは電子部品の電極が接続されることを特徴とする。   In the wiring board with solder bumps of the present invention, preferably, the solder bumps are connected to electrodes of electronic components.

本発明の半田バンプ付き配線基板において好ましくは、前記凸面とそれに連続する前記半田接合パッドの外周部表面との成す角度が鈍角であることを特徴とする。   The wiring board with solder bumps of the present invention is preferably characterized in that an angle formed between the convex surface and the outer peripheral surface of the solder joint pad continuous thereto is an obtuse angle.

本発明の電子装置は、表面に半田接合パッドが形成された絶縁基板と、該絶縁基板の表面に被着されており、前記半田接合パッドの中央部を露出させる開口部を有するとともに前記半田接合パッドの外周部を被覆する耐半田樹脂層と、前記半田バンプ上に接続された電子部品とを具備して成る電子装置であって、前記半田接合パッドは、前記電子部品が接続された表面が凸面となるように突出部が一体的に形成されているとともに、前記凸面と反対側の表面に前記凸面の平面視面積よりも小さな平面視面積を有するビア導体が一体的に形成されており、さらに前記半田接合パッドの外周部が平面視して前記突出部および前記ビア導体よりも外側に延在していることを特徴とする。   The electronic device according to the present invention includes an insulating substrate having a solder bonding pad formed on a surface thereof, an opening that is attached to the surface of the insulating substrate, and exposes a central portion of the solder bonding pad, and the solder bonding. An electronic device comprising a solder-resistant resin layer covering an outer periphery of a pad and an electronic component connected on the solder bump, wherein the solder joint pad has a surface to which the electronic component is connected. The protrusion is integrally formed to be a convex surface, and a via conductor having a planar view area smaller than the planar view area of the convex surface is integrally formed on the surface opposite to the convex surface, Furthermore, the outer peripheral portion of the solder bonding pad extends outward from the protruding portion and the via conductor in plan view.

本発明によれば、半田接合パッドに半田ペーストを塗布するとともにこれを加熱して半田接合パッド上に半田バンプを形成する際に、半田ペースト中の気化したフラックスが半田接合パッドの表面から離れやすくなり、その結果、半田バンプ中に大きなボイドが形成されにくい。   According to the present invention, when the solder paste is applied to the solder bonding pad and heated to form a solder bump on the solder bonding pad, the vaporized flux in the solder paste is easily separated from the surface of the solder bonding pad. As a result, it is difficult to form a large void in the solder bump.

次に、本発明を添付の図面に基づき詳細に説明する。図1は、本発明の半田バンプ付き配線基板の実施の形態の一例を示す断面図である。また、図2は本発明の半田バンプ付き配線基板の要部拡大断面図である。   Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board with solder bumps of the present invention. FIG. 2 is an enlarged sectional view of a main part of the wiring board with solder bumps of the present invention.

図1において、1は絶縁基板、2は配線導体、3は半田接合パッド、4は耐半田樹脂層、5は半田バンプ、6は外部リードピンであり、主にこれらで本例の半田バンプ付き配線基板が構成されている。なお、この例では外部リードピン6を有する例を示したが、外部リードピン6は必ずしも必要ではなく、外部リードピン6に代えて例えば半田から成る外部接続用の端子を設けてもよい。   In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a solder joint pad, 4 is a solder-resistant resin layer, 5 is a solder bump, and 6 is an external lead pin. A substrate is configured. In this example, the external lead pin 6 is shown. However, the external lead pin 6 is not always necessary, and an external connection terminal made of, for example, solder may be provided instead of the external lead pin 6.

絶縁基板1は、例えばガラス繊維を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状の芯体1aの上下面にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る絶縁層1bをそれぞれ複数層ずつ積層して成り、芯体1aや各絶縁層1bの表面には銅箔や銅めっき膜等の導体層から成る複数の配線導体2が形成されている。   The insulating substrate 1 is made of, for example, epoxy resin or bismaleimide triazine on the upper and lower surfaces of a plate-like core 1a formed by impregnating a glass fabric in which glass fibers are woven vertically and horizontally with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. A plurality of insulating layers 1b made of a thermosetting resin such as a resin are laminated, and a plurality of wiring conductors made of a conductor layer such as a copper foil or a copper plating film are formed on the surface of the core 1a or each insulating layer 1b. 2 is formed.

絶縁基板1を構成する芯体1aは、厚みが0.3〜1.5mm程度であり、その上面から下面にかけて直径が0.1〜1.0mm程度の複数の貫通孔7を有している。そして、各貫通孔7の内壁には配線導体2の一部が被着されており、芯体1aの上下面に形成された配線導体2同士が貫通孔7内の配線導体2を介して電気的に接続されている。   The core 1a constituting the insulating substrate 1 has a thickness of about 0.3 to 1.5 mm and has a plurality of through holes 7 having a diameter of about 0.1 to 1.0 mm from the upper surface to the lower surface. . A part of the wiring conductor 2 is attached to the inner wall of each through hole 7, and the wiring conductors 2 formed on the upper and lower surfaces of the core body 1 a are electrically connected to each other through the wiring conductor 2 in the through hole 7. Connected.

このような芯体1aは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートを熱硬化させた後、これに上面から下面にかけて貫通孔7用のドリル加工を施すことにより製作される。なお、芯体1aの上下面の配線導体2は、芯体1a用のシートの上下全面に厚みが3〜50μm程度の銅箔を貼着しておくとともに、この銅箔をシートの硬化後にエッチング加工することにより芯体1aの上下面に所定のパターンに形成される。また、貫通孔7内の配線導体2は、芯体1aに貫通孔7を設けた後に、この貫通孔7の内壁に無電解めっき法および電解めっき法により厚みが3〜50μm程度の銅めっき膜を析出させることにより貫通孔7の内壁に被着形成される。   Such a core body 1a is manufactured by thermally curing a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the through hole 7 from the upper surface to the lower surface. . The wiring conductors 2 on the upper and lower surfaces of the core body 1a have copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the sheet for the core body 1a, and the copper foil is etched after the sheet is cured. By processing, a predetermined pattern is formed on the upper and lower surfaces of the core body 1a. Further, the wiring conductor 2 in the through hole 7 is a copper plating film having a thickness of about 3 to 50 μm formed on the inner wall of the through hole 7 by electroless plating and electrolytic plating after the through hole 7 is provided in the core 1a. Is deposited on the inner wall of the through hole 7.

さらに、芯体1aは、その貫通孔7の内部にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る樹脂柱8が充填されている。樹脂柱8は、貫通孔7を塞ぐことにより貫通孔7の直上および直下に絶縁層1bを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂を貫通孔7内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。そして、この樹脂柱8を含む芯体1aの上下面に絶縁層1bが積層されている。   Furthermore, the core body 1a is filled with a resin column 8 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin in the through hole 7 thereof. The resin pillar 8 is for making it possible to form the insulating layer 1b directly above and below the through hole 7 by closing the through hole 7. An uncured paste-like thermosetting resin is placed in the through hole 7. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat. And the insulating layer 1b is laminated | stacked on the upper and lower surfaces of the core 1a containing this resin pillar 8. As shown in FIG.

芯体1aの上下面に積層された絶縁層1bは、それぞれの厚みが20〜60μm程度であり、各層の上面から下面にかけて直径が30〜100μm程度の複数の貫通孔9を有しており、これらの貫通孔9内には配線導体2の一部が被着形成されている。これらの絶縁層1bは、配線導体2を高密度に配線するための絶縁間隔を提供するためのものである。そして、上層の配線導体2と下層の配線導体2とを貫通孔9内の配線導体2を介して電気的に接続することにより高密度配線を立体的に形成可能としている。   The insulating layer 1b laminated on the upper and lower surfaces of the core body 1a has a plurality of through holes 9 each having a thickness of about 20 to 60 μm and a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. A part of the wiring conductor 2 is deposited in these through holes 9. These insulating layers 1b are for providing an insulating interval for wiring the wiring conductors 2 with high density. The upper wiring conductor 2 and the lower wiring conductor 2 are electrically connected via the wiring conductor 2 in the through hole 9 so that a high-density wiring can be formed three-dimensionally.

このような絶縁層1bは、厚みが20〜60μm程度の未硬化の熱硬化性樹脂のフィルムを芯体1a上下面に貼着し、これを熱硬化させるとともにレーザー加工により貫通孔9を穿孔し、さらにその上に同様にして次の絶縁層1bを順次積み重ねることによって形成される。なお、各絶縁層1b表面および貫通孔9内に被着された配線導体2は、各絶縁層1bを形成する毎に各絶縁層1bの表面および貫通孔9内に5〜50μm程度の厚みの銅めっき膜を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。   Such an insulating layer 1b is obtained by sticking an uncured thermosetting resin film having a thickness of about 20 to 60 μm to the upper and lower surfaces of the core body 1a, thermosetting it, and drilling through holes 9 by laser processing. Further, it is formed by sequentially stacking the next insulating layer 1b in the same manner. The wiring conductor 2 deposited on the surface of each insulating layer 1b and in the through hole 9 has a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and in the through hole 9 every time each insulating layer 1b is formed. It is formed by depositing a copper plating film in a predetermined pattern by a pattern forming method such as a known semi-additive method or subtractive method.

さらに、最表層の絶縁層1b上には耐半田樹脂層4が被着されている。耐半田樹脂層4は、例えばアクリル変性エポキシ樹脂にシリカやタルク等の無機物粉末フィラーを30〜70質量%程度分散させた絶縁材料から成り、表層の配線導体2同士の電気的絶縁信頼性を高めるとともに、後述する半田接合パッド3やピン接合パッド10の絶縁基板1への接合強度を大きなものとする作用をなす。   Further, a solder-resistant resin layer 4 is deposited on the outermost insulating layer 1b. The solder-resistant resin layer 4 is made of an insulating material in which an inorganic powder filler such as silica or talc is dispersed in an acrylic-modified epoxy resin, for example, in an amount of 30 to 70% by mass, and improves the electrical insulation reliability between the wiring conductors 2 on the surface layer. At the same time, the bonding strength of the solder bonding pad 3 and the pin bonding pad 10 described later to the insulating substrate 1 is increased.

このような耐半田樹脂層4は、その厚みが10〜50μm程度であり、感光性を有する耐半田樹脂層4用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して最表層の絶縁層1b上に塗布し、これを乾燥させた後、露光および現像処理を行なって半田接合パッド3やピン接合パッド10の中央部を露出させる開口部4a、4bを形成した後、これを熱硬化させることによって形成される。あるいは、耐半田樹脂層4用の未硬化の樹脂フィルムを最上層の絶縁層1b上に貼着した後、これを熱硬化させ、しかる後、半田接合パッド3やピン接合パッド10に対応する位置にレーザービームを照射し、硬化した樹脂フィルムを部分的に除去することによって半田接合パッド3やピン接合パッド10を露出させる開口部4a、4bを有するように形成される。   Such a solder-resistant resin layer 4 has a thickness of about 10 to 50 μm, and an uncured resin paste for the solder-resistant resin layer 4 having photosensitivity is applied to the outermost layer by employing a roll coater method or a screen printing method. After coating on the insulating layer 1b and drying it, exposure and development processes are performed to form openings 4a and 4b that expose the central portions of the solder bonding pads 3 and the pin bonding pads 10, and then this is heated. It is formed by curing. Alternatively, after an uncured resin film for the solder-resistant resin layer 4 is stuck on the uppermost insulating layer 1b, it is thermally cured, and then the position corresponding to the solder bonding pad 3 or the pin bonding pad 10 Are formed so as to have openings 4a and 4b exposing the solder bonding pad 3 and the pin bonding pad 10 by partially removing the cured resin film.

また、絶縁基板1の上面から下面にかけて形成された配線導体2は、電子部品の各電極を外部電気回路基板に接続するための導電路として機能し、絶縁基板1の上面の実装領域に設けられた部位の一部が電子部品の各電極に例えば鉛−錫合金から成る半田バンプ5を介して接合される半田接合パッド3を、絶縁基板1の下面に露出した部位の一部が外部電気回路基板に接続される外部リードピン6を接合するためのピン接合パッド10を形成している。   The wiring conductor 2 formed from the upper surface to the lower surface of the insulating substrate 1 functions as a conductive path for connecting each electrode of the electronic component to the external electric circuit substrate, and is provided in a mounting region on the upper surface of the insulating substrate 1. A part of the exposed part of the solder bonding pad 3 is bonded to each electrode of the electronic component via a solder bump 5 made of, for example, a lead-tin alloy, and a part of the part exposed on the lower surface of the insulating substrate 1 is an external electric circuit. A pin bonding pad 10 for bonding external lead pins 6 connected to the substrate is formed.

このような半田接合パッド3やピン接合パッド10は、配線導体2に接続された導体層から成る略円形のパターンの外周部を耐半田樹脂層4により15〜35μm程度の幅で被覆してその外周縁を画定することによりその直径が、半田接合パッド3であれば70〜200μm程度に、ピン接合パッド10であれば0.5〜2.5mm程度になるように形成されている。   Such solder joint pads 3 and pin joint pads 10 are formed by covering the outer periphery of a substantially circular pattern made of a conductor layer connected to the wiring conductor 2 with a solder-resistant resin layer 4 with a width of about 15 to 35 μm. By defining the outer periphery, the diameter of the solder bonding pad 3 is about 70 to 200 μm, and the pin bonding pad 10 is about 0.5 to 2.5 mm.

なお、このように半田接合パッド3およびピン接合パッド10の外周部を耐半田樹脂層4により被覆することによって、半田接合パッド3同士やピン接合パッド10同士の電気的な短絡が有効に防止されるとともに、半田接合パッド3やピン接合パッド10の絶縁基板1に対する接合強度が高いものとなっている。   In addition, by covering the outer periphery of the solder bonding pad 3 and the pin bonding pad 10 with the solder-resistant resin layer 4 in this way, an electrical short circuit between the solder bonding pads 3 and the pin bonding pads 10 is effectively prevented. In addition, the bonding strength of the solder bonding pad 3 and the pin bonding pad 10 to the insulating substrate 1 is high.

なお、通常であれば、半田接合パッド3およびピン接合パッド10の露出する表面には、半田接合パッド3やピン接合パッド10の酸化腐蝕の防止と半田バンプ5や外部リードピン6との接続を良好にするために、ニッケル、金等の良導電性で耐腐蝕性に優れた金属をめっき法により1〜20μmの厚さに被着することが好ましい。   Normally, the exposed surfaces of the solder bonding pad 3 and the pin bonding pad 10 are excellent in preventing the oxidative corrosion of the solder bonding pad 3 and the pin bonding pad 10 and connecting the solder bumps 5 and the external lead pins 6 to each other. Therefore, it is preferable to deposit a metal having good conductivity and corrosion resistance, such as nickel and gold, to a thickness of 1 to 20 μm by plating.

また、半田接合パッド3には、半田バンプ5が接合されている。半田バンプ5は、鉛−錫合金等の半田材料から成り、半田接合パッド3と電子部品とを電気的および機械的に接続するための端子として機能し、電子部品の各電極がそれぞれ対応する半田バンプ5に当接するようにして電子部品を載置するとともに、これらを例えば電気炉などの加熱装置で加熱して半田バンプ5を溶融させることにより半田バンプ5と電子部品の電極とが接続される。   Solder bumps 5 are bonded to the solder bonding pads 3. The solder bump 5 is made of a solder material such as a lead-tin alloy and functions as a terminal for electrically and mechanically connecting the solder bonding pad 3 and the electronic component, and each electrode of the electronic component corresponds to a corresponding solder. The electronic components are placed so as to be in contact with the bumps 5 and are heated by a heating device such as an electric furnace to melt the solder bumps 5 so that the solder bumps 5 and the electrodes of the electronic components are connected. .

なお、半田接合パッド3に半田バンプ5を接合するには、半田接合パッド3上に半田ペーストを従来周知のスクリーン印刷法を採用して印刷塗布した後、その半田ペーストを加熱して半田ペースト中のフラックスを気化除去するとともに半田ペースト中の半田を溶融させる方法が採用される。   In order to join the solder bumps 5 to the solder joint pads 3, after applying and applying a solder paste onto the solder joint pads 3 by using a conventionally known screen printing method, the solder paste is heated to be contained in the solder paste. A method of vaporizing and removing the flux and melting the solder in the solder paste is employed.

して、本発明の半田バンプ付き配線基板においては、図2に要部拡大断面図で示すように、半田接合パッド3の半田バンプ5が接合された面が凸面となっており、そのことが重要である。このように、半田接合パッド3の半田バンプ5が接合された面が凸面となっていることから、半田接合パッド3の上に半田ペーストを印刷塗布するとともにその半田ペーストを加熱して半田バンプ5を接合する際に半田ペースト中の気化したフラックスが半田接合パッド3の表面から離れやすくなり、その結果、半田バンプ5中に大きなボイドが多量に発生することが有効に防止される。   In the wiring board with solder bumps of the present invention, as shown in the enlarged sectional view of the main part in FIG. 2, the surface of the solder bonding pad 3 to which the solder bumps 5 are bonded is a convex surface. is important. Thus, since the surface where the solder bump 5 of the solder bonding pad 3 is bonded is a convex surface, the solder paste is printed on the solder bonding pad 3 and the solder paste is heated to solder bump 5. When the solder is bonded, the vaporized flux in the solder paste is easily separated from the surface of the solder bonding pad 3, and as a result, it is effectively prevented that a large amount of large voids are generated in the solder bump 5.

なお、半田接合パッド3の半田バンプ5が接合される表面を凸面とするには、半田接合パッド3を形成する際に、例えばめっき液が半田接合パッド3の中央部に多く当たるようなめっき液の流れを作ってめっきを施すことにより、半田接合パッド3の中央部における銅めっき膜の厚みを厚いものとすればよい。   In order to make the surface to which the solder bumps 5 of the solder bonding pad 3 are bonded convex, for example, when forming the solder bonding pad 3, a plating solution in which a large amount of the plating solution hits the central portion of the solder bonding pad 3 is used. The thickness of the copper plating film at the center portion of the solder bonding pad 3 may be increased by performing the above-described flow for plating.

また、半田接合パッド3の半田バンプ5が接合される凸面の高さが1μm未満の場合、半田接合パッド3に半田ペーストを印刷塗布するとともにその半田ペーストを加熱して半田バンプ5を形成する際に、半田ペースト中の気化したフラックスが半田接合パッド3から離れにくくなり、その結果、半田バンプ3中に大きなボイドが発生しやすくなる傾向にあり、他方、10μmを超えると、耐半田樹脂4の開口部4a内に露出した半田接合パッド3の外周部に耐半田樹脂層4の樹脂の残渣が発生しやすくなり、そのような残渣が発生すると、半田接合パッド3上に半田バンプ5を強固に接合することが困難となってしまう。したがって、半田接合パッド3の半田バンプ5が接合される凸面の高さは1〜10μmの範囲が好ましい。   When the height of the convex surface to which the solder bump 5 of the solder bonding pad 3 is bonded is less than 1 μm, the solder paste 5 is printed and applied to the solder bonding pad 3 and the solder paste 5 is heated to form the solder bump 5. In addition, the vaporized flux in the solder paste is less likely to be separated from the solder bonding pad 3, and as a result, a large void tends to be generated in the solder bump 3. On the other hand, if the solder paste exceeds 10 μm, the solder-resistant resin 4 Resin residue of the solder-resistant resin layer 4 is likely to be generated on the outer peripheral portion of the solder bonding pad 3 exposed in the opening 4a, and when such a residue is generated, the solder bump 5 is firmly attached on the solder bonding pad 3. It becomes difficult to join. Therefore, the height of the convex surface to which the solder bump 5 of the solder bonding pad 3 is bonded is preferably in the range of 1 to 10 μm.

また、ピン接合パッド10には、銅や鉄−ニッケル−コバルト合金等の金属から成る外部リードピン6が半田バンプ5よりも融点が高い半田を介して接合されている。外部リードピン6は、配線基板に実装される電子部品を外部電気回路基板に電気的に接続するための端子部材として機能し、外部リードピン6を外部電気回路基板の配線導体に半田やソケットを介して接続することにより、電子部品が外部電気回路に電気的に接続されることとなる。   In addition, external lead pins 6 made of a metal such as copper or iron-nickel-cobalt alloy are bonded to the pin bonding pads 10 via solder having a melting point higher than that of the solder bumps 5. The external lead pin 6 functions as a terminal member for electrically connecting an electronic component mounted on the wiring board to the external electric circuit board. The external lead pin 6 is connected to the wiring conductor of the external electric circuit board via solder or a socket. By connecting, the electronic component is electrically connected to the external electric circuit.

かくして、本発明の半田バンプ付き配線基板によると、配線基板1の上面に電子部品をその電極が半田バンプ5に当接するようにして載置するとともに、半田バンプ5を溶融させて電子部品の電極と半田接合パッド3とを接合させることにより製品としての本発明の電子装置となる。   Thus, according to the wiring substrate with solder bumps of the present invention, the electronic component is placed on the upper surface of the wiring substrate 1 so that the electrode contacts the solder bump 5, and the solder bump 5 is melted to form the electrode of the electronic component. By bonding the solder bonding pad 3 to the solder bonding pad 3, the electronic device of the present invention as a product is obtained.

なお、本発明は、上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更が可能であることはいうまでもない。   In addition, this invention is not limited to an example of the above-mentioned embodiment, It cannot be overemphasized that a various change is possible if it is a range which does not deviate from the summary of this invention.

本発明の半田バンプ付き配線基板の実施形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the wiring board with a solder bump of this invention. 図1に示す半田バンプ付き配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the wiring board with a solder bump shown in FIG.

符号の説明Explanation of symbols

1・・・・・絶縁基板
2・・・・・配線導体
3・・・・・半田接合パッド
4・・・・・耐半田樹脂層
4a・・・耐半田樹脂層の開口部
5・・・・・半田バンプ
DESCRIPTION OF SYMBOLS 1 ... Insulation board | substrate 2 ... Wiring conductor 3 ... Solder joint pad 4 ... Solder-resistant resin layer 4a ... Opening part 5 of solder-resistant resin layer ... ..Solder bumps

Claims (7)

表面に半田接合パッドが形成された絶縁基板と、該絶縁基板の表面に被着されており、前記半田接合パッドの中央部を露出させる開口部を有するとともに前記半田接合パッドの外周部を被覆する耐半田樹脂層と、前記開口部内に露出した前記半田接合パッド上に接合された半田バンプとを具備して成る半田バンプ付き配線基板であって、前記半田接合パッドは、前記半田バンプが接合された表面が凸面となるように突出部が一体的に形成されているとともに、前記凸面と反対側の表面に前記凸面の平面視面積よりも小さな平面視面積を有するビア導体が一体的に形成されており、さらに前記半田接合パッドの外周部が平面視して前記突出部および前記ビア導体よりも外側に延在していることを特徴とする半田バンプ付き配線基板。 An insulating substrate having a solder bonding pad formed on the surface, and an insulating substrate that is attached to the surface of the insulating substrate, has an opening that exposes the central portion of the solder bonding pad, and covers the outer periphery of the solder bonding pad A wiring board with solder bumps comprising a solder-resistant resin layer and solder bumps bonded onto the solder bonding pads exposed in the openings, wherein the solder bonding pads are bonded to the solder bumps. And a via conductor having a planar view area smaller than the planar view area of the convex surface is integrally formed on the surface opposite to the convex surface. And a solder bump-equipped wiring board, wherein an outer peripheral portion of the solder bonding pad extends outwardly from the protruding portion and the via conductor in plan view. 前記凸面の高さが1〜10μmであることを特徴とする請求項1記載の半田バンプ付き配線基板。 The wiring board with solder bumps according to claim 1, wherein the height of the convex surface is 1 to 10 μm. 前記半田接合パッドはめっきにより形成されていることを特徴とする請求項1または請求項2記載の半田バンプ付き配線基板。 3. The wiring board with solder bumps according to claim 1, wherein the solder bonding pads are formed by plating. 前記絶縁基板は樹脂を含むことを特徴とする請求項1乃至請求項3のいずれかに記載の半田バンプ付き配線基板。 The wiring board with solder bumps according to any one of claims 1 to 3, wherein the insulating substrate contains a resin. 前記半田バンプは電子部品の電極が接続されることを特徴とする請求項1乃至請求項4のいずれかに記載の半田バンプ付き配線基板。 The wiring board with solder bumps according to any one of claims 1 to 4, wherein an electrode of an electronic component is connected to the solder bumps. 前記凸面とそれに連続する前記半田接合パッドの外周部表面との成す角度が鈍角であることを特徴とする請求項1乃至請求項5のいずれかに記載の半田バンプ付き配線基板。 6. The wiring board with solder bumps according to claim 1, wherein an angle formed between the convex surface and the outer peripheral surface of the solder joint pad continuous thereto is an obtuse angle. 表面に半田接合パッドが形成された絶縁基板と、該絶縁基板の表面に被着されており、前記半田接合パッドの中央部を露出させる開口部を有するとともに前記半田接合パッドの外周部を被覆する耐半田樹脂層と、前記半田バンプ上に接続された電子部品とを具備して成る電子装置であって、前記半田接合パッドは、前記電子部品が接続された表面が凸面となるように突出部が一体的に形成されているとともに、前記凸面と反対側の表面に前記凸面の平面視面積よりも小さな平面視面積を有するビア導体が一体的に形成されており、さらに前記半田接合パッドの外周部が平面視して前記突出部および前記ビア導体よりも外側に延在していることを特徴とする電子装置。 An insulating substrate having a solder bonding pad formed on the surface, and an insulating substrate that is attached to the surface of the insulating substrate, has an opening that exposes the central portion of the solder bonding pad, and covers the outer periphery of the solder bonding pad An electronic device comprising a solder-resistant resin layer and an electronic component connected on the solder bump, wherein the solder joint pad has a protruding portion so that a surface to which the electronic component is connected is a convex surface Are formed integrally, and a via conductor having a planar view area smaller than the planar view area of the convex surface is integrally formed on the surface opposite to the convex surface, and the outer periphery of the solder joint pad An electronic device characterized in that a portion extends outside the projecting portion and the via conductor in plan view.
JP2007046114A 2007-02-26 2007-02-26 Process for producing wiring board with solder bump and electronic device Withdrawn JP2007150358A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011043102A1 (en) * 2009-10-06 2011-04-14 株式会社フジクラ Circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011043102A1 (en) * 2009-10-06 2011-04-14 株式会社フジクラ Circuit board
CN102474989A (en) * 2009-10-06 2012-05-23 株式会社藤仓 Circuit board
JPWO2011043102A1 (en) * 2009-10-06 2013-03-04 株式会社フジクラ Circuit board

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