JP2014150086A - Wiring board and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board excellent in joining strength between a base copper foil and an electrolytic copper plating layer which form the wiring board.SOLUTION: A wiring board 10 includes: an insulating substrate 1; a wiring conductor 2 which comprises a base copper foil 2a deposited on the insulating substrate 1 and a first electrolytic copper plating layer 2b deposited on the base copper foil 2a; and a solder resist layer 3 which is deposited on the insulating substrate 1 and the wiring conductor 2 and exposes part of a side surface and an upper surface of the wiring conductor 2, wherein the side surface and the upper surface are coated with a tin plating layer 2e. The side surface and the upper surface of the wiring conductor 2 are coated with a second electrolytic copper plating layer 2d, and a surface of the second electrolytic copper plating layer 2d is coated with the tin plating layer 2e.

Description

  The present invention relates to a wiring board used for mounting an electronic component such as a semiconductor element and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, there is known a wiring board on which a semiconductor element having electrode terminals arranged peripherally on the outer periphery of a lower surface is mounted by flip chip connection. An example of such a conventional wiring board 20 is shown in FIGS. A conventional wiring board 20 includes an insulating substrate 11, a wiring conductor 12, and a solder resist 13. In FIG. 6B, a portion of the wiring conductor 12 on the upper surface of the insulating substrate 11 that is covered with the solder resist layer 13 is indicated by a broken line.

  The insulating substrate 11 is made of, for example, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin, and has a mounting portion 11a for mounting the semiconductor element S on the center of the upper surface thereof. A number of through holes 14 are formed from the upper surface to the lower surface of the insulating substrate 11.

  The wiring conductor 12 is made of a copper foil or a copper plating layer, and is led out from the mounting portion 11 a on the upper surface of the insulating substrate 11 to the lower surface of the insulating substrate 11 through the inner wall of the through hole 14. The wiring conductor 12 on the upper surface of the insulating substrate 11 has a large number of semiconductor element connection pads 15 on the outer periphery of the mounting portion 11a. The semiconductor element connection pads 15 are arranged in two rows along the outer periphery of the semiconductor element S. Further, a lead wiring 16 is connected to each semiconductor element connection pad 15. The lead wiring 16 connected to the semiconductor element connection pad 15 in the inner row extends to the center side of the mounting portion 11a, and the lead wiring 16 connected to the semiconductor element connection pad 15 in the outer row is connected to the mounting portion 11a. It extends outward. Further, the wiring conductor 12 on the lower surface of the insulating substrate 11 has a large number of external connection pads 17. These external connection pads 17 are arranged in a grid on the lower surface of the insulating substrate 11. Corresponding semiconductor element connection pads 15 and external connection pads 17 are electrically connected to each other via lead wires 16 and wiring conductors 12 in the through holes 14.

  The solder resist layer 13 is made of a thermosetting resin such as an epoxy resin, and is attached to the upper and lower surfaces of the insulating substrate 11 and filled in the through holes 14. In the solder resist layer 13, an opening 13 a is formed on the upper surface side of the insulating substrate 11 to expose the semiconductor element connection pad 15 and a part of the lead wiring 16 connected thereto. The opening 13a has a rectangular frame shape along the outer peripheral portion of the mounting portion 11a so as to expose a part of the inner and outer two rows of semiconductor element connection pads 15 and a part of the lead wiring 16 connected thereto. . The solder resist layer 13 is formed with an opening 13 b that exposes the external connection pad 17 on the lower surface side of the insulating substrate 11. The opening 13b has a circular shape that exposes each external connection pad 17 individually.

  According to this conventional wiring substrate 20, the semiconductor element S is arranged on the mounting portion 11a so that the respective electrode terminals T and the corresponding semiconductor element connection pads 15 face each other, and the electrode terminals T and the semiconductor elements. By connecting the connection pads 15 via the solder bumps B, the semiconductor element S is mounted on the mounting portion 11a. The solder bump B is formed by depositing a tin plating layer on the exposed surface of the semiconductor element connection pad 15 and the lead-out wiring 16, and melting the tin plating layer by reflow.

  By the way, the wiring conductor 12 on the upper surface of the insulating substrate 11 in the wiring substrate 20 is formed as follows. First, as shown in FIG. 7A, a base copper foil 12 a is attached to the upper surface of the insulating substrate 11. The thickness of the base copper foil 12a is about 1 to 3 μm.

  Next, as shown in FIG. 7B, a plating resist layer R having an opening corresponding to the pattern of the wiring conductor 12 is formed on the upper surface of the base copper foil 12a. The thickness of the plating resist layer R is about 15 to 50 μm.

  Next, as shown in FIG. 7C, an electrolytic copper plating layer 12b is deposited on the underlying copper foil 12a exposed from the plating resist layer R. The thickness of the electrolytic copper plating layer 12b is about 10 to 30 μm.

  Next, as shown in FIG. 8D, an electrolytic tin plating layer 12c is deposited on the electrolytic copper plating layer 12b exposed from the plating resist layer R. The thickness of the electrolytic tin plating layer 12c is about 2 to 5 μm.

  Next, as shown in FIG. 8E, the plating resist layer R is peeled and removed.

  Next, as shown in FIG. 8F, by using the electrolytic tin plating layer 12c as an etching mask, the portion of the base copper foil 12a that is not covered with the electrolytic copper plating layer 12b is removed by etching.

  Next, as shown in FIG. 9G, the electrolytic tin plating layer 12c is removed by etching. Thereby, the wiring conductor 12 which consists of the base copper foil 12a and the electrolytic copper plating layer 12b is formed.

  Further, as shown in FIG. 9H, a solder resist layer 13 that exposes a part of the wiring conductor 12 is formed on the insulating substrate 11.

  Next, as shown in FIG. 9I, an electrolytic tin plating layer 12d is deposited on the surface of the base copper foil 12a and the electrolytic copper plating layer 12b exposed from the solder resist 13. The thickness of the electrolytic tin plating layer 12d is 2 to 5 μm. The electrolytic tin plating layer 12d is reflowed and melted to complete the wiring board 20 having the solder bumps B made of tin.

  However, according to this conventional wiring board 20, when the portion of the base copper foil 12a not covered with the electrolytic copper plating layer 12b is removed by etching, as shown in FIG. 10, the base copper foil 12a and the electrolytic copper plating layer are removed. The interface of 12b may be preferentially etched to form a constriction between the underlying copper foil 12a and the electrolytic copper plating layer 12b. When such a constriction occurs, the electrolytic tin plating layer 12d is deposited thereon and then reflowed. As shown in FIG. Since the alloy layer is formed by entering the boundary with the copper plating layer 12b, there is a problem that the bonding strength between the base copper foil 12a and the electrolytic copper plating layer 12b is lowered.

JP 2013-8805 A

  The problem of the present invention is that even when a constriction occurs between the underlying copper foil forming the wiring conductor and the electrolytic copper plating layer thereon, the electrolytic tin plating layer is deposited thereon and reflowed. In this case, the molten electrolytic tin plating layer does not enter the boundary between the base copper foil and the electrolytic copper plating layer and forms an alloy, and the bonding strength between the base copper foil and the electrolytic copper plating layer is excellent. It is to provide a wiring board.

  The wiring board of the present invention comprises an insulating substrate, a base copper foil deposited on the insulating substrate, a wiring conductor comprising a first electrolytic copper plating layer deposited on the base copper foil, and the insulating substrate. And a solder resist layer that is deposited on the wiring conductor and exposes part of the side surface and top surface of the wiring conductor, and the side surface and top surface are covered with a tin plating layer. The wiring conductor is characterized in that the side surface and the upper surface are covered with a second electrolytic copper plating layer, and the surface of the second electrolytic copper plating layer is covered with the tin plating layer. Is.

  The method for manufacturing a wiring board of the present invention includes a step of depositing a base copper foil on an insulating substrate, a step of depositing a first electrolytic copper plating layer on the base copper foil in a pattern of a wiring conductor, Etching and removing the base copper foil not covered with the first electrolytic copper plating layer to form a wiring conductor comprising the base copper foil and the first electrolytic copper plating layer; and at least one of the wiring conductors And a step of covering the side surface and upper surface of the part with a second electrolytic copper plating layer and a step of covering the exposed surface of the second electrolytic copper plating layer with a tin plating layer.

  According to the wiring board of the present invention, the exposed side surface and the upper surface of the wiring conductor composed of the base copper foil and the first electrolytic copper plating layer thereon are covered with the second electrolytic copper plating layer, Since the surface of the electrolytic copper plating layer is covered with the tin plating layer, the boundary between the base copper foil and the first electrolytic copper plating layer on the side surface of the wiring conductor is covered with the second electrolytic copper plating layer for protection. Therefore, it is possible to effectively prevent the molten tin plating layer from entering the interface between the base copper foil and the first electrolytic copper plating layer when the tin plating layer is reflowed. As a result, the bonding strength between the base copper foil forming the wiring conductor and the first electrolytic copper plating layer can be kept good.

  According to the method for manufacturing a wiring board of the present invention, after forming the wiring conductor composed of the base copper foil and the first electrolytic copper plating layer thereon, at least a part of the side surface and the upper surface of the wiring conductor are formed on the second side. Since the surface of the second electrolytic copper plating layer is finally covered with a tin plating layer, the boundary between the base copper foil and the first electrolytic copper plating layer on the side surface of the wiring conductor is Since it is in a state of being protected by being covered with the second electrolytic copper plating layer, the molten tin plating layer enters the interface between the base copper foil and the first electrolytic copper plating layer when the tin plating layer is reflowed. This can be effectively prevented. Therefore, it is possible to provide a wiring board capable of maintaining good bonding strength between the base copper foil forming the wiring conductor and the first electrolytic copper plating layer.

FIG. 1A is a schematic cross-sectional view showing an example of an embodiment of the wiring board of the present invention, and FIG. 1B is a schematic top view thereof. FIG. 2 is an enlarged cross-sectional view of a main part of the wiring board shown in FIG. FIGS. 3A to 3C are enlarged perspective views of main parts for explaining a method of manufacturing the wiring board shown in FIG. 4D to 4F are enlarged perspective views of main parts for explaining a method of manufacturing the wiring board shown in FIG. FIGS. 5G to 5I are enlarged perspective views of main parts for explaining a method of manufacturing the wiring board shown in FIG. FIG. 6A is a schematic cross-sectional view showing a conventional wiring board, and FIG. 6B is a schematic top view thereof. FIGS. 7A to 7C are enlarged perspective views of main parts for explaining a method of manufacturing the wiring board shown in FIG. 8D to 8F are enlarged perspective views of main parts for explaining a method of manufacturing the wiring board shown in FIG. FIGS. 9G to 9I are enlarged perspective views of main parts for explaining a method of manufacturing the wiring board shown in FIG. 10 is an enlarged cross-sectional view of a main part of the wiring board shown in FIG. 11 is an enlarged cross-sectional view of a main part of the wiring board shown in FIG.

  Next, the wiring board and the manufacturing method thereof according to the present invention will be described with reference to FIGS. 1A and 1B show an example of an embodiment of a wiring board 10 of the present invention. The wiring substrate 10 of this example is mainly composed of an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3. In FIG. 1B, a portion of the wiring conductor 2 on the upper surface of the insulating substrate 1 that is covered with the solder resist layer 3 is indicated by a broken line.

  The insulating substrate 1 is, for example, a resin-based electric material obtained by thermosetting a single-layer or multilayer insulating layer having a thickness of about 30 to 200 μm in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. It is made of an insulating material and has a mounting portion 1a for mounting the semiconductor element S at the center of the upper surface. Further, a through hole 4 having a diameter of about 50 to 300 μm is formed in the insulating substrate 1 from the upper surface to the lower surface.

  The wiring conductor 2 is made of a copper foil or a copper plating layer, and is led out from the mounting portion 1 a on the upper surface of the insulating substrate 1 to the lower surface of the insulating substrate 1 through the inner wall of the through hole 4. The thickness of the wiring conductor 2 is about 10 to 20 μm. The wiring conductor 2 on the upper surface of the insulating substrate 1 has a large number of semiconductor element connection pads 5 on the outer periphery of the mounting portion 1a. Each semiconductor element connection pad 5 has a width of about 10 to 30 μm and a length of about 20 to 60 μm. These semiconductor element connection pads 5 are arranged in two rows along the outer periphery of the semiconductor element S. Furthermore, a lead wiring 6 is connected to each semiconductor element connection pad 5. The width of the lead wiring 6 is about 10 to 30 μm at the connection portion with the semiconductor element connection pad 5. The lead wiring 6 connected to the semiconductor element connection pad 5 in the inner row extends to the center side of the mounting portion 1a, and the lead wiring 6 connected to the semiconductor element connection pad 5 in the outer row is connected to the mounting portion 1a. It extends outward. The wiring conductor 2 on the lower surface of the insulating substrate 1 has a large number of external connection pads 7. The diameter of the external connection pad 7 is about 200 to 500 μm. These external connection pads 7 are arranged in a grid on the lower surface of the insulating substrate 1. Corresponding semiconductor element connection pads 5 and external connection pads 7 are electrically connected to each other via the lead wiring 6 and the wiring conductor 2 in the through hole 4.

  The solder resist layer 3 is made of a thermosetting resin such as an epoxy resin, is attached to the upper and lower surfaces of the insulating substrate 1 and is filled in the through holes 4. The thickness of the solder resist layer 3 is about 20 to 40 μm at the portions deposited on the upper and lower surfaces of the insulating substrate 1. In the solder resist layer 3, an opening 3 a is formed on the upper surface side of the insulating substrate 1 to expose a part of the semiconductor element connection pad 5 and the lead wiring 6 connected thereto. The opening 3a has a rectangular frame shape along the outer peripheral portion of the mounting portion 1a so as to expose a part of the inner and outer two rows of semiconductor element connection pads 5 and a part of the lead wiring 6 connected thereto. . In addition, the width | variety of the extraction wiring 6 exposed from the opening part 3a is about 10-30 micrometers, and length is about 20-60 micrometers. The solder resist layer 3 is formed with an opening 3 b that exposes the external connection pad 7 on the lower surface side of the insulating substrate 1. The opening 3b has a circular shape that exposes each external connection pad 7 individually.

  According to this wiring substrate 10, the semiconductor element S is arranged on the mounting portion 1 a so that each electrode terminal T and the corresponding semiconductor element connection pad 5 face each other, and the electrode terminal T and the semiconductor element connection pad 5. Are connected via the solder bumps B, the semiconductor element S is mounted on the mounting portion 1a.

  Here, a method of forming the wiring conductor 2 on the wiring substrate 10 will be described below. First, as shown in FIG. 2, it is formed of a base copper foil 2a and a first electrolytic copper plating layer 2b thereon. The semiconductor element connection pad 5 and the lead wiring 6 exposed in the opening 3a are covered with the second electrolytic copper plating layer 2d on the side surfaces and the upper surface. Furthermore, the surface of the second electrolytic copper plating layer 2d is covered with an electrolytic tin plating layer 2e. Then, the solder tin B made of tin is formed on the semiconductor element connection pad 5 by reflowing and melting the electrolytic tin plating layer 2 e at a temperature of 240 to 255 ° C.

  In this case, the exposed side surface and upper surface of the wiring conductor 2 composed of the base copper foil 2a and the first electrolytic copper plating layer 2b thereon are covered with the second electrolytic copper plating layer 2d, and the second electrolytic copper Since the surface of the plating layer 2d is covered with the electrolytic tin plating layer 2e, the boundary between the base copper foil 2a and the first electrolytic copper plating layer 2b on the side surface of the exposed portion of the wiring conductor 2 is the second electrolytic copper. Since it is covered and protected by the plating layer 2d, the molten tin plating layer 2e when the electrolytic tin plating layer 2e is reflowed enters the interface between the base copper foil 2a and the first electrolytic copper plating layer 2b. It can be effectively prevented. As a result, the bonding strength between the base copper foil 2a forming the wiring conductor 2 and the first electrolytic copper plating layer 2b can be kept good.

  By the way, the wiring conductor 12 in this wiring board 20 is manufactured as follows. First, as shown in FIG. 3A, a base copper foil 2 a is attached to the surface of the insulating substrate 1. The thickness of the base copper foil 2a is about 1 to 3 μm. In order to deposit the base copper foil 2a on the surface of the insulating substrate 1, a prepreg for the insulating substrate 1 is prepared, and the base copper foil 2a is superimposed on the upper surface of the prepreg and heated while pressing from above and below to cure the prepreg. Is adopted.

  Next, as shown in FIG. 3B, a plating resist layer R having an opening corresponding to the pattern of the wiring conductor 2 is deposited on the upper surface of the base copper foil 2a. The thickness of the plating resist layer R is about 15 to 50 μm. The plating resist R is formed by adhering a commercially available photosensitive resist film onto the underlying copper foil 2a and exposing and developing it into a predetermined pattern using a well-known photolithography technique.

  Next, as shown in FIG. 3C, the first electrolytic copper plating layer 12 b is deposited on the base copper foil 12 a exposed from the plating resist layer R. The thickness of the 1st electrolytic copper plating layer 2b is about 10-30 micrometers.

  Next, as shown in FIG. 4D, an electrolytic tin plating layer 2c is deposited on the first electrolytic copper plating layer 2b exposed from the plating resist layer R. The thickness of the electrolytic tin plating layer 2c is about 2 to 5 μm.

  Next, as shown in FIG. 4E, the plating resist layer R is peeled and removed.

  Next, as shown in FIG. 4F, by using the electrolytic tin plating layer 12c as an etching mask, the portion of the base copper foil 2a that is not covered with the first electrolytic copper plating layer 12b is removed by etching. .

  Next, as shown in FIG. 5G, the electrolytic tin plating layer 2c is removed by etching. Thereby, the wiring conductor 2 which consists of the base copper foil 2a and the 1st electrolytic copper plating layer 2b is formed.

  Further, as shown in FIG. 5 (h), a solder resist layer 3 is formed on the insulating substrate 1 to expose a part of the side surface and the upper surface of the wiring conductor 2.

  Next, as shown in FIG. 5 (i), a second electrolytic copper plating layer 2d and an electrolytic tin plating layer 2e are formed on the surface of the base copper foil 2a and the first electrolytic copper plating layer 2b exposed from the solder resist layer 3. Are sequentially applied. The thickness of the electrolytic copper plating layer 2d is 2 to 5 μm. The thickness of the electrolytic tin plating layer 2e is 2 to 5 μm.

  Finally, the electrolytic tin plating layer 2e is reflowed and melted to complete the wiring board 10 having the solder bumps B made of tin shown in FIG.

  In this case, after forming the wiring conductor 2 composed of the base copper foil 2a and the first electrolytic copper plating layer 2b thereon, at least a part of the side surface and the upper surface of the wiring conductor 2 are formed on the second electrolytic copper plating layer 2d. Since the surface of the second electrolytic copper plating layer 2d is covered with the electrolytic tin plating layer 2e, the boundary between the base copper foil 2a and the first electrolytic copper plating layer 3b on the side surface of the wiring conductor 2 is Since it is covered and protected by the second electrolytic copper plating layer 2d, the electrolytic tin plating layer 2e melted when the electrolytic tin plating layer 2e is reflowed becomes the base copper foil 2a and the first electrolytic copper plating. It is possible to effectively prevent entry into the interface with the layer 2b. Therefore, it is possible to provide the wiring board 10 capable of maintaining good bonding strength between the base copper foil 2a forming the wiring conductor 2 and the first electrolytic copper plating layer 2b.

DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 2 Wiring conductor 2a Base copper foil 2b 1st electrolytic copper plating layer 2d 2nd electrolytic copper plating layer 2e Tin plating layer 3 Solder resist layer

Claims (2)

  A wiring conductor comprising an insulating substrate, a base copper foil deposited on the insulating substrate, a first electrolytic copper plating layer deposited on the base copper foil, and a coating on the insulating substrate and the wiring conductor; A solder resist layer that exposes a side surface and a top surface of a part of the wiring conductor, wherein the side surface and the top surface are coated with a tin plating layer, and the wiring conductor comprises: The wiring board, wherein the side surface and the upper surface are covered with a second electrolytic copper plating layer, and the surface of the second electrolytic copper plating layer is covered with the tin plating layer.   A step of depositing a base copper foil on an insulating substrate; a step of depositing a first electrolytic copper plating layer on a wiring conductor pattern on the base copper foil; and a step of covering with the first electrolytic copper plating layer. Forming a wiring conductor composed of the base copper foil and the first electrolytic copper plating layer by etching away the base copper foil that has not been etched; A method for manufacturing a wiring board, comprising: a step of covering with a copper plating layer; and a step of covering an exposed surface of the second electrolytic copper plating layer with a tin plating layer.

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