JP2014060424A - Back-illuminated solid-state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a back-illuminated solid-state image sensor which is capable of improving image quality by suppressing image deterioration due to an etalon phenomenon.SOLUTION: The back-illuminated solid-state image sensor includes a semiconductor substrate 4 having a light incident surface on the back side and a plurality of charge transfer electrodes 2 provided on a light detection surface opposite to the light incident surface of the semiconductor substrate 4. A plurality of openings OP for light transmission are formed between adjacent charge transfer electrodes 2. The openings OP are arranged in a staggered manner along a charge transfer direction.

Description

  The present invention relates to a back-illuminated solid-state imaging device.

  BT (Back-illuminated Thinning) -CCD is known as a back-illuminated solid-state imaging device in which a light incident surface side of a substrate is thinned. According to Non-Patent Document 1, interference (etalon phenomenon) occurs between the detected light incident on the BT-CCD and the light reflected by the detection-side surface of the BT-CCD, It affects the detection characteristics in the near infrared region. In order to suppress this etalon phenomenon, in this document, the thickness of the photosensitive region is increased, and an antireflection film is further provided in the photosensitive region.

"Etaloning in Back-Illuminated CCDs", published by ROPER SCIENTIFIC TECHINICAL NOTE (ROPER SCIENTIFIC Technical Note), ROPER SCIENTIFIC (2000). 7

  However, the conventional BT-CCD solution sacrifices the inherent advantage of BT-CCD, which is to improve detection sensitivity by thinning the film, and has not led to an essential improvement in image quality.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a back-illuminated solid-state imaging device capable of suppressing image deterioration due to an etalon phenomenon and improving image quality.

  A back-illuminated solid-state image sensor according to a first aspect of the present invention is the back-illuminated solid-state image sensor. The back-illuminated solid-state image sensor includes a semiconductor substrate and an opening formed between the adjacent semiconductor substrates. And charge transfer electrodes arranged in a staggered pattern along the charge transfer direction.

  A back-illuminated solid-state imaging device according to a second aspect of the present invention is a semiconductor substrate having a light incident surface on the back surface side, and a plurality of charge transfers provided on the light detection surface of the semiconductor substrate opposite to the light incident surface. In a back-illuminated solid-state imaging device having electrodes, a plurality of light transmission openings are formed between adjacent ones of the charge transfer electrodes, and the openings are arranged in the charge transfer direction. It is arranged in a staggered pattern along.

  In a back-illuminated solid-state imaging device according to a third aspect of the invention, the semiconductor substrate has a first conductivity type semiconductor substrate, a second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate, And an insulating layer formed on the semiconductor region, the charge transfer electrode formed on the insulating layer, and a protective film formed on the charge transfer electrode.

  In the back-illuminated solid-state imaging device according to the fourth aspect of the invention, a part of the adjacent charge transfer electrode overlaps with the insulating layer serving as a spacer, and each of the adjacent charge transfer electrodes is It has a notch part recessed in a trapezoidal shape, and the opening part is defined by the notch parts of the adjacent charge transfer electrodes facing each other.

  According to the back-illuminated solid-state imaging device of the present invention, a high-quality image can be acquired.

1 is a perspective view of a back-illuminated solid-state image sensor 100 according to an embodiment. It is the bottom view which looked at the back incidence type solid imaging device 100 from the opposite side to the light incidence direction. It is a figure which shows the imaging area | region 10 and the horizontal shift register 20 which were formed in the surface side (a light incident surface (reverse side) reverse side). It is the longitudinal cross-sectional view of the said pixel which cut one pixel along XZ plane. It is a top view of the imaging region for demonstrating the structure of the charge transfer electrode 2 (mp + 1-mp + 17 ...) of a comparative example. It is BB arrow sectional drawing in the pixel shown in FIG. It is a top view of the imaging region for demonstrating the structure of the charge transfer electrode 2 (mp + 1-mp + 17 ...) which concerns on embodiment. It is BB arrow sectional drawing in the pixel shown in FIG. It is a top view of the imaging region for demonstrating the structure of the charge transfer electrode 2 (mp + 1-mp + 17 ...) which concerns on embodiment. FIG. 10 is a cross-sectional view taken along arrow B1-B1 in the pixel shown in FIG. 9. FIG. 10 is a B2-B2 arrow sectional view of the pixel shown in FIG. 9. It is a top view of the imaging region for demonstrating the structure of the charge transfer electrode 2 (mp + 1-mp + 17 ...) which concerns on embodiment. It is a top view of the imaging region for demonstrating the structure of the charge transfer electrode 2 (mp + 1-mp + 17 ...) which concerns on embodiment.

  Hereinafter, the back-illuminated solid-state imaging device 100 according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is a perspective view of a back-illuminated solid-state imaging device 100 according to an embodiment. In the figure, for convenience of explanation, a three-dimensional orthogonal coordinate system including an X axis, a Y axis, and a Z axis orthogonal to each other is shown.

  The back-illuminated solid-state imaging device 100 is a BT-CCD (charge coupled device) in which the back side of a semiconductor substrate is thinned by etching with a KOH aqueous solution or the like, and a recessed portion TD is formed in the etched central region. There is a thick frame around the TD. Side surfaces 102 a, 102 b, 102 c, 102 d of the recess TD are inclined with an obtuse angle with respect to the bottom surface 101. Note that the frame portion may be removed by etching to form a back-illuminated solid-state imaging device in which the entire region is thinned.

  A thinned central region of the semiconductor substrate is a light sensitive region (imaging region), and a light image L from an object enters the light sensitive region along the negative direction of the Z axis. The bottom surface 101 of the recess TD of the semiconductor substrate constitutes a light incident surface. In the photosensitive region, an imaging CCD composed of a plurality of vertical shift registers is formed as a pixel.

  FIG. 2 is a bottom view of the back-illuminated solid-state imaging device 100 as viewed from the side opposite to the light incident direction. An imaging region 10 is formed in a region corresponding to the bottom surface 101 of the thinned semiconductor substrate. The light image incident on the imaging region 10 is converted into a two-dimensional charge image, and this charge is transferred along the negative direction of the Y axis. A horizontal shift register 20 is provided at the end of the imaging region 10 in the charge transfer direction, and the charges of each pixel transferred in the vertical direction are sequentially transferred along the X-axis direction. A plurality of electrode pads are provided on the frame portion of the back-illuminated solid-state imaging device 100.

  The main electrode pads are electrode pads P1V and P2V for applying a two-phase transfer voltage to the charge transfer electrode, electrode pads P1H and P2H for applying a two-phase transfer voltage to the charge transfer electrode, and the semiconductor substrate to ground. The electrode pad SS for connecting to the electrode pad, the electrode pad SG, OG, OD, RG, RD for reading out the charges transferred in the horizontal direction, and the output can be taken out from the electrode pad OS.

  Other electrode pads may be provided as appropriate according to specifications. In this example, the electrode pad TG for functioning the charge transfer gate to the horizontal shift register 20 and the electrode pad ISV for inputting a test signal are used. , ISH, and electrode pads 1G1V, 1G2V, 1G1H, 1G2H for functioning the charge transfer gates of these test signals. Known CCD charge transfer methods include a frame transfer method, an interline transfer method, and a full frame transfer method. Many such CCD structures are known and are not particularly limited. As an example, a full frame transfer CCD will be described.

  FIG. 3 is a diagram illustrating the imaging region 10 and the horizontal shift register 20 formed on the front surface side (the side opposite to the light incident surface (back surface)). This figure is a schematic diagram, and the shape of each transfer electrode extending in the X-axis direction is a rectangle, and there is a gap between them. A part or all of them are overlapped, and the shape thereof is set so as to have an opening for light transmission as will be described later.

The imaging region 10 is formed by arranging a plurality of vertical shift registers n _{1 to} n _N (N is an integer of 2 or more), that is, vertical charge transfer CCDs. Note that the actual imaging area is the central area of the imaging area 10, and surrounding pixels are shielded from light as necessary. The pixels in the vertical direction are arranged along the Y axis, and each of the charge transfer electrodes m _{1 to} m _M (M is an integer of 2 or more) extends along the X axis. The charge transfer electrodes _m 1 ~m _M, the electrode pads P1V, transfer voltage of two phases is applied from the P2V, charge transfer electrodes _m 1 ~m _M charges accumulated in the semiconductor region directly below the vertical direction (Y-axis negative Direction). In addition, between the vertical CCD channels (semiconductor charge transfer regions) constituting the vertical shift registers n _{1 to} n _N , an isolation region having a conductivity type opposite to the charge flowing through the CCD channel is formed. The isolation region suppresses mutual mixing of charges from different pixel columns.

The final position of the vertical charge transfer is provided with the transfer gate electrodes m _T, depending on the voltage from the electrode pad TG, horizontal shift register via the potential immediately under the transfer gate electrodes m _T from the imaging region 10 Charges will flow into 20. In the horizontal shift register 20, horizontal charge transfer CCDs that transfer charges in the horizontal direction (X-axis positive direction) are aligned along the X-axis, and are disposed on the semiconductor charge transfer region HSR extending in the X-axis direction. , Charge transfer electrodes h _{1 to} h _K (K is an integer of 2 or more) are provided, and these charge transfer electrodes are arranged along the X-axis direction.

The charge transfer electrodes _h 1 to h _K, the electrode pads P1H, transfer voltage of two phases is applied from the P2H, the horizontal direction (X-axis charges accumulated in the semiconductor region directly below the charge transfer electrodes _h 1 to h _K Direction). A charge readout circuit is provided at the final position of the X-axis charge transfer. The charge readout circuit includes a signal gate region located at the end of a horizontal shift register connected to the electrode pad SG. Next to this signal the gate region, the floating diffusion region FD is provided via a transistor to Q ₁ MOS-FET structure. Floating diffusion region FD is connected to the reset drain electrode pads RD via the reset transistor Q _2, also connected to the gate electrode of the output transistor Q _3. One terminal of the output transistor Q ₃ are connected to the overflow drain electrode pads OD, other constitutes an output terminal OS. A load resistor R is connected to the output terminal OS. The gate electrode of the transistor Q ₂ is connected to the reset gate electrode pad RG.

  An appropriate high level potential is applied to the electrode pads OG, OD, and RD throughout. At the time of signal reading, the electrode pad SG and the electrode pad RG are set to high level, the potential of the floating diffusion region FD is set to the reset potential of the reset electrode pad RD, and then the electrode pad RG is set to low level. The output signal becomes a floating level. Next, by setting the electrode pad SG to a low level, the signal charge temporarily stored in the signal gate region flows into the floating diffusion region FD, and the output signal taken out from the electrode pad OS is stored in the amount of stored charge. The signal level according to.

The remaining configuration is for performing a test operation. A test signal is input from the electrode pads ISV and ISH, and an appropriate potential is applied to the electrode pads IG1V, IG2V, IG1H, and IG2H, and the test operation is performed. Electrode pads ISV is connected to the electrode _{m V} which is electrically connected to the semiconductor substrate, the electrode pads IG1V, IG2V is connected to the gate electrode _{m G1, m G2} provided via an insulating film on a CCD channel ing. If an appropriate signal is input to these signals and an output different from the normal signal is obtained, it is determined that the signal is abnormal.

Note that the intersection region between the transfer electrodes _{m M} of each CCD channel _{n N} and this number in FIG. 3, constituting each pixel (reference pixel PIXEL in Figure 7).

  FIG. 4 is a vertical cross-sectional view of a pixel obtained by cutting one pixel along the XZ plane.

Incident light L enters from the back surface (light incident surface) of the semiconductor substrate. That is, the semiconductor substrate has a light incident surface. This pixel includes a protective film 1, a charge transfer electrode 2 (= charge transfer electrodes m _{1 to} m _M shown in FIG. 3), an insulating layer 3, a semiconductor substrate 4 made of Si, and an antireflection film in order from the substrate surface side. 5 is provided. The semiconductor substrate 4 includes a P-type semiconductor substrate 4C, an N-type semiconductor region (layer) 4A formed on the P-type semiconductor substrate 4C, an accumulation layer 4D formed on the back side of the P-type semiconductor substrate 4C, and a CCD. And isolation regions 4B formed on both sides of the channel. The P-type semiconductor substrate 4C and the N-type semiconductor region 4A are in contact with each other to form a PN junction, thereby forming a buried channel CCD. The N-type semiconductor region 4A (PN junction) can be omitted. In this case, the CCD functions as a surface channel CCD.

In this example, the protective film 1 is made of BPSG (Boro-Phospho Silicate Glass), the charge transfer electrode 2 is made of polysilicon, the insulating layer 3 is made of SiO ₂ , and the isolation region 4B and the accumulation layer 4D are both high. It is made of Si to which a P-type impurity having a concentration is added. In the pixel, the conductivity type in the semiconductor functions even if the P-type and the N-type (first conductivity type / second conductivity type) are interchanged. The high concentration means that the impurity concentration is higher than the impurity concentration of the P-type semiconductor substrate 4C, and is preferably a concentration of 1 × 19 cm ³ or more.

  Here, a manufacturing method of the solid-state imaging device having the above structure will be described.

First, as shown in FIG. 4, a P-type semiconductor substrate 4C is prepared. The semiconductor substrate 4C is thinned. Next, a mask is formed by patterning in a region corresponding to a pixel, and a P-type impurity is added to the substrate surface using an ion implantation method or a diffusion method to form an isolation region 4B, and then thermal oxidation is performed. Thus, the insulating layer 3 is formed on the isolation region 4B. Next, when the mask is removed and thermal oxidation is performed, the insulating layer 3 made of SiO ₂ is also formed on the photodetecting surface of silicon.

  N-type impurities are ion-implanted into the semiconductor substrate through the insulating layer 3 to form an N-type semiconductor region 4A immediately below the insulating layer 3. Since the initial semiconductor substrate is a P-type semiconductor substrate 4C, a PN junction is formed between them. Next, a charge transfer electrode 2 made of a metal such as Al or polysilicon is formed on the insulating layer 3, and a protective film 1 made of BPSG is formed thereon.

Next, as shown in FIG. 4, a high concentration P-type impurity is added to the back side of the semiconductor substrate 4 to form an accumulation layer 4D, and subsequently, an antireflection film 5 is formed on the accumulation layer 4D. To do. The antireflection film 5 is made of a dielectric multilayer film, and is formed, for example, by laminating Si and Ge oxides. Although the above-described back-illuminated solid-state imaging device is completed through the above steps, in reality, since the adjacent charge transfer electrodes 2 overlap each other, SiO ₂ is formed after the formation of the lower charge transfer electrode _2. An insulating layer serving as a spacer is formed so as to be continuous with the original insulating layer 3, and an upper charge transfer electrode 2 is formed through the spacer. Since these forming processes are different, the alignment accuracy of the mask for forming the lower-layer (odd-numbered row) charge transfer electrode 2 and the mask for forming the upper-layer (even-numbered row) charge transfer electrode 2 is high. Required.

  Next, the structure of the charge transfer electrode will be described. First, a conventional electrode structure as a comparative example will be described.

FIG. 5 is a plan view of an imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17...) Of the comparative example, and a plurality of charge transfer electrodes extending in the X-axis direction and in the Y-axis direction. An extended CCD channel n _N (nk + 1 to nk + 4) is shown (where p and k are integers). A region surrounded by a dotted line PIXEL in the figure corresponds to one pixel. The cross-sectional view along the line AA in this pixel is the same as that shown in FIG.

  Further, a cross-sectional view taken along the line BB in this pixel is shown in FIG. A low-concentration N-type semiconductor region 4A ′ is formed immediately below the upper-layer electrodes mp + 6, mp + 8, and mp + 10. Low concentration means an impurity concentration lower than that of the N-type semiconductor region 4A. The N-type semiconductor region 4A and the low-concentration N-type semiconductor region (layer) 4A ′ form a surface layer of the P-type semiconductor substrate 4C, and the low-concentration N-type semiconductor is interposed between the adjacent N-type semiconductor regions 4A. Region 4A 'is located. This low-concentration N-type semiconductor region 4A 'is formed so as to have an impurity concentration lower than that of the N-type semiconductor region 4A. As a method for controlling the impurity concentration, there are a method in which the formation time and the amount of impurities added are different, a method in which the thickness of the insulating layer 3 is increased on the low concentration side, and ion implantation is performed through this.

  Next, the structure of the charge transfer electrode according to the embodiment will be described. The structure of this charge transfer electrode is a part of the comparative example that is cut away and constitutes a so-called open gate structure.

FIG. 7 is a plan view of the imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17...) According to the embodiment, and a plurality of charge transfer electrodes extending in the X-axis direction and the Y-axis CCD channels n _N (nk + 1 to nk + 4) extending in the direction are shown (where p and k are integers). A region surrounded by a dotted line PIXEL in the figure corresponds to one pixel. The cross-sectional view along the line AA in this pixel is the same as that shown in FIG.

  Further, a cross-sectional view taken along the line BB in this pixel is shown in FIG. A low-concentration N-type semiconductor region 4A ′ is formed immediately below the upper-layer electrodes mp + 6, mp + 8, and mp + 10. This low-concentration N-type semiconductor region 4A 'is formed so as to have an impurity concentration lower than that of the N-type semiconductor region 4A. The method for controlling the impurity concentration is as described above.

  A part of the charge transfer electrodes 2 (mp + 1 to mp + 17...) Adjacent to each other along the charge transfer direction (Y axis) overlaps, and in forming the charge transfer electrodes mp + 7, mp + 9, mp + 11. After the formation, upper charge transfer electrodes mp + 6, mp + 8, mp + 10... Are formed through the insulating layer 3 serving as a spacer.

  Here, as shown in FIG. 7, a plurality of light transmission openings OP are formed between adjacent ones of the charge transfer electrodes 2 (mp + 1 to mp + 17...) Along the Y-axis direction. Yes. Hereinafter, the structure of the charge transfer electrode will be described in detail. In the following description of the charge transfer electrode, the side not mentioned is a straight line parallel to the X axis. One side of the charge transfer electrode mp + 7 has a notch that is periodically recessed in a trapezoidal shape in the positive direction of the Y axis, and one side of the charge transfer electrode mp + 8 adjacent thereto has a period in the negative direction of the Y axis. In particular, it has a notch that is recessed in a trapezoidal shape, and the opening OP is defined by the two notches facing each other.

  In the same relationship as this, an opening OP is formed between notches of the adjacent charge transfer electrode mp + 9 and charge transfer electrode mp + 10. These four charge transfer electrodes mp + 7 to mp + 10 are included in the same pixel PIXEL. As shown in FIG. 8, a high-concentration P-type semiconductor region 4C ′ is formed in a region immediately below the opening OP. Therefore, in such a region, no PN junction is formed and carriers are not accumulated.

  The light L incident on the back surface is detected on the light detection surface side, but in the solid-state imaging device of the present embodiment, part of the light used for light detection is transmitted to the outside through the opening OP. Thereby, since there is no charge transfer electrode in the opening OP, reflection of incident light is suppressed, and interference between incident light and reflected light is suppressed. Therefore, image degradation due to the etalon phenomenon is suppressed, and image quality is improved.

  Further, as shown in FIG. 7, the plurality of openings OP are arranged in alignment along the charge transfer direction (Y-axis direction). Thus, when the openings OP formed between the adjacent charge transfer electrodes are aligned, the configuration is simple. However, in this structure, alignment accuracy at the time of manufacturing the lower and upper charge transfer electrodes is required, and when the alignment accuracy is low, the area of the opening OP in the pixel for each column is different. There is room for further improvement such as variations in characteristics. There may be some fixed noise patterns in the etalon characteristics and dark characteristics.

  Therefore, an embodiment in which the arrangement of the openings OP is further improved will be described next.

FIG. 9 is a plan view of an imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17...) According to this embodiment, and a plurality of charge transfer electrodes extending in the X-axis direction and the Y-axis CCD channels n _N (nk + 1 to nk + 4) extending in the direction are shown (where p and k are integers). A region surrounded by a dotted line PIXEL in the figure corresponds to one pixel. The cross-sectional view along the line AA in this pixel is the same as that shown in FIG.

  Further, a B1-B1 arrow sectional view of this pixel is shown in FIG. 10, and a B2-B2 arrow sectional view is shown in FIG. A low-concentration N-type semiconductor region 4A ′ is formed immediately below the upper-layer electrodes mp + 6, mp + 8, and mp + 10. This low-concentration N-type semiconductor region 4A 'is formed so as to have an impurity concentration lower than that of the N-type semiconductor region 4A. The method for controlling the impurity concentration is as described above.

  A part of the charge transfer electrodes 2 (mp + 1 to mp + 17...) Adjacent to each other along the charge transfer direction (Y axis) overlaps, and in forming the charge transfer electrodes mp + 7, mp + 9, mp + 11. After the formation, upper charge transfer electrodes mp + 6, mp + 8, mp + 10... Are formed through the insulating layer 3 serving as a spacer.

  As in the structure shown in FIG. 7, in the structure of FIG. 9, a plurality of light transmission electrodes 2 (mp + 1 to mp + 17...) Adjacent to each other along the Y-axis direction are arranged. An opening OP is formed. One side of the charge transfer electrode mp + 7 has a notch that is periodically recessed in a trapezoidal shape in the positive direction of the Y axis, and one side of the charge transfer electrode mp + 8 adjacent thereto has a period in the negative direction of the Y axis. In particular, it has a notch that is recessed in a trapezoidal shape, and the opening OP is defined by the two notches facing each other. The period along the X-axis direction of the formation position of these notches is the same.

  In the same relationship as this, an opening OP is formed between notches of the adjacent charge transfer electrode mp + 9 and charge transfer electrode mp + 10. Although the period along the X-axis direction of the formation position of these notches is the same, the formation position of the notches of the charge transfer electrodes mp + 7 and mp + 8 is, in other words, the formation position along the X-axis direction. The phase is inverted. These four charge transfer electrodes mp + 7 to mp + 10 are included in the same pixel PIXEL. As shown in FIG. 10, a high-concentration P-type semiconductor region 4C ′ is formed in the region immediately below the opening OP. Therefore, in such a region, no PN junction is formed and carriers are not accumulated.

  Here, as shown in FIG. 9, the openings OP are arranged in a staggered manner along the charge transfer direction (Y-axis direction). That is, the openings OP are arranged alternately. As described above, the odd-numbered charge transfer electrodes (mp + 1, mp + 3, mp + 5, mp + 7...) Located in the lower layer are simultaneously formed, and the even-numbered rows (mp + 2, mp + 4, mp + 6, mp + 8,. The charge transfer electrode (1) is formed at the same time after the formation of the lower electrode. Therefore, when the staggered opening arrangement as in the present embodiment is adopted, the charge transfer electrodes in the even-numbered rows are shifted in the horizontal direction during manufacturing, for example, an opening between the charge transfer electrode mp + 7 and the charge transfer electrode mp + 8. When the area of the part OP increases, the area of the opening OP between the charge transfer electrode mp + 9 and the charge transfer electrode mp + 10 decreases. In other words, this structure has a high tolerance of alignment accuracy, and the amount of transmitted light for each pixel is equal, and has the advantage of uniform characteristics, and the occurrence of fixed noise patterns is also suppressed.

  Next, an embodiment in which the structure of the charge transfer electrode is further modified will be described.

FIG. 12 is a plan view of an imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17...) According to this embodiment, and a plurality of charge transfer electrodes extending in the X-axis direction and the Y-axis CCD channels n _N (nk + 1 to nk + 4) extending in the direction are shown (where p and k are integers). A region surrounded by a dotted line PIXEL in the figure corresponds to one pixel. The only difference from the above embodiment is the shape and arrangement of the charge transfer electrodes 2 (mp + 1 to mp + 17...). Other configurations are the same as those described above except that a P-type impurity is added immediately below the opening OP to form a P-type semiconductor region 4C ′ as shown in FIG. 8, FIG. 10, or FIG. This is the same as the embodiment. Further, the cross-sectional structure of the pixel cut along a plane perpendicular to the charge transfer direction (Y axis) and not passing through the opening is the same as that shown in FIG.

  The charge transfer electrode mp + 7 has a first shape, the charge transfer electrode mp + 8 has a second shape, the charge transfer electrode mp + 9 has a third shape, and the charge transfer electrode p + 4 has a fourth shape. These first to fourth shapes are all different from each other, and these four shapes are repeated along the charge transfer direction for each pixel.

  The first shape of the charge transfer electrode mp + 7 has a cutout portion in which one side is periodically recessed in a trapezoidal shape in the positive direction of the Y-axis.

  The second shape of the charge transfer electrode mp + 8 has a cutout portion with one side periodically recessed in a trapezoidal shape in the negative Y-axis direction, but the cycle is the same as that of the charge transfer electrode mp + 7. Thus, the length of the innermost side of the notch is different from that of the charge transfer electrode mp + 7. The cutout portions of the charge transfer electrode mp + 7 and the charge transfer electrode mp + 8 face each other to form an opening OP of the first pattern.

  The third shape of the charge transfer electrode mp + 9 has a cutout portion whose one side is periodically recessed in a trapezoidal shape or a triangular shape in the positive direction of the Y-axis. In the charge transfer electrode mp + 9, the number of notches per unit length in the X-axis direction is larger than the number of notches in the charge transfer electrodes mp + 7 and mp + 8. The trapezoidal cutouts and the triangular cutouts are alternately formed along the X axis.

  The fourth shape of the charge transfer electrode mp + 10 has a cutout portion with one side periodically recessed in a trapezoidal shape in the negative Y-axis direction, but the cycle is the same as that of the charge transfer electrode mp + 9. Thus, the length of the innermost side of the notch is longer than the length of the innermost side of the trapezoidal notch in the charge transfer electrode mp + 9. The cutout portions of the charge transfer electrode mp + 9 and the charge transfer electrode mp + 10 face each other to form the opening OP of the second pattern. Further, the first pattern and the second pattern of the opening OP are different from each other.

  In such a structure, since the shape of the charge transfer electrode and the pattern of the opening are different, the randomness of the opening OP is high. For example, even when the charge transfer electrodes mp + 8 and mp + 10 are laterally displaced, Variations in the opening area can be suppressed.

  The general shape of the charge transfer electrode is such that when p is an integer greater than or equal to 0, the charge transfer electrode in the (p + 1) th row has the first shape, and the charge transfer electrode in the (p + 2) th row has the second shape. , The charge transfer electrode in the (p + 3) th row has a third shape, and the charge transfer electrode in the (p + 4) th row has a fourth shape.

FIG. 13 is a plan view of an imaging region for explaining the structure of charge transfer electrodes 2 (mp + 1 to mp + 17...) According to another embodiment, and a plurality of charge transfer electrodes extending in the X-axis direction, and Y A CCD channel n _N (nk + 1 to nk + 4) extending in the axial direction is shown (where p and k are integers). A region surrounded by a dotted line PIXEL in the figure corresponds to one pixel. The difference from the comparative example is that the charge transfer electrodes 2 (mp + 1 to mp + 17...) Linearly extending along the X axis each have a plurality of openings OP. A P-type impurity is added immediately below, and a P-type semiconductor region 4C ′ as shown in FIG. 8, FIG. 10, or FIG. 11 is formed immediately below the opening OP. Other configurations are the same as those of the above-described comparative example. Further, the cross-sectional structure of the pixel cut along a plane perpendicular to the charge transfer direction (Y axis) and not passing through the opening is the same as that shown in FIG. Note that the number and arrangement of the openings OP in each pixel are the same.

  As described above, in the solid-state imaging device according to the present embodiment, a plurality of light transmission openings OP are formed in each charge transfer electrode 2 (mp + 1 to mp + 17...). The portion is transmitted to the outside through the opening OP. Thereby, since there is no charge transfer electrode in the opening OP, reflection of incident light is suppressed, and interference between incident light and reflected light is suppressed. Therefore, image degradation due to the etalon phenomenon is suppressed, and image quality is improved.

  In addition, this invention is not limited to the said embodiment, For example, it is also possible to use compound semiconductors, such as GaAs and GaN, as a semiconductor material.

  As described above, the above-described back-illuminated solid-state imaging device includes a semiconductor substrate having a light incident surface on the back surface side, and a plurality of charges provided on the light detection surface opposite to the light incident surface of the semiconductor substrate. A back-illuminated solid-state imaging device including a transfer electrode is characterized in that a plurality of light transmission openings are formed between adjacent charge transfer electrodes.

  The light incident on the back surface is detected on the light detection surface side. However, in the solid-state imaging device of the present invention, a part of the light used for light detection is originally transmitted to the outside through the opening. Thereby, since there is no charge transfer electrode in the opening, reflection is suppressed, and interference between incident light and reflected light is suppressed. Therefore, image degradation due to the etalon phenomenon is suppressed, and image quality is improved.

  The openings are preferably arranged in alignment along the charge transfer direction. As described above, when the openings formed between the adjacent charge transfer electrodes are aligned, the reflected light is suppressed although the configuration is simple. However, in this structure, alignment accuracy at the time of manufacturing the charge transfer electrode is required, and when the alignment accuracy is low, the area of the opening in the pixel for each column is different, and the characteristics of each pixel vary. There is room for further improvement.

  Therefore, the openings are preferably arranged in a staggered manner along the charge transfer direction. That is, the openings are arranged alternately. When such a staggered opening arrangement is employed, the charge transfer electrodes in the odd-numbered rows (p + 1 row and p + 3 row (p is an integer of 0 or more)) are formed at the same time, and the even-numbered rows (p + 2). If the charge transfer electrodes of the (row) and (p + 4) rows are formed separately at the same time, the charge transfer electrodes of the even-numbered rows are shifted laterally during manufacturing, and an opening between the charge transfer electrodes of the (p + 1) th and p + 2th rows is formed. When the partial area increases, the opening area between the charge transfer electrodes in the p + 3 and p + 4 rows decreases. That is, this structure has a high tolerance of alignment accuracy, and the amount of transmitted light for each pixel becomes equal, and the characteristics become uniform.

  Regarding the shape and arrangement of the charge transfer electrode, the charge transfer electrode in the (p + 1) th row has the first shape, the charge transfer electrode in the (p + 2) th row has the second shape, and the charge transfer electrode in the (p + 3) th row has the first shape. The charge transfer electrodes in the p + 4th row have a fourth shape, the first to fourth shapes are all different from each other, and the first to fourth charge transfer electrodes are between the p + 1th row and the p + 2th row. A pattern opening is formed, and a second pattern opening is formed between the charge transfer electrodes in the p + 3 and p + 4 rows, and the first and second patterns are preferably different from each other.

  In such a structure, since the shape of the charge transfer electrode and the pattern of the opening are different, the randomness of the opening is high. For example, the charge transfer electrodes in the p + 2 and p + 4 rows are laterally displaced. Even in this case, fluctuations in the opening area can be suppressed.

  The back-illuminated solid-state imaging device includes a semiconductor substrate having a light incident surface on the back surface side, and a plurality of charge transfer electrodes provided on a light detection surface opposite to the light incident surface of the semiconductor substrate. The back-illuminated solid-state imaging device is characterized in that a plurality of light transmission openings are formed in each charge transfer electrode.

  Even in the case of this structure, a part of light used for light detection is transmitted to the outside through the opening. Thereby, since there is no charge transfer electrode in the opening, reflection is suppressed, and interference between incident light and reflected light is suppressed. Therefore, image degradation due to the etalon phenomenon is suppressed, and image quality is improved.

  DESCRIPTION OF SYMBOLS 100 ... Back-illuminated solid-state image sensor, L ... Incident light, 1 ... Protective film, 2 ... Charge transfer electrode, 3 ... Insulating layer, 4 ... Semiconductor substrate, 5 ... Antireflection film, 4A ... N type semiconductor region (layer) 4B: Isolation region, 4C: P-type semiconductor substrate, 4D: Accumulation layer.

Claims (4)

In the back-illuminated solid-state image sensor,
A semiconductor substrate;
Charge transfer electrodes provided adjacent to each other on the semiconductor substrate and formed between adjacent ones are arranged in a staggered manner along the charge transfer direction; and
A back-illuminated solid-state imaging device. A semiconductor substrate having a light incident surface on the back side;
A plurality of charge transfer electrodes provided on a light detection surface opposite to the light incident surface of the semiconductor substrate;
In a back-illuminated solid-state imaging device comprising:
A plurality of light transmission openings are formed between adjacent ones of the charge transfer electrodes,
The back-illuminated solid-state imaging device, wherein the openings are arranged in a staggered manner along the charge transfer direction. The semiconductor substrate is
A first conductivity type semiconductor substrate;
A second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate;
With
An insulating layer formed on the semiconductor region;
The charge transfer electrode formed on the insulating layer;
A protective film formed on the charge transfer electrode;
The back-illuminated solid-state imaging device according to claim 1, further comprising: A portion of the adjacent charge transfer electrode overlaps with the insulating layer serving as a spacer,
Each of the adjacent charge transfer electrodes has a notch recessed in a trapezoidal shape, and the notch of the adjacent charge transfer electrode is opposed to define the opening. ,
The back-illuminated solid-state imaging device according to claim 3.

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