WO2011155182A1 - Solid-state imaging element - Google Patents

Solid-state imaging element Download PDF

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Publication number
WO2011155182A1
WO2011155182A1 PCT/JP2011/003202 JP2011003202W WO2011155182A1 WO 2011155182 A1 WO2011155182 A1 WO 2011155182A1 JP 2011003202 W JP2011003202 W JP 2011003202W WO 2011155182 A1 WO2011155182 A1 WO 2011155182A1
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Prior art keywords
epitaxial layer
layer
photoelectric conversion
solid
state imaging
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PCT/JP2011/003202
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French (fr)
Japanese (ja)
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直人 山田
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パナソニック株式会社
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Publication of WO2011155182A1 publication Critical patent/WO2011155182A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers
    • H01L27/14843—Interline transfer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Definitions

  • the present invention relates to a solid-state imaging device, and more particularly to an interlaced type CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device having a light shielding film.
  • CMOS Complementary Metal Oxide Semiconductor
  • Patent Document 1 the imaging region is composed of a photoelectric conversion region, a charge transfer electrode, a charge transfer region, a charge readout electrode, a charge readout region, an element isolation region, and the like.
  • FIG. 7A is a plan layout view of a general solid-state image sensor 101
  • FIG. 7B is a cross-sectional view (cross-sectional view taken along line A-A ′ in FIG. 7A) showing a schematic configuration of the solid-state image sensor 101.
  • epitaxial layers 111b and 111c are formed on a semiconductor substrate 111a, and a photoelectric conversion region 112 is formed in the epitaxial layer 111c.
  • the photoelectric conversion region 112 is composed of a hole accumulation layer 140 made of a p + layer formed in an upper layer, and an n + type diffusion layer 141 and a p well 120 formed in the lower layer.
  • the n + type diffusion layer 141 in the photoelectric conversion region 112 is formed up to a deep position of the epitaxial layer 111c in consideration of the formation of the hole accumulation layer 140 on the surface of the epitaxial layer 111c.
  • the n + -type diffusion layer 141 is not formed up to a position deeper than the film thickness of the epitaxial layer 111c.
  • a vertical transfer unit (vertical register) 116 is formed as a charge transfer region via a read gate (charge read region) 115.
  • the vertical transfer unit 116 includes an n-type layer 142 in the upper layer and a p-type layer 118a in the lower layer. Further, a p-type layer 118b constituting a pixel isolation region 118 that electrically isolates the pixel region (photoelectric conversion region 112) from other pixel regions in the horizontal direction is formed adjacent to the vertical transfer unit 116. .
  • a vertical transfer unit 116 of a pixel (unit cell) including another photoelectric conversion region 112 adjacent to the photoelectric conversion region 112 is formed via a p-type layer 118b.
  • a gate electrode 122 serving as a charge read electrode and a charge transfer electrode is formed via an insulating film 121 serving as a gate oxide film.
  • a light shielding film 133 having an opening 134 provided on the photoelectric conversion region 112 is formed via an interlayer insulating film.
  • An antireflection film 132 is formed in the opening 134, and an interlayer insulating film 131 is formed on the light shielding film 133.
  • FIGS. 7C and 7D are cross-sectional views for explaining a method for forming the solid-state imaging device 101 having the structure of FIGS. 7A and 7B.
  • a p-well 120 is formed in a substrate 111 composed of a semiconductor substrate 111a and epitaxial layers 111b and 111c. Thereafter, a protective film 160 is formed on the surface of the epitaxial layer 111c, a resist film 150 is formed by a lithography technique, and then an opening 151 is formed in the resist film 150.
  • the first conductivity type (n-type) of the photoelectric conversion region 112 is formed on the surface of the epitaxial layer 111c by an existing impurity doping technique (for example, ion implantation method) using the resist film 150 as a mask.
  • An island-like n + -type diffusion layer 141 as a region is formed.
  • the n + -type diffusion layer 141 is formed to a depth of 2 to 4 ⁇ m. The depth to be formed is determined in consideration of up to which range the light on the long wavelength side is photoelectrically converted.
  • ⁇ 550 nm
  • ⁇ 550 nm
  • a resist mask is formed each time by lithography technique and impurity doping technique, and the readout gate 115 having the opposite conductivity type in the photoelectric conversion region 112 (n + type diffusion layer 141), vertical transfer A p-type layer 118 a of the part 116 and a p-type layer 118 b of the pixel isolation region 118 are formed.
  • the lithography technique requires a high aspect ratio resist (for example, a resist film thickness of 6 ⁇ m or more and an aspect ratio of 15 or more) that prevents impurity doping by the ion implantation method. As a result, fine processing variations are likely to occur, and it is difficult to form the photoelectric conversion region 112 with a certain form with high accuracy.
  • Patent Document 1 proposes a structure having color filter groups of the same color on two adjacent pixels having different photoelectric conversion region depths for the purpose of generating an image with a wide dynamic range.
  • Patent Document 1 intends to increase sensitivity by controlling incident energy on the low illuminance side (shadow) and high illuminance side (highlight).
  • shadow low illuminance side
  • high illuminance side high light
  • An object of the present invention is to provide a solid-state imaging device capable of suppressing a decrease in sensitivity associated with a reduction in pixel size.
  • a solid-state imaging device includes a plurality of photoelectric conversion regions that photoelectrically convert incident light, a read gate for reading signal charges from the corresponding photoelectric conversion region, and the read gate by the read gate.
  • a first conductivity type second epitaxial layer formed on the first epitaxial layer, and the photoelectric conversion region is formed across the first epitaxial layer and the second epitaxial layer. It is characterized by that.
  • the first epitaxial layer is formed on the semiconductor substrate, and a part of the photoelectric conversion region is formed in an island shape by the existing lithography technique and impurity doping technique in the first epitaxial layer.
  • a second epitaxial layer is formed on the surface of the layer, and another part of the photoelectric conversion region is formed in an island shape so as to overlap with a part of the island-shaped photoelectric conversion region by the existing lithography technique and impurity doping technique.
  • the depth of the photoelectric conversion region can be arbitrarily set without using an ultra-high energy injection device, and patterning of the photoelectric conversion region can be performed without using a thick film resist having a high aspect ratio. it can. Therefore, the photoelectric conversion region in the imaging area can be processed and formed with high precision.
  • some of the plurality of photoelectric conversion regions may be formed in the second epitaxial layer without straddling the first epitaxial layer and the second epitaxial layer.
  • FIG. 1A is a plan layout diagram of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view (a cross-sectional view taken along line A-A ′ in FIG. 1A) showing a schematic configuration of the solid-state imaging device according to the embodiment.
  • FIG. 2A is a cross-sectional view showing a manufacturing process in the method for manufacturing the solid-state imaging device according to the embodiment.
  • FIG. 2B is a cross-sectional view showing a manufacturing process in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 2C is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 2D is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 2E is a cross-sectional view showing the manufacturing process in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 2F is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3A is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging device according to the embodiment.
  • FIG. 3B is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3C is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3D is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3E is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 4A is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment.
  • FIG. 4B is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment.
  • FIG. 4A is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment.
  • FIG. 4B is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to
  • FIG. 5A is a cross-sectional view showing a schematic configuration of a solid-state imaging element according to the second embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5C is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5D is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5E is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 5F is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 5G is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5H is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 5I is a cross-sectional view showing the manufacturing process in the method for manufacturing the solid-state imaging device according to the embodiment.
  • FIG. 6 is a diagram illustrating an impurity concentration distribution in the photoelectric conversion region of the solid-state imaging device.
  • FIG. 7A is a plan layout diagram of a general solid-state imaging device.
  • FIG. 7A is a plan layout diagram of a general solid-state imaging device.
  • FIG. 7B is a cross-sectional view (a cross-sectional view taken along the line A-A ′ in FIG. 7A) showing a schematic configuration of a general solid-state imaging device.
  • FIG. 7C is a cross-sectional view for explaining a general method for forming a solid-state imaging device.
  • FIG. 7D is a cross-sectional view for explaining a general method for forming a solid-state imaging element.
  • FIG. 1A is a plan layout view of the solid-state image sensor 1
  • FIG. 1B is a cross-sectional view (cross-sectional view taken along line AA ′ in FIG. 1A) showing a schematic configuration of the solid-state image sensor 1.
  • a semiconductor substrate 11a such as a silicon substrate
  • a conversion region 12 is formed.
  • the substrate 11 includes a semiconductor substrate 11a, a first epitaxial layer 11b formed on the semiconductor substrate 11a, and a second epitaxial layer 11c formed on the first epitaxial layer 11b.
  • a read gate 15 and a transfer unit 16 are formed inside.
  • each of the plurality of photoelectric conversion regions 12 is formed across the first epitaxial layer 11b and the second epitaxial layer 11c.
  • the plurality of photoelectric conversion regions 12 are arranged in a matrix (matrix).
  • the photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c is a region that photoelectrically converts incident light, and is an n-type layer (first layer) of the same conductivity type. ) 41a and n-type layer (second layer) 41b, p + -type hole accumulation layer 40 and p-type layer (p-well) 20.
  • the photoelectric conversion region 12 after the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a and the p-type layer 20 are formed, the n-type layer 41b is formed on the second epitaxial layer 11c. And the hole accumulation layer 40 is formed.
  • the n-type layer 41a is formed only on the first epitaxial layer 11b, but the n-type layer 41b is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and the n-type layer 41b is formed. It overlaps with the whole or a part of the layer 41a.
  • the n-type layer 41a and the n-type layer 41b are electrically connected.
  • the photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer, and includes n-type layers 41 a and 41 b and a p-type layer 20 in the lower layer.
  • the n-type layer 41b is formed so that the n-type layer 41a and the n-type layer 41b overlap each other when the second epitaxial layer 11c is viewed from the surface.
  • a process alignment mark used for determination is formed.
  • the film thickness of the second epitaxial layer 11c is 5 ⁇ m or less. By setting the film thickness to 5 ⁇ m or less, impurities can be injected with high accuracy and can be reliably connected to the first epitaxial layer 11b.
  • the first epitaxial layer 11b is formed with a film thickness of 3 to 5 ⁇ m, for example.
  • the second epitaxial layer 11c is formed with a film thickness of, for example, 1 to 3 ⁇ m.
  • the first epitaxial layer 11b and the second epitaxial layer 11c are formed so that their resistance values are, for example, 0.1 to 100 ⁇ ⁇ cm for an n-type layer.
  • a pixel separation region (pixel horizontal separation region) 18, that is, a readout gate (charge readout region) 15, a transfer unit (vertical transfer unit) 16 as a charge transfer region, and a p-type layer 18b. Is formed.
  • Read gate 15 is provided corresponding to each of the plurality of photoelectric conversion regions 12, and reads signal charges from the corresponding photoelectric conversion regions 12.
  • the transfer unit 16 is a transfer path for transferring the signal charges read by the read gate 15, and includes an n-type layer 42 in the upper layer and a p-type layer 18a in the lower layer.
  • a p-type layer 20 that forms a vertical overflow drain is formed below the photoelectric conversion region 12.
  • Adjacent to the transfer unit 16, a p-type layer 18b for electrically separating the pixel region from other pixel regions in the horizontal direction is formed.
  • An antireflection film 32 that prevents reflection of incident light entering the substrate 11 is formed above the hole accumulation layer 40 in the upper layer of the photoelectric conversion region 12.
  • the refractive index of the antireflection film 32 is larger than the refractive index of the substrate 11 and smaller than the refractive index of the interlayer insulating film on the antireflection film 32.
  • a gate insulating film 21 is formed on the surface of the substrate 11, and a gate electrode 22 serving as a charge readout electrode and a charge transfer electrode is formed on the gate insulating film 21.
  • the gate electrode 22 is formed with a one-layer structure, but may be formed with a two-layer structure, a three-layer structure, or a four-layer structure.
  • the gate electrode 22 is preferably formed immediately above the read gate 15 and the transfer unit 16 as shown in the figure.
  • An interlayer insulating film 31 covering the gate electrode 22 and the gate insulating film 21 is formed on the surface of the substrate 11. Further, a light shielding film 33 having an opening formed above the photoelectric conversion region 12 is formed between the interlayer insulating film 31 and the gate electrode 22 and the gate insulating film 21.
  • FIGS. 2A to 2F are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1.
  • a first conductive type first epitaxial layer 11b is formed on a semiconductor substrate 11a by a chemical vapor deposition method (for example, CVD: Chemical Vapor Deposition) at a high temperature of 1100 ° C. or higher. Form. Thereafter, a protective film 60 made of an oxide film or a nitride film is formed on the surface of the first epitaxial layer 11b with a film thickness of 5 to 50 nm, for example.
  • CVD Chemical Vapor Deposition
  • a resist film 50 in which the openings 51 are formed is formed by a lithography fluffy technique.
  • the resist film 50 has a thickness of 1 to 3 ⁇ m and an aspect ratio of 10 or less.
  • a plurality of n-type layers 41a serving as photoelectric conversion regions are formed in the first epitaxial layer 11b by an impurity doping technique (for example, ion implantation method).
  • the n-type layer 41a is formed of, for example, atoms having a large mass such as Sb that is difficult to outdope.
  • the n-type layer 41a is made to be the first epitaxial layer so that the n-type impurity concentration on the surface is less than 10 ⁇ 10 atoms / cm 3. Formed in layer 11b.
  • the protective film 60 is removed by an etching technique (for example, wet etching).
  • a second epitaxial layer 11c is formed on the surface of the first epitaxial layer 11b by, for example, chemical vapor deposition (for example, CVD) at a high temperature of 1100 ° C. or higher.
  • CVD chemical vapor deposition
  • a protective film 61 made of an oxide film or a nitride film is formed on the surface of the second epitaxial layer 11c with a film thickness of, for example, 5 to 50 nm.
  • a p-type layer (p well) 20 is formed below the n-type layer 41a to be the photoelectric conversion region 12 by a resist mask and an ion implantation method.
  • a vertical overflow drain is formed by the p-type layer 20, and an electronic shutter voltage is set by the p-type layer 20.
  • a resist film 50 having an opening 51 formed on the surface of the second epitaxial layer 11c is formed.
  • the resist film 50 has a thickness of 2 to 5 ⁇ m and an aspect ratio of 10 or less.
  • an n-type layer 41b to be the photoelectric conversion region 12 is formed in the second epitaxial layer 11c by an impurity doping technique (for example, ion implantation method).
  • a plurality of n-type layers 41b are formed so as to correspond to the n-type layer 41a, and are electrically connected to the corresponding n-type layer 41a.
  • an alignment mark formed on the surface of the first epitaxial layer 11b is used.
  • a p-type layer that electrically separates the photoelectric conversion region 12 and the transfer unit 16 between a pair of the plurality of n-type layers 41 a and 41 b, that is, between the plurality of photoelectric conversion regions 12.
  • the read gate 15 and the p-type layers 18a and 18b are formed by a lithography technique and an impurity doping technique, for example, by forming a resist mask each time.
  • the gate insulating film 21, the gate electrode 22, the antireflection film 32, and the like are formed on the surface of the second epitaxial layer 11c.
  • FIGS. 3A to 3E are cross-sectional views of the solid-state imaging device 1 showing the process of forming the alignment mark.
  • the alignment mark is formed in a region around the solid-state imaging device or a position around the semiconductor wafer. There is a mark for alignment in each manufacturing process.
  • a resist film 50 in which an opening 51 is formed is formed, and an n-type layer 41a is formed by using this.
  • a resist film (not shown) having an opening formed only in the alignment mark region is formed.
  • the surface of the first epitaxial layer 11 b and the protective film 60 above the n-type layer 41 a is covered with a resist film 50.
  • the resist film 50 is etched using the protective film 60 as a hard mask by an etching technique (for example, dry etching), and the alignment mark is transferred to the surface of the first epitaxial layer 11b.
  • the step of the alignment mark is 0.2 ⁇ m or more.
  • the surface of the first epitaxial layer 11b is exposed by removing the protective film 60 by an etching technique (for example, wet etching), and then the second epitaxial layer 11c is formed.
  • an etching technique for example, wet etching
  • the first epitaxial layer 11b formed on the semiconductor substrate 11a has the first purpose of suppressing the decrease in sensitivity due to the reduction in pixel size.
  • the island-shaped n-type layer 41a is formed, and the second island-shaped n-type layer 41b is formed on the entire surface of the n-type layer 41a or the second epitaxial layer 11c formed on the surface of the first epitaxial layer 11b. It is formed so as to overlap a part, and is realized by forming the transfer portion 16 and the read gate 15 on the surface of the second epitaxial layer 11c.
  • the photoelectric conversion region 12 is formed at the same time as each epitaxial layer, it is possible to form a fine and deep photoelectric conversion region by the existing lithography technique and impurity doping technique (for example, ion implantation method). Therefore, it is possible to improve sensitivity and dynamic range.
  • impurity doping technique for example, ion implantation method
  • the lateral size of the n-type layer 41b is smaller than that of the n-type layer 41a, and as shown in FIG. 4A, both side ends of the n-type layer 41b are n-type layers. You may be located inside the both ends of 41a. By doing in this way, the photoelectric conversion area
  • the first epitaxial layer 11b may be formed with a conductivity type opposite to that of the photoelectric conversion region 12 (n-type layer 41b).
  • FIG. 5A is a cross-sectional view showing a schematic configuration of the solid-state imaging device 1. Note that the planar layout of the solid-state imaging device 1 according to the present embodiment is the same as FIG. 1A, and FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG.
  • a first conductivity type first epitaxial layer 11b and a first conductivity type second epitaxial layer 11c on the surface of a semiconductor substrate 11a such as a silicon substrate are formed.
  • the photoelectric conversion region 12 is straddled (continuously across the first epitaxial layer 11b and the second epitaxial layer 11c across the boundary between the first epitaxial layer 11b and the second epitaxial layer 11c).
  • a photoelectric conversion region 12 is formed in each of the first epitaxial layer 11b and the second epitaxial layer 11c independently in an island shape.
  • a second pixel comprising are arranged adjacent.
  • a part of the plurality of photoelectric conversion regions 12 is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and the other part of the plurality of photoelectric conversion regions 12 is the first.
  • the first epitaxial layer 11b and the second epitaxial layer 11c are formed so as not to straddle.
  • the photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c and the first epitaxial layer 11b and the second epitaxial layer 11c were formed so as not to straddle.
  • a plurality of photoelectric conversion regions 12 are arranged in a matrix (matrix) so that the photoelectric conversion regions 12 are alternately arranged in the row direction and the column direction.
  • the photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c is a region that photoelectrically converts incident light, and is an n-type layer (first layer) of the same conductivity type. ) 41a, n-type layer (second layer) 41b, n-type layer 41c, p + -type hole accumulation layer 40, and p-type layer (p-well) 20.
  • the n-type layer 41b is formed on the second epitaxial layer 11c.
  • the n-type layer 41c and the hole accumulation layer 40 are formed.
  • the n-type layer 41a is formed on the first epitaxial layer 11b, and the n-type layer 41c is formed on the second epitaxial layer 11c.
  • the n-type layer 41b is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and overlaps the whole or a part of the n-type layer 41a.
  • the n-type layer 41a and the n-type layer 41b are electrically connected.
  • the photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer and n-type layers 41 a, 41 b and 41 c and a p-type layer 20 in the lower layer.
  • the photoelectric conversion region 12 formed without straddling the first epitaxial layer 11b and the second epitaxial layer 11c is a region for photoelectrically converting incident light, and the first epitaxial layer 11b and the second epitaxial layer.
  • the n-type layer and the p-type layer 20 formed so as to straddle the layer 11c are not included, and the n-type layer 41a, the n-type layer 41c, the p-type layer (p-well) 20a, and the hole accumulation layer 40 are included.
  • the p-type layer 20 is formed on the first epitaxial layer 11b, while the p-type layer 20a is formed on the second epitaxial layer 11c.
  • the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a is formed, and then the n-type layer 41c and the hole accumulation layer 40 are formed on the second epitaxial layer 11c. And p-type layer 20a.
  • the n-type layer 41a and the n-type layer 41c are formed so as not to straddle the first epitaxial layer 11b and the second epitaxial layer 11c, respectively, and are electrically separated.
  • the photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer, and includes n-type layers 41a and 41c and a p-type layer 20a in the lower layer.
  • the n-type layer 41b is formed so that the n-type layer 41a and the n-type layer 41b overlap each other when the second epitaxial layer 11c is viewed from the surface.
  • a process alignment mark used for determination is formed.
  • the film thickness of the second epitaxial layer 11c is 5 ⁇ m or less.
  • the first epitaxial layer 11b is formed with a film thickness of 3 to 5 ⁇ m, for example.
  • the second epitaxial layer 11c is formed with a film thickness of, for example, 1 to 3 ⁇ m.
  • the first epitaxial layer 11b and the second epitaxial layer 11c are formed so that their resistance values are, for example, 0.1 to 100 ⁇ ⁇ cm for an n-type layer.
  • a pixel separation region (pixel horizontal separation region) 18, that is, a readout gate 15, a transfer unit (vertical transfer unit) 16, and a p-type layer 18b are formed on the side of the photoelectric conversion region 12.
  • the transfer unit 16 includes an n-type layer 42 in the upper layer and p-type layers 18a and 18c in the lower layer.
  • p-type layers 20 and 20a that form a vertical overflow drain are formed under the photoelectric conversion region 12.
  • a p-type layer 18 b is formed adjacent to the transfer unit 16.
  • An antireflection film 32 that prevents reflection of incident light entering the substrate 11 is formed above the hole accumulation layer 40 in the upper layer of the photoelectric conversion region 12.
  • the refractive index of the antireflection film 32 is larger than the refractive index of the substrate and smaller than the refractive index of the interlayer insulating film on the antireflection film 32.
  • a gate insulating film 21 is formed on the surface of the substrate 11, and a gate electrode 22 serving as a charge readout electrode and a charge transfer electrode is formed on the gate insulating film 21.
  • the gate electrode 22 is formed with a one-layer structure, but may be formed with a two-layer structure, a three-layer structure, or a four-layer structure.
  • the gate electrode 22 is preferably formed immediately above the read gate 15 and the transfer unit 16 as shown in the figure.
  • An interlayer insulating film 31 covering the gate electrode 22 and the gate insulating film 21 is formed on the surface of the substrate 11. Further, a light shielding film 33 having an opening formed above the photoelectric conversion region 12 is formed between the interlayer insulating film 31 and the gate electrode 22 and the gate insulating film 21.
  • FIGS. 5B to 5I are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1.
  • FIG. 5B to 5I are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1.
  • a first conductivity type first epitaxial layer 11b is formed on a semiconductor substrate 11a by, for example, chemical vapor deposition (eg, CVD) at a high temperature of 1100 ° C. or higher.
  • a protective film 60 made of an oxide film or a nitride film is formed on the surface of the first epitaxial layer 11b with a film thickness of 5 to 50 nm, for example.
  • a resist film 50 in which the openings 51 are formed is formed by a lithography fluffy technique.
  • the resist film 50 has a thickness of 1 to 3 ⁇ m and an aspect ratio of 10 or less.
  • a plurality of n-type layers 41a serving as photoelectric conversion regions are formed in the first epitaxial layer 11b by an impurity doping technique (for example, ion implantation method).
  • the n-type layer 41a is formed of, for example, atoms having a large mass such as Sb that is difficult to outdope.
  • the n-type layer 41a is made to be the first epitaxial layer so that the n-type impurity concentration on the surface is less than 10 ⁇ 10 atoms / cm 3. Formed in layer 11b.
  • a resist film 50 in which the openings 51 are formed is formed on the surface of the first epitaxial layer 11b by lithography, and a plurality of resist films 50 are formed by impurity doping (for example, ion implantation).
  • a p-type layer 18a that electrically isolates the n-type layer 41a is formed on the side of the n-type layer 41a (between a plurality of n-type layers 41a).
  • a resist film 50 having an opening 51 formed above a part of the plurality of n-type layers 41a is formed on the surface of the first epitaxial layer 11b. Then, after forming the p-type layer 20 below a part of the n-type layer 41a by ion implantation, the protective film 60 is removed by an etching technique (for example, wet etching).
  • the second epitaxial layer 11c is formed on the surface of the first epitaxial layer 11b by, for example, chemical vapor deposition (CVD) at a high temperature of 1100 ° C. or higher.
  • CVD chemical vapor deposition
  • a protective film 61 made of an oxide film or a nitride film is formed on the surface of the second epitaxial layer 11c with a film thickness of 5 to 50 nm, for example.
  • a resist film 50 having an opening 51 is formed on the surface of the second epitaxial layer 11c, and n which becomes the photoelectric conversion region 12 in the second epitaxial layer 11c by an impurity doping technique (for example, ion implantation method).
  • a mold layer 41c is formed.
  • an opening 51 is formed above a part of the plurality of n-type layers 41c, and a resist mask having a form corresponding to the depth of ion implantation is formed on the surface of the second epitaxial layer 11c.
  • the n-type layer 41b is formed as a connection layer so that the n-type layer 41c and the n-type layer 41a below the opening 51 are electrically connected, and the solid-state imaging device 1 having the photoelectric conversion regions 12 having different depths.
  • alignment marks formed on the surface of the first epitaxial layer 11b are used so that a part or the whole of the n-type layer 41b overlaps both the n-type layers 41a and 41c with high accuracy.
  • the read gate 15 which is a p-type layer to be electrically separated and the p-type layers 18a, 18b and 18c are formed by lithography and impurity doping techniques, for example, by forming a resist mask each time.
  • a p-type layer 20a is formed below the n-type layer 41c where the n-type layer 41b is not formed below by an existing lithography technique and impurity doping technique.
  • region 12 differs, by forming the p-type layer 20a, it is a fixed position from the area
  • a p-type layer is set. Therefore, the vertical overflow drain is optimized for each pixel (for each photoelectric conversion region 12), and the voltage applied during the electronic shutter can be made the same.
  • a gate insulating film 21, a gate electrode 22, an antireflection film 32, and the like are formed on the surface of the second epitaxial layer 11c.
  • the solid-state image pickup device 1 formed by the above manufacturing method becomes a solid-state image pickup device that can obtain the effects as described in the first embodiment.
  • FIG. 6 is a diagram showing the impurity concentration distribution in the depth direction (normal direction of the substrate surface) of the n-type layer constituting the photoelectric conversion region in the substrate of the solid-state imaging device.
  • 6A shows an impurity concentration distribution in a general solid-state imaging device
  • FIG. 6B shows an impurity concentration distribution in the solid-state imaging device 1 of the present embodiment.
  • the solid line shows the concentration distribution of the n-type impurity in each n-type layer constituting the photoelectric conversion region
  • the broken line shows the concentration distribution when the concentration of the n-type impurity in each n-type layer is combined. Is shown.
  • the spread of the impurity concentration distribution is large at a deep position of the substrate (C portion in FIG. 6 (a)), but as shown in FIG. 6 (b).
  • the spread of the impurity concentration distribution is small at a deep position of the substrate (D portion in FIG. 6B).
  • the solid-state imaging device of the present invention has been described based on the embodiment.
  • the present invention is not limited to this embodiment.
  • the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
  • the n-type is exemplified as the first conductivity type
  • the p-type is exemplified as the second conductivity type opposite to the first conductivity type.
  • the first conductivity type is the p-type
  • the second conductivity type may be n-type.
  • the present invention is suitable for a solid-state imaging device and a method for manufacturing the same, and is suitable for application to, for example, an imaging device of various imaging apparatuses.

Abstract

Disclosed is a solid-state imaging element in which the deterioration in sensitivity associated with the reduction in pixel sizes can be avoided. The solid-state imaging element has a substrate (11) having, formed thereon, multiple photoelectric conversion regions (12) which can photoelectrically convert incident light, read-out gates (15) which can read out signal charges from the corresponding photoelectric conversion regions (12) and transfer units (16) which can transfer the signal charges that have been read out by the read-out gates (15), wherein the substrate (11) comprises a semiconductor substrate (11a), a first epitaxial layer (11b) of a first conductivity type formed on the semiconductor substrate (11a), and a second epitaxial layer (11c) of the first conductivity type formed on the first epitaxial layer (11b), and each of the photoelectric conversion regions (12) lies astride the first epitaxial layer (11b) and the second epitaxial layer (11c).

Description

固体撮像素子Solid-state image sensor
　本発明は、固体撮像素子に関し、詳しくは遮光膜を有するインターレース式およびＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）型の固体撮像素子に関するものである。 The present invention relates to a solid-state imaging device, and more particularly to an interlaced type CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device having a light shielding film.
　近年、固体撮像素子は、多画素化が進められ、画素寸法の微細化も進む一方である。固体撮像素子には、従来からＣＣＤ（Ｃｈａｒｇｅ　Ｃｏｕｐｌｅｄ　Ｄｅｖｉｃｅ）型の固体撮像素子が多く用いられている。このようなＣＣＤ型の固体撮像素子を開示する技術として、例えば特許文献１がある。特許文献１において、撮像領域は光電変換領域、電荷転送電極、電荷転送領域、電荷読み出し電極、電荷読み出し領域、および素子分離領域等で構成されている。 In recent years, the number of pixels of solid-state image sensors has been increased, and the pixel dimensions have been reduced. Conventionally, a CCD (Charge Coupled Device) type solid-state image sensor is often used as the solid-state image sensor. As a technique for disclosing such a CCD type solid-state imaging device, there is, for example, Patent Document 1. In Patent Document 1, the imaging region is composed of a photoelectric conversion region, a charge transfer electrode, a charge transfer region, a charge readout electrode, a charge readout region, an element isolation region, and the like.
特開２００７－２６６０３６号公報JP 2007-266036 A
　図７Ａは一般的な固体撮像素子１０１の平面レイアウト図であり、図７Ｂは同固体撮像素子１０１の概略構成を示す断面図（図７ＡにおけるＡ－Ａ’線の断面図）である。 7A is a plan layout view of a general solid-state image sensor 101, and FIG. 7B is a cross-sectional view (cross-sectional view taken along line A-A ′ in FIG. 7A) showing a schematic configuration of the solid-state image sensor 101.
　この固体撮像素子１０１では、図７Ａおよび図７Ｂに示すように、半導体基板１１１ａ上にエピタキシャル層１１１ｂおよび１１１ｃが形成されており、エピタキシャル層１１１ｃ内に光電変換領域１１２が形成されている。 In this solid-state imaging device 101, as shown in FIGS. 7A and 7B, epitaxial layers 111b and 111c are formed on a semiconductor substrate 111a, and a photoelectric conversion region 112 is formed in the epitaxial layer 111c.
　この光電変換領域１１２は、上層に形成されたｐ+層からなるホールアキュムレーション層１４０と、その下層に形成されたｎ+型拡散層１４１およびｐウェル１２０とからなる。この光電変換領域１１２のｎ+型拡散層１４１は、エピタキシャル層１１１ｃ表面にホールアキュムレーション層１４０が形成されることを考慮してエピタキシャル層１１１ｃの深い位置まで形成される。ただし、ｎ+型拡散層１４１は、エピタキシャル層１１１ｃの膜厚以上の深い位置までは、形成されない。 The photoelectric conversion region 112 is composed of a hole accumulation layer 140 made of a p + layer formed in an upper layer, and an n + type diffusion layer 141 and a p well 120 formed in the lower layer. The n + type diffusion layer 141 in the photoelectric conversion region 112 is formed up to a deep position of the epitaxial layer 111c in consideration of the formation of the hole accumulation layer 140 on the surface of the epitaxial layer 111c. However, the n + -type diffusion layer 141 is not formed up to a position deeper than the film thickness of the epitaxial layer 111c.
　光電変換領域１１２の一方側には、読み出しゲート（電荷読み出し領域）１１５を介して、電荷転送領域として垂直転送部（垂直レジスタ）１１６が形成されている。この垂直転送部１１６は、上層にｎ型層１４２を備え、その下層にｐ型層１１８ａを備えている。さらに、この垂直転送部１１６に隣接して、画素領域（光電変換領域１１２）を他の画素領域から水平方向に電気的に分離する画素分離領域１１８を構成するｐ型層１１８ｂが形成されている。 On one side of the photoelectric conversion region 112, a vertical transfer unit (vertical register) 116 is formed as a charge transfer region via a read gate (charge read region) 115. The vertical transfer unit 116 includes an n-type layer 142 in the upper layer and a p-type layer 118a in the lower layer. Further, a p-type layer 118b constituting a pixel isolation region 118 that electrically isolates the pixel region (photoelectric conversion region 112) from other pixel regions in the horizontal direction is formed adjacent to the vertical transfer unit 116. .
　光電変換領域１１２の他方側には、ｐ型層１１８ｂを介してこの光電変換領域１１２に隣接する別の光電変換領域１１２を含む画素（単位セル）の垂直転送部１１６が形成されている。垂直転送部１１６および読み出しゲート１１５上には、ゲート酸化膜となる絶縁膜１２１を介して、電荷読み出し電極および電荷転送電極となるゲート電極１２２が形成されている。さらに、層間絶縁膜を介して、光電変換領域１１２上に開口部１３４が設けられた遮光膜１３３が形成されている。そして、開口部１３４内には反射防止膜１３２が形成され、遮光膜１３３上には層間絶縁膜１３１が形成されている。 On the other side of the photoelectric conversion region 112, a vertical transfer unit 116 of a pixel (unit cell) including another photoelectric conversion region 112 adjacent to the photoelectric conversion region 112 is formed via a p-type layer 118b. On the vertical transfer unit 116 and the read gate 115, a gate electrode 122 serving as a charge read electrode and a charge transfer electrode is formed via an insulating film 121 serving as a gate oxide film. Further, a light shielding film 133 having an opening 134 provided on the photoelectric conversion region 112 is formed via an interlayer insulating film. An antireflection film 132 is formed in the opening 134, and an interlayer insulating film 131 is formed on the light shielding film 133.
　図７Ｃおよび図７Ｄは、図７Ａおよび図７Ｂの構造を有する固体撮像素子１０１の形成方法を説明するための断面図である。 7C and 7D are cross-sectional views for explaining a method for forming the solid-state imaging device 101 having the structure of FIGS. 7A and 7B.
　まず、図７Ｃに示すように、半導体基板１１１ａとエピタキシャル層１１１ｂおよび１１１ｃとから構成される基板１１１内にｐウェル１２０を形成する。その後、エピタキシャル層１１１ｃ表面上に保護膜１６０を形成し、リソグラフィ技術によってレジスト膜１５０を形成した後、レジスト膜１５０に開口部１５１を形成する。 First, as shown in FIG. 7C, a p-well 120 is formed in a substrate 111 composed of a semiconductor substrate 111a and epitaxial layers 111b and 111c. Thereafter, a protective film 160 is formed on the surface of the epitaxial layer 111c, a resist film 150 is formed by a lithography technique, and then an opening 151 is formed in the resist film 150.
　次いで、図７Ｃに示すように、レジスト膜１５０をマスクとした既存の不純物ドーピング技術（例えば、イオン注入法）によって、エピタキシャル層１１１ｃ表面に、光電変換領域１１２の第一導電型（ｎ型）の領域としての島状のｎ+型拡散層１４１を形成する。ｎ+型拡散層１４１は、２～４μｍの深さまで形成する。形成する深さは、どの範囲まで長波長側の光を光電変換させるかを考慮して決められる。たとえば、赤色（λ＝５５０ｎｍ）の波長の光は、エピタキシャル層１１１ｃ表面上から３μｍ以上の深さで光電変換される。ｎ+型拡散層１４１を深く形成することで、画素の感度（ダイナミックレンジ）を増加させることができる。 Next, as shown in FIG. 7C, the first conductivity type (n-type) of the photoelectric conversion region 112 is formed on the surface of the epitaxial layer 111c by an existing impurity doping technique (for example, ion implantation method) using the resist film 150 as a mask. An island-like n + -type diffusion layer 141 as a region is formed. The n + -type diffusion layer 141 is formed to a depth of 2 to 4 μm. The depth to be formed is determined in consideration of up to which range the light on the long wavelength side is photoelectrically converted. For example, light having a wavelength of red (λ = 550 nm) is photoelectrically converted at a depth of 3 μm or more from the surface of the epitaxial layer 111c. By forming the n + -type diffusion layer 141 deeply, the sensitivity (dynamic range) of the pixel can be increased.
　次いで、図７Ｄに示すように、リソグラフィ技術および不純物ドーピング技術により、その都度レジストマスクを形成して、光電変換領域１１２（ｎ+型拡散層１４１）の逆の導電型の読み出しゲート１１５、垂直転送部１１６のｐ型層１１８ａおよび画素分離領域１１８のｐ型層１１８ｂを形成する。 Next, as shown in FIG. 7D, a resist mask is formed each time by lithography technique and impurity doping technique, and the readout gate 115 having the opposite conductivity type in the photoelectric conversion region 112 (n + type diffusion layer 141), vertical transfer A p-type layer 118 a of the part 116 and a p-type layer 118 b of the pixel isolation region 118 are formed.
　ところで、図７Ａおよび図７Ｂの固体撮像素子１０１では、エピタキシャル層１１１ｃ表面から２～４μｍに光電変換領域１１２のｎ+型拡散層１４１を形成するには、たとえば、イオン注入法では、数千ｋｅＶの加速エネルギーが必要である。従って、リソグラフィ技術では、イオン注入法による不純物ドーピングを阻止する高アスペクト化レジスト（たとえば、レジスト膜厚が６μｍ以上、アスペクト比が１５以上のレジスト）が必要である。その結果、微細加工ばらつきが生じやすく、光電変換領域１１２を一定の形態で高精度に形成することが困難であるため、画素サイズのシュリンク（縮小）に対応することが困難である。 7A and 7B, in order to form the n + -type diffusion layer 141 of the photoelectric conversion region 112 from 2 to 4 μm from the surface of the epitaxial layer 111c, for example, in the ion implantation method, several thousand keV is used. Accelerating energy is required. Therefore, the lithography technique requires a high aspect ratio resist (for example, a resist film thickness of 6 μm or more and an aspect ratio of 15 or more) that prevents impurity doping by the ion implantation method. As a result, fine processing variations are likely to occur, and it is difficult to form the photoelectric conversion region 112 with a certain form with high accuracy.
　また、さらなる多画素化が進むに従って、画素サイズのさらなるシュリンクが必要になってきている。しかし画素特性の維持は必要なため、感度（ダイナミックレンジ）悪化を抑えつつ、これ以上の光電変換領域の面積拡大および面積維持が困難である。従って、固体撮像素子の多画素化の要求に応じて固体撮像素子を微細化するには、入射した光を光電変換する領域を深さ方向に増やすことが必要となる。特許文献１では、広ダイナミックレンジの画像生成を目的として、光電変換領域の深さが異なる２つの隣接する画素上に同一色のカラーフィルター群を有する構造が提案されている。すなわち、特許文献１は、低照度側（シャドウ）と高照度側（ハイライト）の入射エネルギー制御による高感度化を意図している。しかしながら、更なる高感度化の要求から光電変換領域の微細化かつ高い精度での深さ方向への拡大（深さ拡大）が必要である。 Also, as the number of pixels increases, further shrinking of pixel size is required. However, since it is necessary to maintain the pixel characteristics, it is difficult to further increase the area and maintain the area of the photoelectric conversion region while suppressing deterioration in sensitivity (dynamic range). Therefore, in order to miniaturize the solid-state image sensor in response to the demand for increasing the number of pixels of the solid-state image sensor, it is necessary to increase the area for photoelectric conversion of incident light in the depth direction. Patent Document 1 proposes a structure having color filter groups of the same color on two adjacent pixels having different photoelectric conversion region depths for the purpose of generating an image with a wide dynamic range. That is, Patent Document 1 intends to increase sensitivity by controlling incident energy on the low illuminance side (shadow) and high illuminance side (highlight). However, in order to further increase the sensitivity, it is necessary to make the photoelectric conversion region finer and expand in the depth direction (depth expansion) with high accuracy.
　本発明の目的は、画素サイズの縮小にともなう感度低下を抑制することができる固体撮像素子を提供することである。 An object of the present invention is to provide a solid-state imaging device capable of suppressing a decrease in sensitivity associated with a reduction in pixel size.
　本発明の一観点の固体撮像素子は、入射光を光電変換する複数の光電変換領域と、対応する前記光電変換領域から信号電荷を読み出すための読み出しゲートと、前記読み出しゲートによって読み出された前記信号電荷の転送を行うための転送部とが形成された基板を備え、前記基板は、半導体基板と、前記半導体基板上に形成された第１導電型の第１のエピタキシャル層と、前記第１のエピタキシャル層上に形成された第１導電型の第２のエピタキシャル層とを含み、前記光電変換領域が、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成されていることを特徴とする。 A solid-state imaging device according to an aspect of the present invention includes a plurality of photoelectric conversion regions that photoelectrically convert incident light, a read gate for reading signal charges from the corresponding photoelectric conversion region, and the read gate by the read gate. A substrate on which a transfer unit for transferring signal charges is formed, the substrate including a semiconductor substrate, a first conductivity type first epitaxial layer formed on the semiconductor substrate, and the first substrate A first conductivity type second epitaxial layer formed on the first epitaxial layer, and the photoelectric conversion region is formed across the first epitaxial layer and the second epitaxial layer. It is characterized by that.
　この構成により、半導体基板上に第１のエピタキシャル層を形成し、第１のエピタキシャル層に既存のリソグラフィ技術と不純物ドーピング技術とにより光電変換領域の一部を島状に形成し、第１のエピタキシャル層表面上に第２のエピタキシャル層を形成し、既存のリソグラフィ技術と不純物ドーピング技術とにより島状の光電変換領域の一部と重なるように光電変換領域の別の一部を島状に形成して島状の領域を電気的に接続することで、既存の技術で深い光電変換領域を形成することが可能になる。その結果、特に高波長側の光電変換率を増加させて高感度化が可能になるため、画素サイズの縮小にともなう感度低下を抑制できる。 With this configuration, the first epitaxial layer is formed on the semiconductor substrate, and a part of the photoelectric conversion region is formed in an island shape by the existing lithography technique and impurity doping technique in the first epitaxial layer. A second epitaxial layer is formed on the surface of the layer, and another part of the photoelectric conversion region is formed in an island shape so as to overlap with a part of the island-shaped photoelectric conversion region by the existing lithography technique and impurity doping technique. By connecting the island-shaped regions electrically, it is possible to form a deep photoelectric conversion region using existing technology. As a result, it is possible to increase the sensitivity by increasing the photoelectric conversion rate particularly on the high wavelength side, and therefore it is possible to suppress a decrease in sensitivity due to the reduction in pixel size.
　また、超高エネルギー注入装置を使用することなく、光電変換領域の深さを任意に設定することができ、また光電変換領域のパターニングも高アスペクト比の厚膜レジストを使用することなく行うことができる。従って、撮像エリア内の光電変換領域を微細かつ高精度に加工形成できる。 In addition, the depth of the photoelectric conversion region can be arbitrarily set without using an ultra-high energy injection device, and patterning of the photoelectric conversion region can be performed without using a thick film resist having a high aspect ratio. it can. Therefore, the photoelectric conversion region in the imaging area can be processed and formed with high precision.
　ここで、前記複数の光電変換領域の一部は、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がらないで前記第２のエピタキシャル層に形成されていてもよい。 Here, some of the plurality of photoelectric conversion regions may be formed in the second epitaxial layer without straddling the first epitaxial layer and the second epitaxial layer.
　この構成により、撮像エリア内で２つのエピタキシャル層に跨がって形成された光電変換領域と、２つのエピタキシャル層に跨がらない光電変換領域とを形成することができ、深さの異なる光電変換領域を形成することができる。従って、カラーフィルター毎つまり光電変換する色毎に最適な深さの光電変換領域を設けることが可能になり、隣接する画素からのウェルを通した光の進入（混色）の低減が可能となる。 With this configuration, it is possible to form a photoelectric conversion region formed across two epitaxial layers in the imaging area and a photoelectric conversion region that does not straddle two epitaxial layers. Regions can be formed. Therefore, it is possible to provide a photoelectric conversion region having an optimum depth for each color filter, that is, for each color to be subjected to photoelectric conversion, and it is possible to reduce the entry (color mixing) of light from adjacent pixels through a well.
　本発明によれば、画素サイズの縮小にともなう感度低下を抑制できるという効果が奏される。 According to the present invention, there is an effect that it is possible to suppress a decrease in sensitivity associated with a reduction in pixel size.
図１Ａは、本発明の第１の実施の形態に係る固体撮像素子の平面レイアウト図である。FIG. 1A is a plan layout diagram of the solid-state imaging device according to the first embodiment of the present invention. 図１Ｂは、同実施の形態に係る固体撮像素子の概略構成を示す断面図（図１ＡにおけるＡ－Ａ’線の断面図）である。FIG. 1B is a cross-sectional view (a cross-sectional view taken along line A-A ′ in FIG. 1A) showing a schematic configuration of the solid-state imaging device according to the embodiment. 図２Ａは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 2A is a cross-sectional view showing a manufacturing process in the method for manufacturing the solid-state imaging device according to the embodiment. 図２Ｂは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 2B is a cross-sectional view showing a manufacturing process in the method for manufacturing the solid-state imaging element according to the embodiment. 図２Ｃは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 2C is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment. 図２Ｄは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 2D is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment. 図２Ｅは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 2E is a cross-sectional view showing the manufacturing process in the manufacturing method of the solid-state imaging element according to the embodiment. 図２Ｆは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 2F is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment. 図３Ａは、同実施の形態に係る固体撮像素子の製造方法におけるアライメントマークの形成工程を示す断面図である。FIG. 3A is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging device according to the embodiment. 図３Ｂは、同実施の形態に係る固体撮像素子の製造方法におけるアライメントマークの形成工程を示す断面図である。FIG. 3B is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment. 図３Ｃは、同実施の形態に係る固体撮像素子の製造方法におけるアライメントマークの形成工程を示す断面図である。FIG. 3C is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment. 図３Ｄは、同実施の形態に係る固体撮像素子の製造方法におけるアライメントマークの形成工程を示す断面図である。FIG. 3D is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment. 図３Ｅは、同実施の形態に係る固体撮像素子の製造方法におけるアライメントマークの形成工程を示す断面図である。FIG. 3E is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment. 図４Ａは、同実施の形態に係る固体撮像素子の変形例の概略構成を示す断面図である。FIG. 4A is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment. 図４Ｂは、同実施の形態に係る固体撮像素子の変形例の概略構成を示す断面図である。FIG. 4B is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment. 図５Ａは、本発明の第２の実施の形態に係る固体撮像素子の概略構成を示す断面図である。FIG. 5A is a cross-sectional view showing a schematic configuration of a solid-state imaging element according to the second embodiment of the present invention. 図５Ｂは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5B is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment. 図５Ｃは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5C is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment. 図５Ｄは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5D is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment. 図５Ｅは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5E is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment. 図５Ｆは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5F is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment. 図５Ｇは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5G is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment. 図５Ｈは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5H is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment. 図５Ｉは、同実施の形態に係る固体撮像素子の製造方法における製造工程を示す断面図である。FIG. 5I is a cross-sectional view showing the manufacturing process in the method for manufacturing the solid-state imaging device according to the embodiment. 図６は、固体撮像素子の光電変換領域の不純物濃度分布を示す図である。FIG. 6 is a diagram illustrating an impurity concentration distribution in the photoelectric conversion region of the solid-state imaging device. 図７Ａは、一般的な固体撮像素子の平面レイアウト図である。FIG. 7A is a plan layout diagram of a general solid-state imaging device. 図７Ｂは、一般的な固体撮像素子の概略構成を示す断面図（図７ＡにおけるＡ－Ａ’線の断面図）である。FIG. 7B is a cross-sectional view (a cross-sectional view taken along the line A-A ′ in FIG. 7A) showing a schematic configuration of a general solid-state imaging device. 図７Ｃは、一般的な固体撮像素子の形成方法を説明するための断面図である。FIG. 7C is a cross-sectional view for explaining a general method for forming a solid-state imaging device. 図７Ｄは、一般的な固体撮像素子の形成方法を説明するための断面図である。FIG. 7D is a cross-sectional view for explaining a general method for forming a solid-state imaging element.
　以下、本発明の実施の形態における固体撮像素子について、図面を参照しながら説明する。 Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.
　（第１の実施の形態）
　本実施の形態に係るＣＣＤ型の固体撮像素子１について図１Ａおよび図１Ｂを用いて説明する。図１Ａは同固体撮像素子１の平面レイアウト図であり、図１Ｂは同固体撮像素子１の概略構成を示す断面図（図１ＡにおけるＡ－Ａ’線の断面図）である。 (First embodiment)
A CCD type solid-state imaging device 1 according to the present embodiment will be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan layout view of the solid-state image sensor 1, and FIG. 1B is a cross-sectional view (cross-sectional view taken along line AA ′ in FIG. 1A) showing a schematic configuration of the solid-state image sensor 1.
　この固体撮像素子１では、図１Ｂに示すように、たとえばシリコン基板等の半導体基板１１ａ表面上の第１導電型（ｎ型）の第１のエピタキシャル層１１ｂと第１導電型の第２のエピタキシャル層１１ｃとに跨がって（第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとの境界を横切る形で、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとにわたって連続して）光電変換領域１２が形成されている。基板１１は、半導体基板１１ａと、半導体基板１１ａ上に形成された第１のエピタキシャル層１１ｂと、第１のエピタキシャル層１１ｂ上に形成された第２のエピタキシャル層１１ｃとを含み、光電変換領域１２、読み出しゲート１５および転送部１６が内部に形成されている。 In the solid-state imaging device 1, as shown in FIG. 1B, a first conductivity type (n-type) first epitaxial layer 11b and a first conductivity type second epitaxial layer on the surface of a semiconductor substrate 11a such as a silicon substrate, for example. Over the layer 11c (continuously across the first epitaxial layer 11b and the second epitaxial layer 11c across the boundary between the first epitaxial layer 11b and the second epitaxial layer 11c) A conversion region 12 is formed. The substrate 11 includes a semiconductor substrate 11a, a first epitaxial layer 11b formed on the semiconductor substrate 11a, and a second epitaxial layer 11c formed on the first epitaxial layer 11b. A read gate 15 and a transfer unit 16 are formed inside.
　この固体撮像素子１では、複数の光電変換領域１２のそれぞれは、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成されている。複数の光電変換領域１２は、マトリクス状（行列状）に配置されている。 In the solid-state imaging device 1, each of the plurality of photoelectric conversion regions 12 is formed across the first epitaxial layer 11b and the second epitaxial layer 11c. The plurality of photoelectric conversion regions 12 are arranged in a matrix (matrix).
　第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成された光電変換領域１２は、入射光を光電変換する領域であり、同じ導電型のｎ型層（第１の層）４１ａおよびｎ型層（第２の層）４１ｂ、ｐ+型のホールアキュムレーション層４０並びにｐ型層（ｐウェル）２０を含む。この光電変換領域１２は、ｎ型層４１ａおよびｐ型層２０が形成された第１のエピタキシャル層１１ｂ上に第２のエピタキシャル層１１ｃを形成した後、第２のエピタキシャル層１１ｃにｎ型層４１ｂおよびホールアキュムレーション層４０を形成することにより形成される。ｎ型層４１ａは第１のエピタキシャル層１１ｂにのみ形成されているが、ｎ型層４１ｂは第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成されており、ｎ型層４１ａの全体又は一部と重なっている。ｎ型層４１ａとｎ型層４１ｂとは、電気的に接続されている。光電変換領域１２は、上層にホールアキュムレーション層４０を備え、下層にｎ型層４１ａおよび４１ｂならびにｐ型層２０を備えている。 The photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c is a region that photoelectrically converts incident light, and is an n-type layer (first layer) of the same conductivity type. ) 41a and n-type layer (second layer) 41b, p + -type hole accumulation layer 40 and p-type layer (p-well) 20. In the photoelectric conversion region 12, after the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a and the p-type layer 20 are formed, the n-type layer 41b is formed on the second epitaxial layer 11c. And the hole accumulation layer 40 is formed. The n-type layer 41a is formed only on the first epitaxial layer 11b, but the n-type layer 41b is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and the n-type layer 41b is formed. It overlaps with the whole or a part of the layer 41a. The n-type layer 41a and the n-type layer 41b are electrically connected. The photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer, and includes n- type layers 41 a and 41 b and a p-type layer 20 in the lower layer.
　第１のエピタキシャル層１１ｂの表面上には、ｎ型層４１ａとｎ型層４１ｂとが第２のエピタキシャル層１１ｃを表面からみたとき重なる位置にあるようにｎ型層４１ｂの形成でその位置を決定するために用いられる工程位置合わせマークが形成されている。第２のエピタキシャル層１１ｃの膜厚は５μｍ以下である。膜厚を５μｍ以下とすることで、不純物を精度良く注入することができ、また、第１のエピタキシャル層１１ｂとも確実に接続できる。 On the surface of the first epitaxial layer 11b, the n-type layer 41b is formed so that the n-type layer 41a and the n-type layer 41b overlap each other when the second epitaxial layer 11c is viewed from the surface. A process alignment mark used for determination is formed. The film thickness of the second epitaxial layer 11c is 5 μm or less. By setting the film thickness to 5 μm or less, impurities can be injected with high accuracy and can be reliably connected to the first epitaxial layer 11b.
　第１のエピタキシャル層１１ｂは、例えば３～５μｍの膜厚で形成されている。また第２のエピタキシャル層１１ｃは、例えば１～３μｍの膜厚で形成されている。第１のエピタキシャル層１１ｂおよび第２のエピタキシャル層１１ｃは、その抵抗値がたとえばｎ型層で０．１～１００Ω・ｃｍとなるように形成されている。 The first epitaxial layer 11b is formed with a film thickness of 3 to 5 μm, for example. The second epitaxial layer 11c is formed with a film thickness of, for example, 1 to 3 μm. The first epitaxial layer 11b and the second epitaxial layer 11c are formed so that their resistance values are, for example, 0.1 to 100 Ω · cm for an n-type layer.
　光電変換領域１２の側方には、画素分離領域（画素水平分離領域）１８、つまり読み出しゲート（電荷読み出し領域）１５、電荷転送領域としての転送部（垂直転送部）１６、およびｐ型層１８ｂが形成されている。 Beside the photoelectric conversion region 12, a pixel separation region (pixel horizontal separation region) 18, that is, a readout gate (charge readout region) 15, a transfer unit (vertical transfer unit) 16 as a charge transfer region, and a p-type layer 18b. Is formed.
　読み出しゲート１５は、複数の光電変換領域１２のそれぞれに対応して設けられ、対応する光電変換領域１２から信号電荷を読み出す。 Read gate 15 is provided corresponding to each of the plurality of photoelectric conversion regions 12, and reads signal charges from the corresponding photoelectric conversion regions 12.
　転送部１６は、読み出しゲート１５によって読み出された信号電荷の転送を行うための転送路であり、その上層にｎ型層４２を備え、その下層にｐ型層１８ａを備えている。光電変換領域１２の下部には、垂直オーバーフロードレインを形成するｐ型層２０が形成されている。転送部１６に隣接して、画素領域を他の画素領域から水平方向に電気的に分離するためのｐ型層１８ｂが形成されている。 The transfer unit 16 is a transfer path for transferring the signal charges read by the read gate 15, and includes an n-type layer 42 in the upper layer and a p-type layer 18a in the lower layer. A p-type layer 20 that forms a vertical overflow drain is formed below the photoelectric conversion region 12. Adjacent to the transfer unit 16, a p-type layer 18b for electrically separating the pixel region from other pixel regions in the horizontal direction is formed.
　光電変換領域１２の上層のホールアキュムレーション層４０上方に、基板１１に進入する入射光の反射を防ぐ反射防止膜３２が形成されている。反射防止膜３２の屈折率は、基板１１の屈折率より大きく、反射防止膜３２上の層間絶縁膜の屈折率より小さい。 An antireflection film 32 that prevents reflection of incident light entering the substrate 11 is formed above the hole accumulation layer 40 in the upper layer of the photoelectric conversion region 12. The refractive index of the antireflection film 32 is larger than the refractive index of the substrate 11 and smaller than the refractive index of the interlayer insulating film on the antireflection film 32.
　基板１１表面上にはゲート絶縁膜２１が形成され、ゲート絶縁膜２１上には電荷読み出し電極および電荷転送電極となるゲート電極２２が形成されている。ゲート電極２２は、１層構造で形成されているが、２層構造、３層構造、または４層構造で形成されてもよい。このゲート電極２２は、図示したように、読み出しゲート１５および転送部１６の直上に形成されることが好ましい。 A gate insulating film 21 is formed on the surface of the substrate 11, and a gate electrode 22 serving as a charge readout electrode and a charge transfer electrode is formed on the gate insulating film 21. The gate electrode 22 is formed with a one-layer structure, but may be formed with a two-layer structure, a three-layer structure, or a four-layer structure. The gate electrode 22 is preferably formed immediately above the read gate 15 and the transfer unit 16 as shown in the figure.
　ゲート電極２２およびゲート絶縁膜２１を被覆する層間絶縁膜３１が基板１１表面上に形成されている。さらに層間絶縁膜３１とゲート電極２２およびゲート絶縁膜２１との間には、光電変換領域１２上方に開口部が形成された遮光膜３３が形成されている。 An interlayer insulating film 31 covering the gate electrode 22 and the gate insulating film 21 is formed on the surface of the substrate 11. Further, a light shielding film 33 having an opening formed above the photoelectric conversion region 12 is formed between the interlayer insulating film 31 and the gate electrode 22 and the gate insulating film 21.
　以下、本実施の形態に係る固体撮像素子１の製造方法（光電変換領域１２の詳細な製造方法）を図２Ａ～図２Ｆに示す。図２Ａ～図２Ｆは、同固体撮像素子１の製造方法における製造工程を示す断面図である。 Hereinafter, a manufacturing method of the solid-state imaging device 1 according to the present embodiment (a detailed manufacturing method of the photoelectric conversion region 12) is shown in FIGS. 2A to 2F. 2A to 2F are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1. FIG.
　まず、図２Ａに示すように、半導体基板１１ａ上に第１導電型の第１のエピタキシャル層１１ｂを例えば、１１００℃以上の高温での化学気相成長法（たとえば、ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）によって形成する。その後、第１のエピタキシャル層１１ｂ表面上に酸化膜もしくは窒化膜からなる保護膜６０を例えば、５～５０ｎｍの膜厚で形成する。 First, as shown in FIG. 2A, a first conductive type first epitaxial layer 11b is formed on a semiconductor substrate 11a by a chemical vapor deposition method (for example, CVD: Chemical Vapor Deposition) at a high temperature of 1100 ° C. or higher. Form. Thereafter, a protective film 60 made of an oxide film or a nitride film is formed on the surface of the first epitaxial layer 11b with a film thickness of 5 to 50 nm, for example.
　次いで、図２Ａに示すように、リソグフラフィー技術によって、開口部５１が形成されたレジスト膜５０を形成する。レジスト膜５０は、例えば膜厚が１～３μｍ、アスペクト比が１０以下とされる。そして、不純物ドーピング技術（例えば、イオン注入法）によって、第１のエピタキシャル層１１ｂに光電変換領域となるｎ型層４１ａを複数形成する。ｎ型層４１ａは、例えば、アウトドーピングし難いＳｂ等の質量が大きい原子で形成される。なお、ｎ型層４１ａの形成にＡｓ等の軽い原子を使用する場合は、例えば、表面のｎ型不純物濃度が１０-10ａｔｏｍｓ／ｃｍ3未満となるようにｎ型層４１ａを第１のエピタキシャル層１１ｂ内に形成する。ｎ型層４１ａを形成後、保護膜６０をエッチング技術（たとえば、ウエットエッチング）によって除去する。 Next, as shown in FIG. 2A, a resist film 50 in which the openings 51 are formed is formed by a lithography fluffy technique. For example, the resist film 50 has a thickness of 1 to 3 μm and an aspect ratio of 10 or less. Then, a plurality of n-type layers 41a serving as photoelectric conversion regions are formed in the first epitaxial layer 11b by an impurity doping technique (for example, ion implantation method). The n-type layer 41a is formed of, for example, atoms having a large mass such as Sb that is difficult to outdope. When light atoms such as As are used to form the n-type layer 41a, for example, the n-type layer 41a is made to be the first epitaxial layer so that the n-type impurity concentration on the surface is less than 10 −10 atoms / cm 3. Formed in layer 11b. After forming the n-type layer 41a, the protective film 60 is removed by an etching technique (for example, wet etching).
　次いで、図２Ｂに示すように、第１のエピタキシャル層１１ｂ表面上に第２のエピタキシャル層１１ｃを例えば、１１００℃以上の高温での化学気相成長法（たとえば、ＣＶＤ）によって形成する。 Next, as shown in FIG. 2B, a second epitaxial layer 11c is formed on the surface of the first epitaxial layer 11b by, for example, chemical vapor deposition (for example, CVD) at a high temperature of 1100 ° C. or higher.
　次いで、図２Ｃに示すように、第２のエピタキシャル層１１ｃ表面上に酸化膜もしくは窒化膜からなる保護膜６１を例えば、５～５０ｎｍの膜厚で形成する。その後、光電変換領域１２が２次元状に形成される撮像エリアにおいてのみ、光電変換領域１２となるｎ型層４１ａ下方にｐ型層（ｐウェル）２０をレジストマスクとイオン注入法によって形成する。ｐ型層２０により、垂直オーバーフロードレインを形成し、電子シャッター電圧をｐ型層２０で設定する。 Next, as shown in FIG. 2C, a protective film 61 made of an oxide film or a nitride film is formed on the surface of the second epitaxial layer 11c with a film thickness of, for example, 5 to 50 nm. Thereafter, only in the imaging area in which the photoelectric conversion region 12 is formed in a two-dimensional form, a p-type layer (p well) 20 is formed below the n-type layer 41a to be the photoelectric conversion region 12 by a resist mask and an ion implantation method. A vertical overflow drain is formed by the p-type layer 20, and an electronic shutter voltage is set by the p-type layer 20.
　次いで、図２Ｄに示すように、第２のエピタキシャル層１１ｃ表面上に開口部５１が形成されたレジスト膜５０を形成する。レジスト膜５０は、例えば、膜厚が２～５μｍ、アスペクト比が１０以下とされる。そして、不純物ドーピング技術（たとえばイオン注入法）によって、第２のエピタキシャル層１１ｃに光電変換領域１２となるｎ型層４１ｂを形成する。ｎ型層４１ｂは、ｎ型層４１ａに対応するように複数形成され、対応するｎ型層４１ａと電気的に接続される。このとき、ｎ型層４１ａとｎ型層４１ｂとが精度良く重なるように形成するため、第１のエピタキシャル層１１ｂ表面上に形成されたアライメントマークを使用する。 Next, as shown in FIG. 2D, a resist film 50 having an opening 51 formed on the surface of the second epitaxial layer 11c is formed. For example, the resist film 50 has a thickness of 2 to 5 μm and an aspect ratio of 10 or less. Then, an n-type layer 41b to be the photoelectric conversion region 12 is formed in the second epitaxial layer 11c by an impurity doping technique (for example, ion implantation method). A plurality of n-type layers 41b are formed so as to correspond to the n-type layer 41a, and are electrically connected to the corresponding n-type layer 41a. At this time, in order to form the n-type layer 41a and the n-type layer 41b so as to overlap with high accuracy, an alignment mark formed on the surface of the first epitaxial layer 11b is used.
　次いで、図２Ｅに示すように、複数のｎ型層４１ａおよび４１ｂのペアの間つまり複数の光電変換領域１２の間に、光電変換領域１２と転送部１６とを電気的に分離するｐ型層である読み出しゲート１５、ならびにｐ型層１８ａおよび１８ｂの形成をリソグラフィ技術および不純物ドーピング技術によって、例えば、その都度レジストマスクを形成して行う。 Next, as shown in FIG. 2E, a p-type layer that electrically separates the photoelectric conversion region 12 and the transfer unit 16 between a pair of the plurality of n- type layers 41 a and 41 b, that is, between the plurality of photoelectric conversion regions 12. The read gate 15 and the p- type layers 18a and 18b are formed by a lithography technique and an impurity doping technique, for example, by forming a resist mask each time.
　次いで、図２Ｆに示すように、レジスト膜５０と保護膜６０を除去後、第２のエピタキシャル層１１ｃ表面上にゲート絶縁膜２１およびゲート電極２２および反射防止膜３２等を形成する。 Next, as shown in FIG. 2F, after removing the resist film 50 and the protective film 60, the gate insulating film 21, the gate electrode 22, the antireflection film 32, and the like are formed on the surface of the second epitaxial layer 11c.
　ここで、ｎ型層４１ｂの形成で使用したアライメントマークの詳細な形成方法を図３Ａ～図３Ｅに示す。図３Ａ～図３Ｅは、アライメントマークの形成工程を示す固体撮像素子１の断面図であり、アライメントマークは、固体撮像素子の周辺の領域や、半導体ウエハの周辺などの位置に形成されるものであり、各製造工程での位置合わせの目印となる。 Here, a detailed method of forming the alignment mark used in forming the n-type layer 41b is shown in FIGS. 3A to 3E. 3A to 3E are cross-sectional views of the solid-state imaging device 1 showing the process of forming the alignment mark. The alignment mark is formed in a region around the solid-state imaging device or a position around the semiconductor wafer. There is a mark for alignment in each manufacturing process.
　まず、図３Ａに示すように、開口部５１が形成されたレジスト膜５０を形成し、これを用いてｎ型層４１ａを形成する。 First, as shown in FIG. 3A, a resist film 50 in which an opening 51 is formed is formed, and an n-type layer 41a is formed by using this.
　次いで、図３Ｂに示すように、レジスト膜５０をマスクにして、開口部５１内に位置して表面が露出した保護膜６０の部分の保護膜６０のみをエッチング技術（例えば、ウエットエッチング）によって除去する。 Next, as shown in FIG. 3B, using the resist film 50 as a mask, only the protective film 60 in the portion of the protective film 60 that is located in the opening 51 and whose surface is exposed is removed by an etching technique (for example, wet etching). To do.
　次いで、図３Ｃに示すように、アライメントマーク領域のみに開口部が形成されたレジスト膜（図外）を形成する。 Next, as shown in FIG. 3C, a resist film (not shown) having an opening formed only in the alignment mark region is formed.
　次いで、図３Ｄに示すように、ｎ型層４１ａの上方の第１のエピタキシャル層１１ｂおよび保護膜６０表面をレジスト膜５０で覆う。 Next, as shown in FIG. 3D, the surface of the first epitaxial layer 11 b and the protective film 60 above the n-type layer 41 a is covered with a resist film 50.
　次いで、図３Ｅに示すように、エッチング技術（たとえば、ドライエッチング）によって保護膜６０をハードマスクとしてレジスト膜５０をエッチングし、第１のエピタキシャル層１１ｂ表面にアライメントマークを転写する。アライメントマークの段差は、０．２μｍ以上とする。 Next, as shown in FIG. 3E, the resist film 50 is etched using the protective film 60 as a hard mask by an etching technique (for example, dry etching), and the alignment mark is transferred to the surface of the first epitaxial layer 11b. The step of the alignment mark is 0.2 μm or more.
　次いで、エッチング技術（例えば、ウエットエッチング）で保護膜６０を除去することで第１のエピタキシャル層１１ｂ表面を露出させた後、第２のエピタキシャル層１１ｃの形成を行う。 Next, the surface of the first epitaxial layer 11b is exposed by removing the protective film 60 by an etching technique (for example, wet etching), and then the second epitaxial layer 11c is formed.
　以上のように本実施の形態の固体撮像素子１によれば、画素サイズの縮小にともなう感度低下を抑制するという目的を、半導体基板１１ａ上に成膜された第１のエピタキシャル層１１ｂに第１の島状のｎ型層４１ａを形成し、第１のエピタキシャル層１１ｂ表面上に成膜された第２のエピタキシャル層１１ｃに第２の島状のｎ型層４１ｂをｎ型層４１ａの全体もしくは一部と重なるように形成し、第２のエピタキシャル層１１ｃ表面に転送部１６および読み出しゲート１５を形成することによって実現する。従って、光電変換領域１２は各エピタキシャル層と同時に形成されるため、既存のリソグラフィ技術および不純物ドーピング技術（たとえば、イオン注入法）で、微細かつ深い光電変換領域を形成することが可能となる。従って、感度およびダイナミックレンジを良化することが可能である。 As described above, according to the solid-state imaging device 1 of the present embodiment, the first epitaxial layer 11b formed on the semiconductor substrate 11a has the first purpose of suppressing the decrease in sensitivity due to the reduction in pixel size. The island-shaped n-type layer 41a is formed, and the second island-shaped n-type layer 41b is formed on the entire surface of the n-type layer 41a or the second epitaxial layer 11c formed on the surface of the first epitaxial layer 11b. It is formed so as to overlap a part, and is realized by forming the transfer portion 16 and the read gate 15 on the surface of the second epitaxial layer 11c. Therefore, since the photoelectric conversion region 12 is formed at the same time as each epitaxial layer, it is possible to form a fine and deep photoelectric conversion region by the existing lithography technique and impurity doping technique (for example, ion implantation method). Therefore, it is possible to improve sensitivity and dynamic range.
　なお、本実施の形態の固体撮像素子１において、ｎ型層４１ｂの側方への大きさはｎ型層４１ａより小さく、図４Ａに示すように、ｎ型層４１ｂの両側端はｎ型層４１ａの両側端より内側に位置してもよい。このようにすることで、ｎ型層４１ａである光電変換領域が広くなり、感度を向上させることができる。また、ｎ型層４１ｂの側方への大きさはｎ型層４１ａより大きく、図４Ｂに示すように、ｎ型層４１ｂの両側端はｎ型層４１ａの両側端より外側に位置していても良い。このようにすることで、深い位置まで到達した光が隣接画素に漏れこむ混色を防止できる。更に、第１のエピタキシャル層１１ｂは、光電変換領域１２（ｎ型層４１ｂ）と逆の導電型で形成されても良い。 In the solid-state imaging device 1 of the present embodiment, the lateral size of the n-type layer 41b is smaller than that of the n-type layer 41a, and as shown in FIG. 4A, both side ends of the n-type layer 41b are n-type layers. You may be located inside the both ends of 41a. By doing in this way, the photoelectric conversion area | region which is the n-type layer 41a becomes wide, and a sensitivity can be improved. Further, the lateral size of the n-type layer 41b is larger than that of the n-type layer 41a, and as shown in FIG. 4B, both side ends of the n-type layer 41b are positioned outside both side ends of the n-type layer 41a. Also good. By doing in this way, the color mixture which the light which reached | attained the deep position leaks into an adjacent pixel can be prevented. Furthermore, the first epitaxial layer 11b may be formed with a conductivity type opposite to that of the photoelectric conversion region 12 (n-type layer 41b).
　（第２の実施の形態）
　本実施の形態に係るＣＣＤ型の固体撮像素子１について図５Ａを用いて説明する。図５Ａは同固体撮像素子１の概略構成を示す断面図である。なお、本実施の形態に係る固体撮像素子１の平面レイアウト図は図１Ａと同様であり、図５Ａは図１Ｂと同様に図１ＡにおけるＡ－Ａ’線の断面図を示している。 (Second Embodiment)
A CCD type solid-state imaging device 1 according to the present embodiment will be described with reference to FIG. 5A. FIG. 5A is a cross-sectional view showing a schematic configuration of the solid-state imaging device 1. Note that the planar layout of the solid-state imaging device 1 according to the present embodiment is the same as FIG. 1A, and FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG.
　この固体撮像素子１では、図５Ａに示すように、たとえばシリコン基板等の半導体基板１１ａ表面上の第１導電型の第１のエピタキシャル層１１ｂと第１導電型の第２のエピタキシャル層１１ｃとに跨がって（第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとの境界を横切る形で、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとにわたって連続して）光電変換領域１２が形成されてなる第１画素と、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がらないで（第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとの境界を横切らない形で第１のエピタキシャル層１１ｂおよび第２のエピタキシャル層１１ｃのそれぞれに島状に独立に）光電変換領域１２が形成されてなる第２画素とが隣接して配置されている。 In the solid-state imaging device 1, as shown in FIG. 5A, for example, a first conductivity type first epitaxial layer 11b and a first conductivity type second epitaxial layer 11c on the surface of a semiconductor substrate 11a such as a silicon substrate are formed. The photoelectric conversion region 12 is straddled (continuously across the first epitaxial layer 11b and the second epitaxial layer 11c across the boundary between the first epitaxial layer 11b and the second epitaxial layer 11c). Do not straddle the formed first pixel, the first epitaxial layer 11b, and the second epitaxial layer 11c (in a form that does not cross the boundary between the first epitaxial layer 11b and the second epitaxial layer 11c) A photoelectric conversion region 12 is formed in each of the first epitaxial layer 11b and the second epitaxial layer 11c independently in an island shape. A second pixel comprising are arranged adjacent.
　この固体撮像素子１では、複数の光電変換領域１２の一部が第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成され、複数の光電変換領域１２の他部が第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がらないで形成されている。第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成された光電変換領域１２と、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がらないで形成された光電変換領域１２とが交互に行方向および列方向に並ぶように、複数の光電変換領域１２がマトリクス状（行列状）に配置されている。 In the solid-state imaging device 1, a part of the plurality of photoelectric conversion regions 12 is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and the other part of the plurality of photoelectric conversion regions 12 is the first. The first epitaxial layer 11b and the second epitaxial layer 11c are formed so as not to straddle. The photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c and the first epitaxial layer 11b and the second epitaxial layer 11c were formed so as not to straddle. A plurality of photoelectric conversion regions 12 are arranged in a matrix (matrix) so that the photoelectric conversion regions 12 are alternately arranged in the row direction and the column direction.
　第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成された光電変換領域１２は、入射光を光電変換する領域であり、同じ導電型のｎ型層（第１の層）４１ａ、ｎ型層（第２の層）４１ｂおよびｎ型層４１ｃ、ｐ+型のホールアキュムレーション層４０並びにｐ型層（ｐウェル）２０から構成される。この光電変換領域１２は、ｎ型層４１ａおよびｐ型層２０が形成された第１のエピタキシャル層１１ｂ上に第２のエピタキシャル層１１ｃを形成した後、第２のエピタキシャル層１１ｃにｎ型層４１ｂ、ｎ型層４１ｃおよびホールアキュムレーション層４０を形成することにより形成される。ｎ型層４１ａは第１のエピタキシャル層１１ｂに形成され、ｎ型層４１ｃは第２のエピタキシャル層１１ｃに形成されている。一方、ｎ型層４１ｂは、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成され、ｎ型層４１ａの全体又は一部と重なっている。ｎ型層４１ａとｎ型層４１ｂとは、電気的に接続されている。この光電変換領域１２は、上層にホールアキュムレーション層４０を備え、下層にｎ型層４１ａ、４１ｂおよび４１ｃならびにｐ型層２０を備えている。 The photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c is a region that photoelectrically converts incident light, and is an n-type layer (first layer) of the same conductivity type. ) 41a, n-type layer (second layer) 41b, n-type layer 41c, p + -type hole accumulation layer 40, and p-type layer (p-well) 20. In the photoelectric conversion region 12, after the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a and the p-type layer 20 are formed, the n-type layer 41b is formed on the second epitaxial layer 11c. The n-type layer 41c and the hole accumulation layer 40 are formed. The n-type layer 41a is formed on the first epitaxial layer 11b, and the n-type layer 41c is formed on the second epitaxial layer 11c. On the other hand, the n-type layer 41b is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and overlaps the whole or a part of the n-type layer 41a. The n-type layer 41a and the n-type layer 41b are electrically connected. The photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer and n- type layers 41 a, 41 b and 41 c and a p-type layer 20 in the lower layer.
　第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がらないで形成された光電変換領域１２は、入射光を光電変換する領域であり、第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がって形成されたｎ型層およびｐ型層２０を含まず、ｎ型層４１ａ、ｎ型層４１ｃ、ｐ型層（ｐウェル）２０ａおよびホールアキュムレーション層４０から構成される。ｐ型層２０は第１のエピタキシャル層１１ｂに形成されるが、ｐ型層２０ａは第２のエピタキシャル層１１ｃに形成される。この光電変換領域１２は、ｎ型層４１ａが形成された第１のエピタキシャル層１１ｂ上に第２のエピタキシャル層１１ｃを形成した後、第２のエピタキシャル層１１ｃにｎ型層４１ｃ、ホールアキュムレーション層４０およびｐ型層２０ａを形成することにより形成される。ｎ型層４１ａとｎ型層４１ｃとは、それぞれ第１のエピタキシャル層１１ｂと第２のエピタキシャル層１１ｃとに跨がらないで離れて形成されており、電気的に分離されている。この光電変換領域１２は、上層にホールアキュムレーション層４０を備え、下層にｎ型層４１ａおよび４１ｃならびにｐ型層２０ａを備えている。 The photoelectric conversion region 12 formed without straddling the first epitaxial layer 11b and the second epitaxial layer 11c is a region for photoelectrically converting incident light, and the first epitaxial layer 11b and the second epitaxial layer. The n-type layer and the p-type layer 20 formed so as to straddle the layer 11c are not included, and the n-type layer 41a, the n-type layer 41c, the p-type layer (p-well) 20a, and the hole accumulation layer 40 are included. The p-type layer 20 is formed on the first epitaxial layer 11b, while the p-type layer 20a is formed on the second epitaxial layer 11c. In the photoelectric conversion region 12, the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a is formed, and then the n-type layer 41c and the hole accumulation layer 40 are formed on the second epitaxial layer 11c. And p-type layer 20a. The n-type layer 41a and the n-type layer 41c are formed so as not to straddle the first epitaxial layer 11b and the second epitaxial layer 11c, respectively, and are electrically separated. The photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer, and includes n- type layers 41a and 41c and a p-type layer 20a in the lower layer.
　第１のエピタキシャル層１１ｂの表面上には、ｎ型層４１ａとｎ型層４１ｂとが第２のエピタキシャル層１１ｃを表面からみたとき重なる位置にあるようにｎ型層４１ｂの形成でその位置を決定するために用いられる工程位置合わせマークが形成されている。第２のエピタキシャル層１１ｃの膜厚は５μｍ以下である。 On the surface of the first epitaxial layer 11b, the n-type layer 41b is formed so that the n-type layer 41a and the n-type layer 41b overlap each other when the second epitaxial layer 11c is viewed from the surface. A process alignment mark used for determination is formed. The film thickness of the second epitaxial layer 11c is 5 μm or less.
　第１のエピタキシャル層１１ｂは、例えば３～５μｍの膜厚で形成されている。また第２のエピタキシャル層１１ｃは、例えば１～３μｍの膜厚で形成されている。第１のエピタキシャル層１１ｂおよび第２のエピタキシャル層１１ｃは、その抵抗値がたとえばｎ型層で０．１～１００Ω・ｃｍとなるように形成されている。 The first epitaxial layer 11b is formed with a film thickness of 3 to 5 μm, for example. The second epitaxial layer 11c is formed with a film thickness of, for example, 1 to 3 μm. The first epitaxial layer 11b and the second epitaxial layer 11c are formed so that their resistance values are, for example, 0.1 to 100 Ω · cm for an n-type layer.
　光電変換領域１２の側方には、画素分離領域（画素水平分離領域）１８、つまり読み出しゲート１５、転送部（垂直転送部）１６、およびｐ型層１８ｂが形成されている。転送部１６は、その上層にｎ型層４２を備え、その下層にｐ型層１８ａおよび１８ｃを備えている。光電変換領域１２の下部には、垂直オーバーフロードレインを形成するｐ型層２０および２０ａが形成されている。転送部１６に隣接して、ｐ型層１８ｂが形成されている。 On the side of the photoelectric conversion region 12, a pixel separation region (pixel horizontal separation region) 18, that is, a readout gate 15, a transfer unit (vertical transfer unit) 16, and a p-type layer 18b are formed. The transfer unit 16 includes an n-type layer 42 in the upper layer and p- type layers 18a and 18c in the lower layer. Under the photoelectric conversion region 12, p- type layers 20 and 20a that form a vertical overflow drain are formed. A p-type layer 18 b is formed adjacent to the transfer unit 16.
　光電変換領域１２の上層のホールアキュムレーション層４０上方に、基板１１に進入する入射光の反射を防ぐ反射防止膜３２が形成されている。反射防止膜３２の屈折率は、基板の屈折率より大きく、反射防止膜３２上の層間絶縁膜の屈折率より小さい。 An antireflection film 32 that prevents reflection of incident light entering the substrate 11 is formed above the hole accumulation layer 40 in the upper layer of the photoelectric conversion region 12. The refractive index of the antireflection film 32 is larger than the refractive index of the substrate and smaller than the refractive index of the interlayer insulating film on the antireflection film 32.
　基板１１表面上にはゲート絶縁膜２１が形成され、ゲート絶縁膜２１上には電荷読み出し電極および電荷転送電極となるゲート電極２２が形成されている。ゲート電極２２は、１層構造で形成されているが、２層構造、３層構造、または４層構造で形成されてもよい。このゲート電極２２は、図示したように、読み出しゲート１５および転送部１６の直上に形成されることが好ましい。 A gate insulating film 21 is formed on the surface of the substrate 11, and a gate electrode 22 serving as a charge readout electrode and a charge transfer electrode is formed on the gate insulating film 21. The gate electrode 22 is formed with a one-layer structure, but may be formed with a two-layer structure, a three-layer structure, or a four-layer structure. The gate electrode 22 is preferably formed immediately above the read gate 15 and the transfer unit 16 as shown in the figure.
　ゲート電極２２およびゲート絶縁膜２１を被覆する層間絶縁膜３１が基板１１表面上に形成されている。さらに層間絶縁膜３１とゲート電極２２およびゲート絶縁膜２１との間には、光電変換領域１２上方に開口部が形成された遮光膜３３が形成されている。 An interlayer insulating film 31 covering the gate electrode 22 and the gate insulating film 21 is formed on the surface of the substrate 11. Further, a light shielding film 33 having an opening formed above the photoelectric conversion region 12 is formed between the interlayer insulating film 31 and the gate electrode 22 and the gate insulating film 21.
　以下、本実施の形態に係る固体撮像素子１の製造方法（光電変換領域１２の詳細な製造方法）を図５Ｂ～図５Ｉに示す。図５Ｂ～図５Ｉは、同固体撮像素子１の製造方法における製造工程を示す断面図である。 Hereinafter, a method for manufacturing the solid-state imaging device 1 according to the present embodiment (a detailed method for manufacturing the photoelectric conversion region 12) is shown in FIGS. 5B to 5I. 5B to 5I are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1. FIG.
　まず、図５Ｂに示すように、半導体基板１１ａ上に第１導電型の第１のエピタキシャル層１１ｂを例えば、１１００℃以上の高温での化学気相成長法（たとえば、ＣＶＤ）によって形成する。その後、第１のエピタキシャル層１１ｂ表面上に酸化膜もしくは窒化膜からなる保護膜６０を例えば、５～５０ｎｍの膜厚で形成する。 First, as shown in FIG. 5B, a first conductivity type first epitaxial layer 11b is formed on a semiconductor substrate 11a by, for example, chemical vapor deposition (eg, CVD) at a high temperature of 1100 ° C. or higher. Thereafter, a protective film 60 made of an oxide film or a nitride film is formed on the surface of the first epitaxial layer 11b with a film thickness of 5 to 50 nm, for example.
　次いで、図５Ｂに示すように、リソグフラフィー技術によって、開口部５１が形成されたレジスト膜５０を形成する。レジスト膜５０は、例えば膜厚が１～３μｍ、アスペクト比が１０以下とされる。そして、不純物ドーピング技術（例えば、イオン注入法）によって、第１のエピタキシャル層１１ｂに光電変換領域となるｎ型層４１ａを複数形成する。ｎ型層４１ａは、例えば、アウトドーピングし難いＳｂ等の質量が大きい原子で形成される。なお、ｎ型層４１ａの形成にＡｓ等の軽い原子を使用する場合は、例えば、表面のｎ型不純物濃度が１０-10ａｔｏｍｓ／ｃｍ3未満となるようにｎ型層４１ａを第１のエピタキシャル層１１ｂ内に形成する。 Next, as shown in FIG. 5B, a resist film 50 in which the openings 51 are formed is formed by a lithography fluffy technique. For example, the resist film 50 has a thickness of 1 to 3 μm and an aspect ratio of 10 or less. Then, a plurality of n-type layers 41a serving as photoelectric conversion regions are formed in the first epitaxial layer 11b by an impurity doping technique (for example, ion implantation method). The n-type layer 41a is formed of, for example, atoms having a large mass such as Sb that is difficult to outdope. When light atoms such as As are used to form the n-type layer 41a, for example, the n-type layer 41a is made to be the first epitaxial layer so that the n-type impurity concentration on the surface is less than 10 −10 atoms / cm 3. Formed in layer 11b.
　次いで、図５Ｃに示すように、リソグラフィ技術によって、開口部５１が形成されたレジスト膜５０を第１のエピタキシャル層１１ｂ表面上に形成し、不純物ドーピング技術（たとえば、イオン注入法）によって、複数のｎ型層４１ａを電気的に分離するｐ型層１８ａをｎ型層４１ａの側方（複数のｎ型層４１ａの間）に形成する。 Next, as shown in FIG. 5C, a resist film 50 in which the openings 51 are formed is formed on the surface of the first epitaxial layer 11b by lithography, and a plurality of resist films 50 are formed by impurity doping (for example, ion implantation). A p-type layer 18a that electrically isolates the n-type layer 41a is formed on the side of the n-type layer 41a (between a plurality of n-type layers 41a).
　次いで、図５Ｄに示すように、複数のｎ型層４１ａの一部の上方に開口部５１が形成されたレジスト膜５０を第１のエピタキシャル層１１ｂ表面上に形成する。そして、イオン注入法によってｎ型層４１ａの一部の下方にｐ型層２０を形成した後、保護膜６０をエッチング技術（たとえば、ウエットエッチング）によって除去する。 Next, as shown in FIG. 5D, a resist film 50 having an opening 51 formed above a part of the plurality of n-type layers 41a is formed on the surface of the first epitaxial layer 11b. Then, after forming the p-type layer 20 below a part of the n-type layer 41a by ion implantation, the protective film 60 is removed by an etching technique (for example, wet etching).
　次いで、図５Ｅに示すように、第１のエピタキシャル層１１ｂの表面上に第２のエピタキシャル層１１ｃを例えば、１１００℃以上の高温での化学気相成長法（ＣＶＤ）によって形成する。その後、第２のエピタキシャル層１１ｃ表面上に酸化膜もしくは窒化膜からなる保護膜６１を例えば、５～５０ｎｍの膜厚で形成する。そして、開口部５１が形成されたレジスト膜５０を第２のエピタキシャル層１１ｃ表面上に形成し、不純物ドーピング技術（たとえばイオン注入法）により、第２のエピタキシャル層１１ｃに光電変換領域１２となるｎ型層４１ｃを形成する。 Next, as shown in FIG. 5E, the second epitaxial layer 11c is formed on the surface of the first epitaxial layer 11b by, for example, chemical vapor deposition (CVD) at a high temperature of 1100 ° C. or higher. Thereafter, a protective film 61 made of an oxide film or a nitride film is formed on the surface of the second epitaxial layer 11c with a film thickness of 5 to 50 nm, for example. Then, a resist film 50 having an opening 51 is formed on the surface of the second epitaxial layer 11c, and n which becomes the photoelectric conversion region 12 in the second epitaxial layer 11c by an impurity doping technique (for example, ion implantation method). A mold layer 41c is formed.
　次いで、図５Ｆに示すように、複数のｎ型層４１ｃの一部の上方に開口部５１が形成され、イオン注入の深さに応じた形態を持つレジストマスクを第２のエピタキシャル層１１ｃ表面上に形成する。その後、開口部５１下方のｎ型層４１ｃとｎ型層４１ａとが電気的に接続するように接続層としてｎ型層４１ｂを形成し、深さの異なる光電変換領域１２を有する固体撮像素子１を形成する。このとき、ｎ型層４１ｂの一部又は全体がｎ型層４１ａおよび４１ｃの両方と精度良く重なるように、第１のエピタキシャル層１１ｂ表面上に形成されたアライメントマークを使用する。 Next, as shown in FIG. 5F, an opening 51 is formed above a part of the plurality of n-type layers 41c, and a resist mask having a form corresponding to the depth of ion implantation is formed on the surface of the second epitaxial layer 11c. To form. Thereafter, the n-type layer 41b is formed as a connection layer so that the n-type layer 41c and the n-type layer 41a below the opening 51 are electrically connected, and the solid-state imaging device 1 having the photoelectric conversion regions 12 having different depths. Form. At this time, alignment marks formed on the surface of the first epitaxial layer 11b are used so that a part or the whole of the n-type layer 41b overlaps both the n- type layers 41a and 41c with high accuracy.
　次いで、図５Ｇに示すように、ｎ型層４１ａおよび４１ｃのペアとｎ型層４１ａ、４１ｂおよび４１ｃのペアとの間つまり光電変換領域１２の間に、光電変換領域１２と転送部１６とを電気的に分離するｐ型層である読み出しゲート１５、ならびにｐ型層１８ａ、１８ｂおよび１８ｃの形成をリソグラフィ技術および不純物ドーピング技術によって、例えば、その都度レジストマスクを形成して行う。 Next, as shown in FIG. 5G, between the pair of n- type layers 41a and 41c and the pair of n- type layers 41a, 41b and 41c, that is, between the photoelectric conversion regions 12, the photoelectric conversion region 12 and the transfer unit 16 are connected. The read gate 15 which is a p-type layer to be electrically separated and the p- type layers 18a, 18b and 18c are formed by lithography and impurity doping techniques, for example, by forming a resist mask each time.
　次いで、図５Ｈに示すように、その下方にｎ型層４１ｂが形成されていないｎ型層４１ｃの下方に、既存のリソグラフィ技術と不純物ドーピング技術により、ｐ型層２０ａを形成する。隣り合う光電変換領域１２で光電変換を行う領域の深さが異なるが、ｐ型層２０ａを形成することで、光電変換領域１２の深さに関わらず、光電変換を行う領域から一定の位置にｐ型層が設定される。従って、垂直オーバーフロードレインが画素毎（光電変換領域１２毎）に最適化され、電子シャッター時に印加する電圧を同じにすることが可能となる。 Next, as shown in FIG. 5H, a p-type layer 20a is formed below the n-type layer 41c where the n-type layer 41b is not formed below by an existing lithography technique and impurity doping technique. Although the depth of the area | region which performs photoelectric conversion in the adjacent photoelectric conversion area | region 12 differs, by forming the p-type layer 20a, it is a fixed position from the area | region which performs photoelectric conversion irrespective of the depth of the photoelectric conversion area | region 12. A p-type layer is set. Therefore, the vertical overflow drain is optimized for each pixel (for each photoelectric conversion region 12), and the voltage applied during the electronic shutter can be made the same.
　次いで、図５Ｉに示すように、レジスト膜５０と保護膜６０を除去後、第２のエピタキシャル層１１ｃ表面上にゲート絶縁膜２１、ゲート電極２２および反射防止膜３２等を形成する。 Next, as shown in FIG. 5I, after removing the resist film 50 and the protective film 60, a gate insulating film 21, a gate electrode 22, an antireflection film 32, and the like are formed on the surface of the second epitaxial layer 11c.
　上記製造方法で形成された固体撮像素子１は、第１の実施の形態で説明したような作用効果が得られる固体撮像素子となる。 The solid-state image pickup device 1 formed by the above manufacturing method becomes a solid-state image pickup device that can obtain the effects as described in the first embodiment.
　図６は、固体撮像素子の基板内の光電変換領域を構成するｎ型層の深さ方向（基板表面の法線方向）での不純物濃度分布を示す図である。なお、図６（ａ）は一般的な固体撮像素子における不純物濃度分布を示し、図６（ｂ）は本実施の形態の固体撮像素子１における不純物濃度分布を示している。また、図６において実線は光電変換領域を構成する各ｎ型層のｎ型不純物の濃度分布をそれぞれ示しており、破線はその各ｎ型層のｎ型不純物の濃度を合わせたときの濃度分布を示している。 FIG. 6 is a diagram showing the impurity concentration distribution in the depth direction (normal direction of the substrate surface) of the n-type layer constituting the photoelectric conversion region in the substrate of the solid-state imaging device. 6A shows an impurity concentration distribution in a general solid-state imaging device, and FIG. 6B shows an impurity concentration distribution in the solid-state imaging device 1 of the present embodiment. In FIG. 6, the solid line shows the concentration distribution of the n-type impurity in each n-type layer constituting the photoelectric conversion region, and the broken line shows the concentration distribution when the concentration of the n-type impurity in each n-type layer is combined. Is shown.
　図６（ａ）に示すように、一般的な固体撮像素子では基板の深い位置（図６（ａ）のＣ部分）で不純物濃度分布の広がりが大きいが、図６（ｂ）に示すように、本実施の形態の固体撮像素子１では、基板の深い位置（図６（ｂ）のＤ部分）で不純物濃度分布の広がりが小さい。 As shown in FIG. 6 (a), in a general solid-state imaging device, the spread of the impurity concentration distribution is large at a deep position of the substrate (C portion in FIG. 6 (a)), but as shown in FIG. 6 (b). In the solid-state imaging device 1 of the present embodiment, the spread of the impurity concentration distribution is small at a deep position of the substrate (D portion in FIG. 6B).
　以上、本発明の固体撮像素子について、実施の形態に基づいて説明したが、本発明は、この実施の形態に限定されるものではない。本発明の要旨を逸脱しない範囲内で当業者が思いつく各種変形を施したものも本発明の範囲内に含まれる。また、発明の趣旨を逸脱しない範囲で、複数の実施の形態における各構成要素を任意に組み合わせてもよい。 As described above, the solid-state imaging device of the present invention has been described based on the embodiment. However, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.
　例えば、上記実施の形態において、第１導電型としてｎ型を例示し、第１導電型と逆導電型の第２導電型としてｐ型を例示したが、第１導電型がｐ型であり、第２導電型がｎ型であってもよい。 For example, in the above embodiment, the n-type is exemplified as the first conductivity type, and the p-type is exemplified as the second conductivity type opposite to the first conductivity type. However, the first conductivity type is the p-type, The second conductivity type may be n-type.
　本発明は、固体撮像素子およびその製造方法に好適であり、例えば各種撮像装置の撮像素子という用途に適用するのに好適である。 The present invention is suitable for a solid-state imaging device and a method for manufacturing the same, and is suitable for application to, for example, an imaging device of various imaging apparatuses.
　　１、１０１　　固体撮像素子
　　１１、１１１　　基板
　　１１ａ、１１１ａ　　半導体基板
　　１１ｂ　　第１のエピタキシャル層
　　１１ｃ　　第２のエピタキシャル層
　　１２、１１２　　光電変換領域
　　１５、１１５　　読み出しゲート
　　１６　　転送部
　　１８、１１８　　画素分離領域
　　１８ａ、１８ｂ、１８ｃ、２０、２０ａ、１１８ａ、１１８ｂ　　ｐ型層
　　２１　　ゲート絶縁膜
　　２２、１２２　　ゲート電極
　　３１、１３１　　層間絶縁膜
　　３２、１３２　　反射防止膜
　　３３、１３３　　遮光膜
　　４０、１４０　　ホールアキュムレーション層
　　４１ａ、４１ｂ、４１ｃ、４２、１４２　　ｎ型層
　　５０、１５０　　レジスト膜
　　５１、１３４、１５１　　開口部
　　６０、６１、１６０　　保護膜
　　１１１ｂ、１１１ｃ　　エピタキシャル層
　　１１６　　垂直転送部
　　１２０　　ｐウェル
　　１２１　　絶縁膜
　　１４１　　ｎ+型拡散層 DESCRIPTION OF SYMBOLS 1,101 Solid- state image sensor 11, 111 Substrate 11a, 111a Semiconductor substrate 11b 1st epitaxial layer 11c 2nd epitaxial layer 12, 112 Photoelectric conversion area | region 15,115 Read-out gate 16 Transfer part 18,118 Pixel isolation area 18a, 18b , 18c, 20, 20a, 118a, 118b p-type layer 21 gate insulating film 22, 122 gate electrode 31, 131 interlayer insulating film 32, 132 antireflection film 33, 133 light shielding film 40, 140 hole accumulation layer 41a, 41b, 41c , 42, 142 n- type layer 50, 150 resist film 51, 134, 151 opening 60, 61, 160 protective film 111b, 111c epitaxial layer 116 vertical transfer portion 120 p well 121 insulating film 141 + -Type diffusion layer

Claims (10)

  1. 　入射光を光電変換する複数の光電変換領域と、対応する前記光電変換領域から信号電荷を読み出すための読み出しゲートと、前記読み出しゲートによって読み出された前記信号電荷の転送を行うための転送部とが形成された基板を備え、
    　前記基板は、半導体基板と、前記半導体基板上に形成された第１導電型の第１のエピタキシャル層と、前記第１のエピタキシャル層上に形成された第１導電型の第２のエピタキシャル層とを含み、
    　前記光電変換領域が、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成されている
    　固体撮像素子。     A plurality of photoelectric conversion regions for photoelectrically converting incident light, a read gate for reading signal charges from the corresponding photoelectric conversion region, and a transfer unit for transferring the signal charges read by the read gate; Comprising a substrate formed with
    The substrate includes: a semiconductor substrate; a first conductivity type first epitaxial layer formed on the semiconductor substrate; a first conductivity type second epitaxial layer formed on the first epitaxial layer; Including
    The solid-state imaging device, wherein the photoelectric conversion region is formed across the first epitaxial layer and the second epitaxial layer.
  2. 　前記複数の光電変換領域の一部は、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がらないで前記第２のエピタキシャル層に形成されている
    　請求項１に記載の固体撮像素子。     2. The solid-state imaging device according to claim 1, wherein some of the plurality of photoelectric conversion regions are formed in the second epitaxial layer without straddling the first epitaxial layer and the second epitaxial layer.
  3. 　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成された光電変換領域は、同じ導電型の第１の層および第２の層を含み、前記第１の層が形成された前記第１のエピタキシャル層上に前記第２のエピタキシャル層を形成した後、前記第２のエピタキシャル層に前記第２の層を形成することにより形成される
    　請求項１又は２に記載の固体撮像素子。     The photoelectric conversion region formed across the first epitaxial layer and the second epitaxial layer includes a first layer and a second layer having the same conductivity type, and the first layer is formed. 3. The solid-state imaging according to claim 1, wherein the second epitaxial layer is formed on the first epitaxial layer, and then the second layer is formed on the second epitaxial layer. 4. element.
  4. 　前記第１のエピタキシャル層の表面上には、工程位置合わせマークが形成されている
    　請求項１又は２に記載の固体撮像素子。     The solid-state imaging device according to claim 1, wherein a process alignment mark is formed on the surface of the first epitaxial layer.
  5. 　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成された光電変換領域は、前記第１のエピタキシャル層に形成された第１の層と、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成され、前記第１の層と一部が重なる、前記第１の層と同じ導電型の第２の層とを含む
    　請求項１又は２に記載の固体撮像素子。     The photoelectric conversion region formed across the first epitaxial layer and the second epitaxial layer includes a first layer formed in the first epitaxial layer, a first epitaxial layer, and a first epitaxial layer. 3. The solid according to claim 1, further comprising: a second layer of the same conductivity type as the first layer, which is formed to straddle the two epitaxial layers and partially overlaps the first layer. Image sensor.
  6. 　前記第２のエピタキシャル層の膜厚が、５μｍ以下である
    　請求項１又は２に記載の固体撮像素子。     The solid-state imaging device according to claim 1, wherein a film thickness of the second epitaxial layer is 5 μm or less.
  7. 　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成された光電変換領域は、前記第１のエピタキシャル層に形成された第１導電型と逆導電型の第２導電型のウェルを含む
    　請求項１又は２に記載の固体撮像素子。     The photoelectric conversion region formed across the first epitaxial layer and the second epitaxial layer has a second conductivity type opposite to the first conductivity type formed in the first epitaxial layer. The solid-state imaging device according to claim 1, comprising a well.
  8. 　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成された光電変換領域は、前記第１のエピタキシャル層に形成された第１導電型と逆導電型の第２導電型のウェルを含み、
    　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がらないで形成された光電変換領域は、前記ウェルを含まない
    　請求項２に記載の固体撮像素子。     The photoelectric conversion region formed across the first epitaxial layer and the second epitaxial layer has a second conductivity type opposite to the first conductivity type formed in the first epitaxial layer. Including wells,
    The solid-state imaging device according to claim 2, wherein a photoelectric conversion region formed without straddling the first epitaxial layer and the second epitaxial layer does not include the well.
  9. 　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成された光電変換領域は、前記第１のエピタキシャル層に形成された第１の層と、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成され、前記第１の層と一部が重なる、前記第１の層と同じ導電型の第２の層とを含み、　前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がらないで形成された光電変換領域は、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成された層を含まない
    　請求項２に記載の固体撮像素子。     The photoelectric conversion region formed across the first epitaxial layer and the second epitaxial layer includes a first layer formed in the first epitaxial layer, a first epitaxial layer, and a first epitaxial layer. A second layer of the same conductivity type as the first layer, which is formed across the two epitaxial layers and partially overlaps the first layer, The photoelectric conversion region formed without straddling the two epitaxial layers does not include a layer formed straddling the first epitaxial layer and the second epitaxial layer. Image sensor.
  10. 　前記複数の光電変換領域のそれぞれは、前記第１のエピタキシャル層と第２のエピタキシャル層とに跨がって形成されている
    　請求項１に記載の固体撮像素子。     The solid-state imaging device according to claim 1, wherein each of the plurality of photoelectric conversion regions is formed so as to straddle the first epitaxial layer and the second epitaxial layer.
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