WO2011155182A1 - Elément d'imagerie à semi-conducteurs - Google Patents

Elément d'imagerie à semi-conducteurs Download PDF

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Publication number
WO2011155182A1
WO2011155182A1 PCT/JP2011/003202 JP2011003202W WO2011155182A1 WO 2011155182 A1 WO2011155182 A1 WO 2011155182A1 JP 2011003202 W JP2011003202 W JP 2011003202W WO 2011155182 A1 WO2011155182 A1 WO 2011155182A1
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epitaxial layer
layer
photoelectric conversion
solid
state imaging
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PCT/JP2011/003202
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English (en)
Japanese (ja)
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直人 山田
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers
    • H01L27/14843—Interline transfer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Definitions

  • the present invention relates to a solid-state imaging device, and more particularly to an interlaced type CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device having a light shielding film.
  • CMOS Complementary Metal Oxide Semiconductor
  • Patent Document 1 the imaging region is composed of a photoelectric conversion region, a charge transfer electrode, a charge transfer region, a charge readout electrode, a charge readout region, an element isolation region, and the like.
  • FIG. 7A is a plan layout view of a general solid-state image sensor 101
  • FIG. 7B is a cross-sectional view (cross-sectional view taken along line A-A ′ in FIG. 7A) showing a schematic configuration of the solid-state image sensor 101.
  • epitaxial layers 111b and 111c are formed on a semiconductor substrate 111a, and a photoelectric conversion region 112 is formed in the epitaxial layer 111c.
  • the photoelectric conversion region 112 is composed of a hole accumulation layer 140 made of a p + layer formed in an upper layer, and an n + type diffusion layer 141 and a p well 120 formed in the lower layer.
  • the n + type diffusion layer 141 in the photoelectric conversion region 112 is formed up to a deep position of the epitaxial layer 111c in consideration of the formation of the hole accumulation layer 140 on the surface of the epitaxial layer 111c.
  • the n + -type diffusion layer 141 is not formed up to a position deeper than the film thickness of the epitaxial layer 111c.
  • a vertical transfer unit (vertical register) 116 is formed as a charge transfer region via a read gate (charge read region) 115.
  • the vertical transfer unit 116 includes an n-type layer 142 in the upper layer and a p-type layer 118a in the lower layer. Further, a p-type layer 118b constituting a pixel isolation region 118 that electrically isolates the pixel region (photoelectric conversion region 112) from other pixel regions in the horizontal direction is formed adjacent to the vertical transfer unit 116. .
  • a vertical transfer unit 116 of a pixel (unit cell) including another photoelectric conversion region 112 adjacent to the photoelectric conversion region 112 is formed via a p-type layer 118b.
  • a gate electrode 122 serving as a charge read electrode and a charge transfer electrode is formed via an insulating film 121 serving as a gate oxide film.
  • a light shielding film 133 having an opening 134 provided on the photoelectric conversion region 112 is formed via an interlayer insulating film.
  • An antireflection film 132 is formed in the opening 134, and an interlayer insulating film 131 is formed on the light shielding film 133.
  • FIGS. 7C and 7D are cross-sectional views for explaining a method for forming the solid-state imaging device 101 having the structure of FIGS. 7A and 7B.
  • a p-well 120 is formed in a substrate 111 composed of a semiconductor substrate 111a and epitaxial layers 111b and 111c. Thereafter, a protective film 160 is formed on the surface of the epitaxial layer 111c, a resist film 150 is formed by a lithography technique, and then an opening 151 is formed in the resist film 150.
  • the first conductivity type (n-type) of the photoelectric conversion region 112 is formed on the surface of the epitaxial layer 111c by an existing impurity doping technique (for example, ion implantation method) using the resist film 150 as a mask.
  • An island-like n + -type diffusion layer 141 as a region is formed.
  • the n + -type diffusion layer 141 is formed to a depth of 2 to 4 ⁇ m. The depth to be formed is determined in consideration of up to which range the light on the long wavelength side is photoelectrically converted.
  • ⁇ 550 nm
  • ⁇ 550 nm
  • a resist mask is formed each time by lithography technique and impurity doping technique, and the readout gate 115 having the opposite conductivity type in the photoelectric conversion region 112 (n + type diffusion layer 141), vertical transfer A p-type layer 118 a of the part 116 and a p-type layer 118 b of the pixel isolation region 118 are formed.
  • the lithography technique requires a high aspect ratio resist (for example, a resist film thickness of 6 ⁇ m or more and an aspect ratio of 15 or more) that prevents impurity doping by the ion implantation method. As a result, fine processing variations are likely to occur, and it is difficult to form the photoelectric conversion region 112 with a certain form with high accuracy.
  • Patent Document 1 proposes a structure having color filter groups of the same color on two adjacent pixels having different photoelectric conversion region depths for the purpose of generating an image with a wide dynamic range.
  • Patent Document 1 intends to increase sensitivity by controlling incident energy on the low illuminance side (shadow) and high illuminance side (highlight).
  • shadow low illuminance side
  • high illuminance side high light
  • An object of the present invention is to provide a solid-state imaging device capable of suppressing a decrease in sensitivity associated with a reduction in pixel size.
  • a solid-state imaging device includes a plurality of photoelectric conversion regions that photoelectrically convert incident light, a read gate for reading signal charges from the corresponding photoelectric conversion region, and the read gate by the read gate.
  • a first conductivity type second epitaxial layer formed on the first epitaxial layer, and the photoelectric conversion region is formed across the first epitaxial layer and the second epitaxial layer. It is characterized by that.
  • the first epitaxial layer is formed on the semiconductor substrate, and a part of the photoelectric conversion region is formed in an island shape by the existing lithography technique and impurity doping technique in the first epitaxial layer.
  • a second epitaxial layer is formed on the surface of the layer, and another part of the photoelectric conversion region is formed in an island shape so as to overlap with a part of the island-shaped photoelectric conversion region by the existing lithography technique and impurity doping technique.
  • the depth of the photoelectric conversion region can be arbitrarily set without using an ultra-high energy injection device, and patterning of the photoelectric conversion region can be performed without using a thick film resist having a high aspect ratio. it can. Therefore, the photoelectric conversion region in the imaging area can be processed and formed with high precision.
  • some of the plurality of photoelectric conversion regions may be formed in the second epitaxial layer without straddling the first epitaxial layer and the second epitaxial layer.
  • FIG. 1A is a plan layout diagram of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view (a cross-sectional view taken along line A-A ′ in FIG. 1A) showing a schematic configuration of the solid-state imaging device according to the embodiment.
  • FIG. 2A is a cross-sectional view showing a manufacturing process in the method for manufacturing the solid-state imaging device according to the embodiment.
  • FIG. 2B is a cross-sectional view showing a manufacturing process in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 2C is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 2D is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 2E is a cross-sectional view showing the manufacturing process in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 2F is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3A is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging device according to the embodiment.
  • FIG. 3B is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3C is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3D is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 3E is a cross-sectional view showing the alignment mark forming step in the method of manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 4A is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment.
  • FIG. 4B is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment.
  • FIG. 4A is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to the embodiment.
  • FIG. 4B is a cross-sectional view illustrating a schematic configuration of a modified example of the solid-state imaging device according to
  • FIG. 5A is a cross-sectional view showing a schematic configuration of a solid-state imaging element according to the second embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5C is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5D is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5E is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 5F is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 5G is a cross-sectional view showing a manufacturing step in the method for manufacturing the solid-state imaging element according to the embodiment.
  • FIG. 5H is a cross-sectional view showing a manufacturing step in the manufacturing method of the solid-state imaging element according to the embodiment.
  • FIG. 5I is a cross-sectional view showing the manufacturing process in the method for manufacturing the solid-state imaging device according to the embodiment.
  • FIG. 6 is a diagram illustrating an impurity concentration distribution in the photoelectric conversion region of the solid-state imaging device.
  • FIG. 7A is a plan layout diagram of a general solid-state imaging device.
  • FIG. 7A is a plan layout diagram of a general solid-state imaging device.
  • FIG. 7B is a cross-sectional view (a cross-sectional view taken along the line A-A ′ in FIG. 7A) showing a schematic configuration of a general solid-state imaging device.
  • FIG. 7C is a cross-sectional view for explaining a general method for forming a solid-state imaging device.
  • FIG. 7D is a cross-sectional view for explaining a general method for forming a solid-state imaging element.
  • FIG. 1A is a plan layout view of the solid-state image sensor 1
  • FIG. 1B is a cross-sectional view (cross-sectional view taken along line AA ′ in FIG. 1A) showing a schematic configuration of the solid-state image sensor 1.
  • a semiconductor substrate 11a such as a silicon substrate
  • a conversion region 12 is formed.
  • the substrate 11 includes a semiconductor substrate 11a, a first epitaxial layer 11b formed on the semiconductor substrate 11a, and a second epitaxial layer 11c formed on the first epitaxial layer 11b.
  • a read gate 15 and a transfer unit 16 are formed inside.
  • each of the plurality of photoelectric conversion regions 12 is formed across the first epitaxial layer 11b and the second epitaxial layer 11c.
  • the plurality of photoelectric conversion regions 12 are arranged in a matrix (matrix).
  • the photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c is a region that photoelectrically converts incident light, and is an n-type layer (first layer) of the same conductivity type. ) 41a and n-type layer (second layer) 41b, p + -type hole accumulation layer 40 and p-type layer (p-well) 20.
  • the photoelectric conversion region 12 after the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a and the p-type layer 20 are formed, the n-type layer 41b is formed on the second epitaxial layer 11c. And the hole accumulation layer 40 is formed.
  • the n-type layer 41a is formed only on the first epitaxial layer 11b, but the n-type layer 41b is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and the n-type layer 41b is formed. It overlaps with the whole or a part of the layer 41a.
  • the n-type layer 41a and the n-type layer 41b are electrically connected.
  • the photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer, and includes n-type layers 41 a and 41 b and a p-type layer 20 in the lower layer.
  • the n-type layer 41b is formed so that the n-type layer 41a and the n-type layer 41b overlap each other when the second epitaxial layer 11c is viewed from the surface.
  • a process alignment mark used for determination is formed.
  • the film thickness of the second epitaxial layer 11c is 5 ⁇ m or less. By setting the film thickness to 5 ⁇ m or less, impurities can be injected with high accuracy and can be reliably connected to the first epitaxial layer 11b.
  • the first epitaxial layer 11b is formed with a film thickness of 3 to 5 ⁇ m, for example.
  • the second epitaxial layer 11c is formed with a film thickness of, for example, 1 to 3 ⁇ m.
  • the first epitaxial layer 11b and the second epitaxial layer 11c are formed so that their resistance values are, for example, 0.1 to 100 ⁇ ⁇ cm for an n-type layer.
  • a pixel separation region (pixel horizontal separation region) 18, that is, a readout gate (charge readout region) 15, a transfer unit (vertical transfer unit) 16 as a charge transfer region, and a p-type layer 18b. Is formed.
  • Read gate 15 is provided corresponding to each of the plurality of photoelectric conversion regions 12, and reads signal charges from the corresponding photoelectric conversion regions 12.
  • the transfer unit 16 is a transfer path for transferring the signal charges read by the read gate 15, and includes an n-type layer 42 in the upper layer and a p-type layer 18a in the lower layer.
  • a p-type layer 20 that forms a vertical overflow drain is formed below the photoelectric conversion region 12.
  • Adjacent to the transfer unit 16, a p-type layer 18b for electrically separating the pixel region from other pixel regions in the horizontal direction is formed.
  • An antireflection film 32 that prevents reflection of incident light entering the substrate 11 is formed above the hole accumulation layer 40 in the upper layer of the photoelectric conversion region 12.
  • the refractive index of the antireflection film 32 is larger than the refractive index of the substrate 11 and smaller than the refractive index of the interlayer insulating film on the antireflection film 32.
  • a gate insulating film 21 is formed on the surface of the substrate 11, and a gate electrode 22 serving as a charge readout electrode and a charge transfer electrode is formed on the gate insulating film 21.
  • the gate electrode 22 is formed with a one-layer structure, but may be formed with a two-layer structure, a three-layer structure, or a four-layer structure.
  • the gate electrode 22 is preferably formed immediately above the read gate 15 and the transfer unit 16 as shown in the figure.
  • An interlayer insulating film 31 covering the gate electrode 22 and the gate insulating film 21 is formed on the surface of the substrate 11. Further, a light shielding film 33 having an opening formed above the photoelectric conversion region 12 is formed between the interlayer insulating film 31 and the gate electrode 22 and the gate insulating film 21.
  • FIGS. 2A to 2F are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1.
  • a first conductive type first epitaxial layer 11b is formed on a semiconductor substrate 11a by a chemical vapor deposition method (for example, CVD: Chemical Vapor Deposition) at a high temperature of 1100 ° C. or higher. Form. Thereafter, a protective film 60 made of an oxide film or a nitride film is formed on the surface of the first epitaxial layer 11b with a film thickness of 5 to 50 nm, for example.
  • CVD Chemical Vapor Deposition
  • a resist film 50 in which the openings 51 are formed is formed by a lithography fluffy technique.
  • the resist film 50 has a thickness of 1 to 3 ⁇ m and an aspect ratio of 10 or less.
  • a plurality of n-type layers 41a serving as photoelectric conversion regions are formed in the first epitaxial layer 11b by an impurity doping technique (for example, ion implantation method).
  • the n-type layer 41a is formed of, for example, atoms having a large mass such as Sb that is difficult to outdope.
  • the n-type layer 41a is made to be the first epitaxial layer so that the n-type impurity concentration on the surface is less than 10 ⁇ 10 atoms / cm 3. Formed in layer 11b.
  • the protective film 60 is removed by an etching technique (for example, wet etching).
  • a second epitaxial layer 11c is formed on the surface of the first epitaxial layer 11b by, for example, chemical vapor deposition (for example, CVD) at a high temperature of 1100 ° C. or higher.
  • CVD chemical vapor deposition
  • a protective film 61 made of an oxide film or a nitride film is formed on the surface of the second epitaxial layer 11c with a film thickness of, for example, 5 to 50 nm.
  • a p-type layer (p well) 20 is formed below the n-type layer 41a to be the photoelectric conversion region 12 by a resist mask and an ion implantation method.
  • a vertical overflow drain is formed by the p-type layer 20, and an electronic shutter voltage is set by the p-type layer 20.
  • a resist film 50 having an opening 51 formed on the surface of the second epitaxial layer 11c is formed.
  • the resist film 50 has a thickness of 2 to 5 ⁇ m and an aspect ratio of 10 or less.
  • an n-type layer 41b to be the photoelectric conversion region 12 is formed in the second epitaxial layer 11c by an impurity doping technique (for example, ion implantation method).
  • a plurality of n-type layers 41b are formed so as to correspond to the n-type layer 41a, and are electrically connected to the corresponding n-type layer 41a.
  • an alignment mark formed on the surface of the first epitaxial layer 11b is used.
  • a p-type layer that electrically separates the photoelectric conversion region 12 and the transfer unit 16 between a pair of the plurality of n-type layers 41 a and 41 b, that is, between the plurality of photoelectric conversion regions 12.
  • the read gate 15 and the p-type layers 18a and 18b are formed by a lithography technique and an impurity doping technique, for example, by forming a resist mask each time.
  • the gate insulating film 21, the gate electrode 22, the antireflection film 32, and the like are formed on the surface of the second epitaxial layer 11c.
  • FIGS. 3A to 3E are cross-sectional views of the solid-state imaging device 1 showing the process of forming the alignment mark.
  • the alignment mark is formed in a region around the solid-state imaging device or a position around the semiconductor wafer. There is a mark for alignment in each manufacturing process.
  • a resist film 50 in which an opening 51 is formed is formed, and an n-type layer 41a is formed by using this.
  • a resist film (not shown) having an opening formed only in the alignment mark region is formed.
  • the surface of the first epitaxial layer 11 b and the protective film 60 above the n-type layer 41 a is covered with a resist film 50.
  • the resist film 50 is etched using the protective film 60 as a hard mask by an etching technique (for example, dry etching), and the alignment mark is transferred to the surface of the first epitaxial layer 11b.
  • the step of the alignment mark is 0.2 ⁇ m or more.
  • the surface of the first epitaxial layer 11b is exposed by removing the protective film 60 by an etching technique (for example, wet etching), and then the second epitaxial layer 11c is formed.
  • an etching technique for example, wet etching
  • the first epitaxial layer 11b formed on the semiconductor substrate 11a has the first purpose of suppressing the decrease in sensitivity due to the reduction in pixel size.
  • the island-shaped n-type layer 41a is formed, and the second island-shaped n-type layer 41b is formed on the entire surface of the n-type layer 41a or the second epitaxial layer 11c formed on the surface of the first epitaxial layer 11b. It is formed so as to overlap a part, and is realized by forming the transfer portion 16 and the read gate 15 on the surface of the second epitaxial layer 11c.
  • the photoelectric conversion region 12 is formed at the same time as each epitaxial layer, it is possible to form a fine and deep photoelectric conversion region by the existing lithography technique and impurity doping technique (for example, ion implantation method). Therefore, it is possible to improve sensitivity and dynamic range.
  • impurity doping technique for example, ion implantation method
  • the lateral size of the n-type layer 41b is smaller than that of the n-type layer 41a, and as shown in FIG. 4A, both side ends of the n-type layer 41b are n-type layers. You may be located inside the both ends of 41a. By doing in this way, the photoelectric conversion area
  • the first epitaxial layer 11b may be formed with a conductivity type opposite to that of the photoelectric conversion region 12 (n-type layer 41b).
  • FIG. 5A is a cross-sectional view showing a schematic configuration of the solid-state imaging device 1. Note that the planar layout of the solid-state imaging device 1 according to the present embodiment is the same as FIG. 1A, and FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG.
  • a first conductivity type first epitaxial layer 11b and a first conductivity type second epitaxial layer 11c on the surface of a semiconductor substrate 11a such as a silicon substrate are formed.
  • the photoelectric conversion region 12 is straddled (continuously across the first epitaxial layer 11b and the second epitaxial layer 11c across the boundary between the first epitaxial layer 11b and the second epitaxial layer 11c).
  • a photoelectric conversion region 12 is formed in each of the first epitaxial layer 11b and the second epitaxial layer 11c independently in an island shape.
  • a second pixel comprising are arranged adjacent.
  • a part of the plurality of photoelectric conversion regions 12 is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and the other part of the plurality of photoelectric conversion regions 12 is the first.
  • the first epitaxial layer 11b and the second epitaxial layer 11c are formed so as not to straddle.
  • the photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c and the first epitaxial layer 11b and the second epitaxial layer 11c were formed so as not to straddle.
  • a plurality of photoelectric conversion regions 12 are arranged in a matrix (matrix) so that the photoelectric conversion regions 12 are alternately arranged in the row direction and the column direction.
  • the photoelectric conversion region 12 formed across the first epitaxial layer 11b and the second epitaxial layer 11c is a region that photoelectrically converts incident light, and is an n-type layer (first layer) of the same conductivity type. ) 41a, n-type layer (second layer) 41b, n-type layer 41c, p + -type hole accumulation layer 40, and p-type layer (p-well) 20.
  • the n-type layer 41b is formed on the second epitaxial layer 11c.
  • the n-type layer 41c and the hole accumulation layer 40 are formed.
  • the n-type layer 41a is formed on the first epitaxial layer 11b, and the n-type layer 41c is formed on the second epitaxial layer 11c.
  • the n-type layer 41b is formed across the first epitaxial layer 11b and the second epitaxial layer 11c, and overlaps the whole or a part of the n-type layer 41a.
  • the n-type layer 41a and the n-type layer 41b are electrically connected.
  • the photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer and n-type layers 41 a, 41 b and 41 c and a p-type layer 20 in the lower layer.
  • the photoelectric conversion region 12 formed without straddling the first epitaxial layer 11b and the second epitaxial layer 11c is a region for photoelectrically converting incident light, and the first epitaxial layer 11b and the second epitaxial layer.
  • the n-type layer and the p-type layer 20 formed so as to straddle the layer 11c are not included, and the n-type layer 41a, the n-type layer 41c, the p-type layer (p-well) 20a, and the hole accumulation layer 40 are included.
  • the p-type layer 20 is formed on the first epitaxial layer 11b, while the p-type layer 20a is formed on the second epitaxial layer 11c.
  • the second epitaxial layer 11c is formed on the first epitaxial layer 11b on which the n-type layer 41a is formed, and then the n-type layer 41c and the hole accumulation layer 40 are formed on the second epitaxial layer 11c. And p-type layer 20a.
  • the n-type layer 41a and the n-type layer 41c are formed so as not to straddle the first epitaxial layer 11b and the second epitaxial layer 11c, respectively, and are electrically separated.
  • the photoelectric conversion region 12 includes a hole accumulation layer 40 in the upper layer, and includes n-type layers 41a and 41c and a p-type layer 20a in the lower layer.
  • the n-type layer 41b is formed so that the n-type layer 41a and the n-type layer 41b overlap each other when the second epitaxial layer 11c is viewed from the surface.
  • a process alignment mark used for determination is formed.
  • the film thickness of the second epitaxial layer 11c is 5 ⁇ m or less.
  • the first epitaxial layer 11b is formed with a film thickness of 3 to 5 ⁇ m, for example.
  • the second epitaxial layer 11c is formed with a film thickness of, for example, 1 to 3 ⁇ m.
  • the first epitaxial layer 11b and the second epitaxial layer 11c are formed so that their resistance values are, for example, 0.1 to 100 ⁇ ⁇ cm for an n-type layer.
  • a pixel separation region (pixel horizontal separation region) 18, that is, a readout gate 15, a transfer unit (vertical transfer unit) 16, and a p-type layer 18b are formed on the side of the photoelectric conversion region 12.
  • the transfer unit 16 includes an n-type layer 42 in the upper layer and p-type layers 18a and 18c in the lower layer.
  • p-type layers 20 and 20a that form a vertical overflow drain are formed under the photoelectric conversion region 12.
  • a p-type layer 18 b is formed adjacent to the transfer unit 16.
  • An antireflection film 32 that prevents reflection of incident light entering the substrate 11 is formed above the hole accumulation layer 40 in the upper layer of the photoelectric conversion region 12.
  • the refractive index of the antireflection film 32 is larger than the refractive index of the substrate and smaller than the refractive index of the interlayer insulating film on the antireflection film 32.
  • a gate insulating film 21 is formed on the surface of the substrate 11, and a gate electrode 22 serving as a charge readout electrode and a charge transfer electrode is formed on the gate insulating film 21.
  • the gate electrode 22 is formed with a one-layer structure, but may be formed with a two-layer structure, a three-layer structure, or a four-layer structure.
  • the gate electrode 22 is preferably formed immediately above the read gate 15 and the transfer unit 16 as shown in the figure.
  • An interlayer insulating film 31 covering the gate electrode 22 and the gate insulating film 21 is formed on the surface of the substrate 11. Further, a light shielding film 33 having an opening formed above the photoelectric conversion region 12 is formed between the interlayer insulating film 31 and the gate electrode 22 and the gate insulating film 21.
  • FIGS. 5B to 5I are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1.
  • FIG. 5B to 5I are cross-sectional views showing manufacturing steps in the method for manufacturing the solid-state imaging device 1.
  • a first conductivity type first epitaxial layer 11b is formed on a semiconductor substrate 11a by, for example, chemical vapor deposition (eg, CVD) at a high temperature of 1100 ° C. or higher.
  • a protective film 60 made of an oxide film or a nitride film is formed on the surface of the first epitaxial layer 11b with a film thickness of 5 to 50 nm, for example.
  • a resist film 50 in which the openings 51 are formed is formed by a lithography fluffy technique.
  • the resist film 50 has a thickness of 1 to 3 ⁇ m and an aspect ratio of 10 or less.
  • a plurality of n-type layers 41a serving as photoelectric conversion regions are formed in the first epitaxial layer 11b by an impurity doping technique (for example, ion implantation method).
  • the n-type layer 41a is formed of, for example, atoms having a large mass such as Sb that is difficult to outdope.
  • the n-type layer 41a is made to be the first epitaxial layer so that the n-type impurity concentration on the surface is less than 10 ⁇ 10 atoms / cm 3. Formed in layer 11b.
  • a resist film 50 in which the openings 51 are formed is formed on the surface of the first epitaxial layer 11b by lithography, and a plurality of resist films 50 are formed by impurity doping (for example, ion implantation).
  • a p-type layer 18a that electrically isolates the n-type layer 41a is formed on the side of the n-type layer 41a (between a plurality of n-type layers 41a).
  • a resist film 50 having an opening 51 formed above a part of the plurality of n-type layers 41a is formed on the surface of the first epitaxial layer 11b. Then, after forming the p-type layer 20 below a part of the n-type layer 41a by ion implantation, the protective film 60 is removed by an etching technique (for example, wet etching).
  • the second epitaxial layer 11c is formed on the surface of the first epitaxial layer 11b by, for example, chemical vapor deposition (CVD) at a high temperature of 1100 ° C. or higher.
  • CVD chemical vapor deposition
  • a protective film 61 made of an oxide film or a nitride film is formed on the surface of the second epitaxial layer 11c with a film thickness of 5 to 50 nm, for example.
  • a resist film 50 having an opening 51 is formed on the surface of the second epitaxial layer 11c, and n which becomes the photoelectric conversion region 12 in the second epitaxial layer 11c by an impurity doping technique (for example, ion implantation method).
  • a mold layer 41c is formed.
  • an opening 51 is formed above a part of the plurality of n-type layers 41c, and a resist mask having a form corresponding to the depth of ion implantation is formed on the surface of the second epitaxial layer 11c.
  • the n-type layer 41b is formed as a connection layer so that the n-type layer 41c and the n-type layer 41a below the opening 51 are electrically connected, and the solid-state imaging device 1 having the photoelectric conversion regions 12 having different depths.
  • alignment marks formed on the surface of the first epitaxial layer 11b are used so that a part or the whole of the n-type layer 41b overlaps both the n-type layers 41a and 41c with high accuracy.
  • the read gate 15 which is a p-type layer to be electrically separated and the p-type layers 18a, 18b and 18c are formed by lithography and impurity doping techniques, for example, by forming a resist mask each time.
  • a p-type layer 20a is formed below the n-type layer 41c where the n-type layer 41b is not formed below by an existing lithography technique and impurity doping technique.
  • region 12 differs, by forming the p-type layer 20a, it is a fixed position from the area
  • a p-type layer is set. Therefore, the vertical overflow drain is optimized for each pixel (for each photoelectric conversion region 12), and the voltage applied during the electronic shutter can be made the same.
  • a gate insulating film 21, a gate electrode 22, an antireflection film 32, and the like are formed on the surface of the second epitaxial layer 11c.
  • the solid-state image pickup device 1 formed by the above manufacturing method becomes a solid-state image pickup device that can obtain the effects as described in the first embodiment.
  • FIG. 6 is a diagram showing the impurity concentration distribution in the depth direction (normal direction of the substrate surface) of the n-type layer constituting the photoelectric conversion region in the substrate of the solid-state imaging device.
  • 6A shows an impurity concentration distribution in a general solid-state imaging device
  • FIG. 6B shows an impurity concentration distribution in the solid-state imaging device 1 of the present embodiment.
  • the solid line shows the concentration distribution of the n-type impurity in each n-type layer constituting the photoelectric conversion region
  • the broken line shows the concentration distribution when the concentration of the n-type impurity in each n-type layer is combined. Is shown.
  • the spread of the impurity concentration distribution is large at a deep position of the substrate (C portion in FIG. 6 (a)), but as shown in FIG. 6 (b).
  • the spread of the impurity concentration distribution is small at a deep position of the substrate (D portion in FIG. 6B).
  • the solid-state imaging device of the present invention has been described based on the embodiment.
  • the present invention is not limited to this embodiment.
  • the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
  • the n-type is exemplified as the first conductivity type
  • the p-type is exemplified as the second conductivity type opposite to the first conductivity type.
  • the first conductivity type is the p-type
  • the second conductivity type may be n-type.
  • the present invention is suitable for a solid-state imaging device and a method for manufacturing the same, and is suitable for application to, for example, an imaging device of various imaging apparatuses.

Abstract

La présente invention concerne un élément d'imagerie à semi-conducteurs permettant d'éviter une détérioration de la sensibilité associée à la réduction de la taille de pixel. L'élément d'imagerie à semi-conducteurs comprend : un substrat (11) sur lequel sont formées de multiples régions de conversion photoélectrique (12) pouvant convertir de manière photoélectrique la lumière incidente ; des grilles de lecture (15), pouvant lire les charges de signaux provenant des régions de conversion photoélectrique (12) correspondantes ; et des unités de transfert (16), pouvant transférer les charges de signaux lues par les grilles de lecture (15). Le substrat (11) comprend : un substrat semi-conducteur (11a) ; une première couche épitaxiale (11b) d'un premier type de conductivité formée sur le substrat semi-conducteur (11a) ; et une seconde couche épitaxiale (11c) du premier type de conductivité formée sur la première couche épitaxiale (11b). Chaque région de conversion photoélectrique (12) s'étend à cheval sur la première couche épitaxiale (11b) et sur la seconde couche épitaxiale (11c).
PCT/JP2011/003202 2010-06-11 2011-06-07 Elément d'imagerie à semi-conducteurs WO2011155182A1 (fr)

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JP2001291858A (ja) * 2000-04-04 2001-10-19 Sony Corp 固体撮像素子及びその製造方法
JP2003204057A (ja) * 2002-01-10 2003-07-18 Nikon Corp 背面照射型撮像装置、収差計測装置、位置計測装置、投影露光装置、背面照射型撮像装置の製造方法、およびデバイス製造方法
JP2007036034A (ja) * 2005-07-28 2007-02-08 Fujifilm Corp 固体撮像素子の製造方法及び固体撮像素子
JP2007201267A (ja) * 2006-01-27 2007-08-09 Fujifilm Corp 固体撮像素子およびその製造方法
JP2008546176A (ja) * 2005-05-16 2008-12-18 マイクロン テクノロジー， インク． アンチブルーミングアイソレーションを備えたカラー画素および形成方法
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Publication number Priority date Publication date Assignee Title
JP2001291858A (ja) * 2000-04-04 2001-10-19 Sony Corp 固体撮像素子及びその製造方法
JP2003204057A (ja) * 2002-01-10 2003-07-18 Nikon Corp 背面照射型撮像装置、収差計測装置、位置計測装置、投影露光装置、背面照射型撮像装置の製造方法、およびデバイス製造方法
JP2008546176A (ja) * 2005-05-16 2008-12-18 マイクロン テクノロジー， インク． アンチブルーミングアイソレーションを備えたカラー画素および形成方法
JP2007036034A (ja) * 2005-07-28 2007-02-08 Fujifilm Corp 固体撮像素子の製造方法及び固体撮像素子
JP2007201267A (ja) * 2006-01-27 2007-08-09 Fujifilm Corp 固体撮像素子およびその製造方法
JP2009088286A (ja) * 2007-09-28 2009-04-23 Sony Corp 固体撮像装置とその製造方法、並びにカメラ

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