JP2010251628A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device that suppresses an influence of a noise current due to cracking to improve sensitivity to light in a long-wavelength range, and a method of manufacturing the same. <P>SOLUTION: The solid-state imaging device includes a plurality of pixels each including a photoelectric conversion element 206 formed on a semiconductor substrate made of a first material. The photoelectric conversion element 206 has a first semiconductor portion made of the first material and having a recess or projection portion, and a second semiconductor portion of the same conductivity type with the first semiconductor portion laminated in three dimensions on the recess or projection portion of the first semiconductor portion and made of a second material having smaller band gap energy than the first material. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device in which an imaging region having a plurality of pixels is provided on a semiconductor substrate, and a manufacturing method thereof.

  In recent years, there has been a growing demand for reduction in cell size and higher sensitivity for incident light up to the near-infrared long wavelength region with respect to CCD (Charge Coupled Device) and MOS (Metal Oxide Semiconductor) type solid-state imaging devices. In general, the amount of charge generated in a photodiode depends on the amount of incident light absorbed. In the case of a silicon substrate, light in a wavelength region of 1100 nm or less is absorbed by the substrate. For example, the depth at which the amount of light incident on the substrate surface is halved is 0.32 μm for blue light having a wavelength of 450 nm, 0.80 μm for green light having a wavelength of 550 nm, and 3.0 μm for red light having a wavelength of 700 nm. Thus, the light having a longer wavelength is transmitted to the deep part of the substrate.

  In general, the photodiode region is formed by impurity implantation and diffusion. For this reason, if the photodiode is expanded to the extent that long-wavelength light can be completely absorbed, impurities diffuse in the lateral direction (the direction parallel to the top surface of the substrate). It becomes difficult to expand. As a method for solving the above problems, there is a conventional technique as shown in Patent Document 1.

  FIG. 11 is a cross-sectional view showing a photodiode portion of a conventional solid-state imaging device. As shown in the drawing, the photodiode includes a part of a p-type region 1121, an n-type region (charge storage region) 1112, and an n-type single crystal semiconductor layer 1171. The n-type single crystal semiconductor layer 1171 is made of germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or the like, which has a larger absorption coefficient than silicon. Thus, the thickness of the n-type single crystal semiconductor layer 1171 provided above the silicon substrate 1111 can be reduced as compared with the case where the n-type single crystal semiconductor layer 1171 is formed of silicon. Alternatively, the n-type single crystal semiconductor layer 1171 can be expanded and thickened above the silicon substrate 1111 to improve the sensitivity of the photodiode. In FIG. 11, reference numeral 1122 denotes a p-type region, reference numeral 1113 denotes an n-type region, reference numeral 1125 denotes a p-type region, reference numeral 1141 denotes a transfer electrode, reference numerals 1132, 1135 denote insulating films, reference numeral 1134 denotes a spacer, and reference numeral 1151 denotes light shielding. A film, reference numeral 1152 indicates an opening of the light shielding film 1151.

Japanese Patent No. 2959460

  However, in the conventional solid-state imaging device shown in FIG. 11, materials having different lattice constants are grown on a silicon substrate as a single crystal. Therefore, n increases as the film thickness of the n-type single crystal semiconductor layer 1171 increases in order to improve sensitivity. A crack is likely to occur in the single crystal semiconductor layer 1171. For this reason, when a crack occurs, a large amount of noise current (dark current) is generated even when light is not irradiated due to this crack. This noise current is also generated during light irradiation. In particular, at low illuminance, there is a problem that it is difficult to improve the sensitivity of the solid-state imaging device because the noise charge cancels out the signal charge generated by photoelectric conversion.

  The present invention has been made in view of the above problems, and provides a solid-state imaging device that suppresses the generation of noise current associated with the occurrence of cracks and improves the sensitivity to light in a long wavelength region, and a method for manufacturing the same. For the purpose.

  In order to solve the above problems, a solid-state imaging device of the present invention includes a plurality of pixels including a photoelectric conversion element formed on a semiconductor substrate made of a first material, and the photoelectric conversion element includes the first conversion element. A first semiconductor portion having a concave portion or a convex portion, and a three-dimensionally laminated layer on the concave portion or the convex portion of the first semiconductor portion, and having a band gap larger than that of the first material. The second semiconductor portion is made of a second material with low energy and has the same conductivity type as the first semiconductor portion. The first semiconductor portion may have only a concave portion or only a convex portion, or may have both a concave portion and a convex portion.

  According to this configuration, since the photoelectric conversion element has the fourth semiconductor layer composed of the second material having a band gap energy smaller than that of the first material, the photoelectric conversion element includes only the first material. Compared with the case where it comprises, it can absorb long wavelength light, such as red light, and can also absorb other visible light efficiently. Furthermore, since the fourth semiconductor layer has a three-dimensional shape, the effective thickness of the fourth semiconductor layer with respect to incident light can be reduced without increasing the thickness of the fourth semiconductor layer. 4 can be made thicker than when the semiconductor layer is flat. Therefore, the photoelectric conversion element can absorb light more effectively, and the sensitivity can be improved. In particular, a highly sensitive solid-state imaging device can be realized even when it is difficult to form the fourth semiconductor layer thick due to lattice mismatch between the first material and the second material. In this case, since sensitivity can be improved without increasing the thickness of the fourth semiconductor layer, generation of cracks can be suppressed and generation of noise current can be suppressed.

  The first semiconductor portion has the convex portion, the second semiconductor portion is stacked on the convex portion of the first semiconductor portion, and the photoelectric conversion element is formed on the semiconductor substrate. A part of the first semiconductor layer of the second conductivity type provided, a second semiconductor layer of the second conductivity type provided on a part of the first semiconductor layer, and the second semiconductor layer A third semiconductor layer of a second conductivity type made of the first material selectively provided on the second material, and the second material provided on the second semiconductor layer and the third semiconductor layer; A second semiconductor layer of the second conductivity type, and the first semiconductor portion is composed of the second semiconductor layer and the third semiconductor layer which is the convex portion. The second semiconductor portion may be composed of the fourth semiconductor layer.

  The third semiconductor layer may have a columnar structure, a stripe structure, or a wall-like structure that has a lattice shape in plan view.

  The first semiconductor portion has the recess, the second semiconductor portion is stacked on the recess of the first semiconductor portion, and the photoelectric conversion element is provided on the semiconductor substrate. A first semiconductor layer of a first conductivity type and a second semiconductor layer provided on a part of the first semiconductor layer, the recess is formed in an upper portion thereof, and the second semiconductor portion constituting the first semiconductor portion You may have a semiconductor layer and the 4th semiconductor layer which is provided on the said 2nd semiconductor layer and comprises the said 2nd semiconductor part.

  The concave portion may be formed by selectively etching an upper portion of the second semiconductor layer.

  The concave portion may be a hole shape or a groove shape, and the planar shape may be a lattice shape or a stripe shape.

  The photoelectric conversion element may further include a fifth semiconductor layer of a first conductivity type that covers the fourth semiconductor layer.

The first material may be silicon, and the second material may be Si _x Ge _(1-x) (0 ≦ x <1).

  The manufacturing method of the 1st solid-state imaging device of this invention is a manufacturing method of the solid-state imaging device provided with multiple pixels containing the photoelectric conversion element formed on the semiconductor substrate which consists of a 1st material, Comprising: The said semiconductor substrate (A) forming a first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer in a region of the semiconductor substrate located on the first semiconductor layer. A step (b) of forming an insulating film having one or more openings on the second semiconductor layer, and a step located in the opening of the second semiconductor layer A step (d) of selectively epitaxially growing the first material on the region using the insulating film as a mask to form a third semiconductor layer of a second conductivity type; and after removing the insulating film, The first material on the second semiconductor layer and the third semiconductor layer Rimobandogyappuenerugi grown epitaxially small second material, and a fourth semiconductor layer of the second conductivity type and a step (e) to form a three-dimensional shape.

  According to this method, since the three-dimensional fourth semiconductor layer can be formed on the third semiconductor layer, the effective film thickness of the fourth semiconductor layer with respect to incident light can be increased. Therefore, it is possible to manufacture a solid-state imaging device with high sensitivity and reduced generation of noise current due to crystal defects.

  A second method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device including a plurality of pixels including photoelectric conversion elements formed on a semiconductor substrate made of a first material, the semiconductor substrate (A) forming a first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer in a region of the semiconductor substrate located on the first semiconductor layer. Forming a step (b) of forming the insulating film having one or more openings on the second semiconductor layer, and using the insulating film as a mask, A step (d) of forming a groove-shaped recess in the upper portion of the second semiconductor layer by selectively etching a portion of the upper portion located in the opening, and after removing the insulating film, On the upper surface of the second semiconductor layer including the recess, there is a barrier than the first material. A second material de gap energy is smaller is epitaxially grown, and a fourth semiconductor layer of the second conductivity type and a step (e) to form a three-dimensional shape.

  According to this method, the fourth semiconductor layer having a three-dimensional shape can be formed on the second semiconductor layer having the recess formed in the upper portion, so that the effective film thickness of the fourth semiconductor layer with respect to incident light is increased. The solid-state imaging device can be manufactured with high sensitivity and reduced generation of noise current due to crystal defects.

  In addition, the shape of the longitudinal direction cross section of each recessed part is not specifically limited, For example, V shape may be sufficient and U shape etc. may be sufficient.

  According to the solid-state imaging device and the method for manufacturing the same of the present invention, the photoelectric conversion element has the fourth semiconductor layer composed of the second material having a band gap energy smaller than that of the first material. Compared to the case where the conversion element is composed of only the first material, it is possible to absorb light having a long wavelength, such as red light, and also to efficiently absorb other visible light. Further, since the fourth semiconductor layer has a three-dimensional shape, the effective thickness of the fourth semiconductor layer with respect to incident light is increased without increasing the thickness of the fourth semiconductor layer. be able to. Therefore, the photoelectric conversion element can absorb light more effectively. Therefore, it is possible to improve the sensitivity to light in the long wavelength region while suppressing the generation of cracks in the fourth semiconductor layer and suppressing the generation of noise current.

It is a figure which shows an example of the circuit structure of the MOS type solid-state imaging device which concerns on 1st Embodiment. It is sectional drawing which shows an example of a part of pixel of the solid-state imaging device which concerns on 1st Embodiment. It is a figure which shows the wavelength dependence of the absorption coefficient of Si, SiGe (Ge composition ratio 40%), and Ge. It is a figure which shows the relationship between Ge composition of a semiconductor layer, and critical film thickness in the case of forming a desired semiconductor layer on a Si layer. (A)-(c) is sectional drawing which shows the manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. (A)-(c) is sectional drawing which shows the manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. (A)-(c) is sectional drawing which shows the manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. It is sectional drawing which shows an example of a part of pixel of the solid-state imaging device which concerns on 2nd Embodiment. (A)-(d) is sectional drawing which shows the manufacturing process of the solid-state imaging device which concerns on 2nd Embodiment. It is sectional drawing which shows a part of pixel of the solid-state imaging device which concerns on 3rd Embodiment. It is sectional drawing which shows the photodiode part of the conventional solid-state imaging device.

  As will be described below, the solid-state imaging device of the present invention is characterized by the configuration of a photoelectric conversion unit such as a photodiode in a pixel, and the circuit configuration thereof is a circuit of a general MOS type image sensor. Configuration can be applied. In this specification, “solid-state imaging device” refers to a device that includes a photoelectric conversion element provided on a semiconductor chip and outputs an image signal to the outside. It refers to an imaging device including a solid-state imaging device such as a still camera, a digital video camera, a mobile phone camera, and a surveillance camera.

(First embodiment)
-Circuit configuration of solid-state imaging device-
FIG. 1 is a diagram illustrating an example of a circuit configuration of a MOS type solid-state imaging device according to the first embodiment of the present invention.

  As shown in the figure, the solid-state imaging device of this embodiment includes an imaging region 202 in which a plurality of pixels 201 are arranged in a matrix, a vertical shift register 203 for selecting pixels, and an output signal line 204. And a horizontal shift register 205 for transmitting a signal output from the pixel 201. The pixel 201 includes, for example, a photoelectric conversion element 206 which is a photodiode, a transfer transistor 207 for transferring charges generated in the photoelectric conversion element 206 to a floating diffusion portion (FD portion), and a charge signal accumulated in the FD portion. Amplifying transistor 208 that amplifies and outputs to output signal line 204, one end connected to power supply voltage supply unit 209, reset transistor 210 that resets the state of the FD unit, and a signal amplified by amplification transistor 208 are output signal lines And a selection transistor 211 for controlling whether or not to output to 204.

  The gate electrode of the transfer transistor 207, the gate electrode of the reset transistor 210, and the gate electrode of the selection transistor 211 are connected to output pulse lines 212, 213, and 214 controlled by the vertical shift register 203, respectively. Note that this is an example of a pixel, and any circuit configuration in which at least one photoelectric conversion element 206 is disposed in the pixel can be used in the solid-state imaging device of the present invention. Further, the peripheral circuit (vertical shift register 203, horizontal shift register 205, signal output circuit, column amplifier, etc.) is the same as the imaging region 202 by applying the structure of the photoelectric conversion element 206 of this embodiment to the MOS type solid-state imaging device. Since it can be provided on the chip, the area can be reduced and the signal processing time can be shortened. However, it can also be applied to a CCD solid-state imaging device.

-Configuration of solid-state imaging device-
FIG. 2 is a cross-sectional view illustrating an example of a part of a pixel of the solid-state imaging device according to the first embodiment of the present invention. Here, a cross section passing through the photoelectric conversion element 206, the gate electrode 10 of the transfer transistor 207, and the FD portion 11 is shown.

  The solid-state imaging device of the present embodiment includes a plurality of pixels including the photoelectric conversion elements 206 formed on the semiconductor substrate 12a made of the first material (for example, silicon in the present embodiment). The photoelectric conversion element 206 is made of a first material, and is stacked in a three-dimensional manner on a first semiconductor portion having a concave portion or a convex portion, and on the concave portion or the convex portion of the first semiconductor portion. And a second semiconductor portion having the same conductivity type as the first semiconductor portion. The second semiconductor portion is made of a second material (eg, silicon germanium or germanium in this embodiment) having a smaller band gap energy. Here, the small band gap energy of the second material means that the absorption coefficient of light in the second material is larger than the absorption coefficient of the first material. Further, the first semiconductor portion may have only a concave portion or only a convex portion, or may have both a concave portion and a convex portion.

  Note that in this specification, the “semiconductor substrate 12 a” refers to a substrate (wafer) before performing a process such as ion implantation, and the “substrate 12” is located below the first semiconductor layer 13, and the semiconductor substrate 12 a. The part which has not received implantation of impurities shall be pointed out.

  In the example shown in FIG. 2, the first semiconductor portion is composed of a second semiconductor layer 14 and a third semiconductor layer 15, of which the third semiconductor layer 15 constitutes a convex portion. The second semiconductor portion is constituted by the fourth semiconductor layer 16. Next, the configuration of the solid-state imaging device will be described more specifically.

As shown in FIG. 2, in the pixel of the solid-state imaging device according to the present embodiment, a photoelectric conversion element 206 is formed on a substrate 12 made of, for example, silicon. The photoelectric conversion element 206 includes a part of the p ⁻ -type first semiconductor layer 13 provided on the substrate 12 and an n-type second semiconductor layer provided on a part of the first semiconductor layer 13. 14, the n-type third semiconductor layer 15 provided on the second semiconductor layer 14, the upper surface of the second semiconductor layer 14, the upper surface of the third semiconductor layer 15, and the side surface. The n-type fourth semiconductor layer 16 made of, for example, single crystal Si _x Ge _(1-x) (0 ≦ x <1).

  The third semiconductor layer 15 constituting the convex portion has a quadrilateral shape in the longitudinal section shown in FIG. 2, but has a columnar structure, a stripe structure, or a wall-like structure that is a lattice shape in plan view. .

The impurity concentration of the first semiconductor layer 13 is about 1 × 10 ¹³ to 1 × 10 ¹⁷ (pieces / cm ³ ), and the second semiconductor layer 14, the third semiconductor layer 15, and the fourth semiconductor layer 16 The impurity concentration is about 1 × 10 ¹³ to 1 × 10 ¹⁸ (pieces / cm ³ ).

  The lower side surface of the second semiconductor layer 14 is in contact with the p-type stopper layers 17 and 19, and the upper side surface of the second semiconductor layer 14 is the element isolation region 18 having the STI structure and the p-type stopper layer 19a. Surrounded by

Further, an impurity diffusion layer (not shown), a gate insulating film (not shown), and the gate electrode 10 are provided on the p-type surface layer 31 formed on the p-type stopper layer 19a. A transfer transistor 207 is provided. The side surface and the bottom surface of the element isolation region 18 are covered with a thin p ⁺ type sidewall layer 30. A gate wiring 20 made of the same polysilicon as the gate electrode 10 is provided on the element isolation region 18. A silicon oxide film 21 is provided on the side surfaces of the gate electrode 10 and the gate wiring 20, and a silicon oxide film 22 is provided on the photoelectric conversion element 206 and the silicon oxide film 21. A first interlayer insulating film 23 and a second interlayer insulating film 24 are respectively provided on the silicon oxide film 22 and the gate wiring 20.

  Further, in the solid-state imaging device, a contact 25 that is connected to the gate electrode 10 and penetrates the first interlayer insulating film 23, and aluminum (Al) that is connected to the contact 25 and is disposed on the first interlayer insulating film 23. ) And the like, a contact 27 connected to the wiring 26 and penetrating the second interlayer insulating film 24, a wiring 28 connected to the contact 27 and disposed on the second interlayer insulating film 24, A protective film 29 extending at least from the wiring 28 to the second interlayer insulating film 24 is provided.

  The effect of the solid-state imaging device of the present embodiment having the above configuration will be described.

  When light enters the photoelectric conversion element 206, holes and electrons are generated, and charges (electrons) corresponding to the amount of incident light are stored in the pn junction capacitance formed by the depletion layer. Here, the depletion layer is formed by the junction of the p-type stopper layers 19 and 19a, the first semiconductor layer 13 and the sidewall layer 30, and the n-type second semiconductor layer 14, respectively.

  In the solid-state imaging device of the present embodiment, the Ge composition ratio of the fourth semiconductor layer 16 can be set arbitrarily, but by increasing the Ge composition ratio, light having a wavelength up to about 1800 nm can be absorbed. In this specification, the “Ge composition ratio” refers to the ratio of Ge atoms to the atoms (excluding impurity atoms) constituting the semiconductor layer.

  FIG. 3 is a diagram showing the wavelength dependence of absorption coefficients of Si, SiGe (Ge composition ratio 40%), and Ge. As shown in the figure, the absorption coefficient of SiGe and Ge is larger than the absorption coefficient of silicon for light having a wavelength that can be absorbed by Si. Therefore, in the photoelectric conversion element 206 of the present embodiment having the fourth semiconductor layer 16 made of SiGe or Ge, the sensitivity is very high as compared with the case where the photoelectric conversion element is formed only of Si. In particular, the sensitivity to light in the long wavelength region is greatly improved as compared with the case of using Si. Single-crystal SiGe and Ge can be formed more easily than Si by using a CVD (Chemical Vapor Deposition) method. Further, SiGe or Ge formed on a semiconductor layer made of Si can be selectively grown only in a desired region by using a mask.

  Here, the thickness of the fourth semiconductor layer 16 can be arbitrarily set. However, in terms of light receiving sensitivity, a thicker layer is preferable because the number of charges generated by light absorption can be increased. However, although the Ge composition ratio of the fourth semiconductor layer 16 is not particularly limited, the light receiving efficiency is improved as the Ge composition ratio is increased, but the silicon constituting the second semiconductor layer 14 and the third semiconductor layer 15 is increased. The difference between the lattice constants increases and crystal defects increase.

  FIG. 4 is a diagram showing the relationship between the Ge composition of the semiconductor layer and the critical film thickness when a desired semiconductor layer is formed on the Si layer. The crosses in the figure indicate that crystal defects can occur. As can be seen from FIG. 4, when the film thickness of the fourth semiconductor layer 16 exceeds the critical film thickness at the Ge composition ratio of the fourth semiconductor layer 16, cracks due to crystal defects occur and noise current is generated. Therefore, the sensitivity cannot be sufficiently improved. The critical film thickness decreases as the Ge composition ratio increases. For example, when the Ge composition ratio is 20%, the critical film thickness is about 200 nm, whereas when the Ge composition ratio is 100%, the critical film thickness is about 200 nm. 1 nm. Therefore, the film thickness of the fourth semiconductor layer 16 is preferably equal to or less than the critical film thickness in the Ge composition ratio of the fourth semiconductor layer 16.

  In the solid-state imaging device of the present embodiment, the fourth semiconductor layer 16 is formed in a three-dimensional shape on the third semiconductor layer 15 and the upper surface of the second semiconductor layer 14 constituting the convex portion. Since light from the outside is incident in a vertical direction or an oblique direction with respect to the substrate surface of the semiconductor substrate 12a, the fourth semiconductor layer 16 through which the light passes compared to the case where the fourth semiconductor layer 16 is made flat. The effective film thickness can be increased. For example, when light perpendicular to the substrate surface of the semiconductor substrate 12 a is incident on a portion of the fourth semiconductor layer 16 formed on the side surface of the third semiconductor layer 15, The height of the portion is an effective film thickness. In the case shown in FIG. 2, the height of the portion of the fourth semiconductor layer 16 is substantially equal to the thickness of the third semiconductor layer 15.

  For the above reason, even when the film thickness of the fourth semiconductor layer 16 having a large light absorption coefficient is limited, the fourth semiconductor layer is compared with the case where the fourth semiconductor layer 16 is formed flat. 16 can greatly increase the amount of light absorbed. For this reason, even when the film thickness of the fourth semiconductor layer 16 is less than or equal to the critical film thickness, it is possible to increase the amount of light absorption in the photoelectric conversion element 206 as compared with the conventional solid-state imaging device, so that the generation of cracks is suppressed, The sensitivity of the photoelectric conversion element 206 can be improved without generating noise current. In particular, the sensitivity to visible light in the long wavelength region and light in the infrared region can be significantly improved.

  Note that the third semiconductor layer 15 may have one or more columnar structures, a stripe structure, or a wall-like structure that has a lattice shape in plan view as described above, but is formed in at least a convex shape. If so, the fourth semiconductor layer 16 covering this can be made into a three-dimensional shape. The longitudinal section of the fourth semiconductor layer 16 is not limited to a quadrilateral shape. Further, the amount of light absorption in the fourth semiconductor layer 16 can be increased by increasing the thickness of the third semiconductor layer 15 or increasing the number of columnar structures. The sensitivity of the photoelectric conversion element 206 can be adjusted without changing the film thickness. The thickness of the third semiconductor layer 15 can be determined according to the required sensitivity.

  Note that in the case where the third semiconductor layer 15 has a plurality of columnar structures or the like, the distance between the third semiconductor layers can be determined by the thickness of the fourth semiconductor layer 16. For example, when the Ge composition ratio is 20% and the thickness of the fourth semiconductor layer 16 is about 200 nm, which is equal to the critical film thickness, the third semiconductor layers 15 are spaced apart from each other by about 400 nm or more. Preferably formed on a layer. In this way, the proportion of the portion where the effective thickness of the fourth semiconductor layer 16 is larger than the absorption length of incident light increases, and the sensitivity of the photoelectric conversion element 206 can be further improved. Here, “light absorption length” refers to a depth at which the intensity of incident light attenuates to 1 / e (e is a natural logarithm).

-Manufacturing method of solid-state imaging device-
Next, a method for manufacturing the solid-state imaging device according to the first embodiment shown in FIG. 2 will be described with reference to the drawings.

  FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 7A to 7C are cross-sectional views illustrating manufacturing processes of the solid-state imaging device according to the first embodiment. is there.

  First, as shown in FIG. 5A, a pad insulating film 301 made of a silicon oxide film having a thickness of about 1 nm to 50 nm and a silicon nitride film having a thickness of 50 nm to 400 nm on a semiconductor substrate 12a made of silicon or the like. An oxidation resistant film 302 made of the like is sequentially formed. Next, a resist (not shown) having an opening in a predetermined region is formed over the pad insulating film 301 and the oxidation resistant film 302, and etching is performed using the resist as a mask, whereby the pad insulating film 301 and the oxidation resistant film are formed. A part of the film 302 is selectively removed to form an opening exposing a predetermined region on the upper surface of the semiconductor substrate 12a, and then the resist is removed. Here, the resist may be left without being removed. In the method of the present embodiment, silicon nitride is used as the material of the oxidation resistant film 302 that is a hard mask, but silicon oxide may be used as the material of the hard mask. Further, a resist film may be used instead of the oxidation resistant film 302.

Subsequently, as shown in FIG. 5B, after forming a groove in the semiconductor substrate 12a using dry etching using the oxidation resistant film 302 as a mask, a p ⁺ -type sidewall layer 30 is formed by ion implantation. . Next, an insulating film is deposited on the entire surface of the substrate including the trench, the insulating film formed on the oxidation resistant film 302 is removed, and then the oxidation resistant film 302 is removed by etching.

  Next, as shown in FIG. 5C, an element isolation region 18 having a general STI structure is formed by embedding a silicon oxide film or the like in the trench. Next, a resist having an opening in a desired region is formed using a lithography method, and the first semiconductor layer 13 and the second semiconductor layer 14 are formed using these resists as appropriate.

  Next, as shown in FIG. 6A, a resist having an opening in a desired region is formed using a lithography method, and p-type stopper layers 17, 19, 19a, p are appropriately used using these resists. A type surface layer 31 and an FD portion 11 containing n-type impurities are formed in the semiconductor substrate 12a by ion implantation. After these ion implantations, the resist is removed.

  Subsequently, as shown in FIG. 6B, a gate electrode 10 for depositing a polysilicon film on the semiconductor substrate 12a and performing patterning to transfer charges generated by photoelectric conversion to the FD portion 11, Gate wiring 20 is formed. Next, a silicon oxide film 21 having a thickness of about 100 nm having an opening in a region for forming a photoelectric conversion element is formed on the semiconductor substrate 12a, the gate electrode 10, and the gate wiring 20 by using a lithography method and an etching method. . Here, in the silicon oxide film 21, the width of the opening provided on the second semiconductor layer 14 is about 200 nm, and the width of the remaining film is about 200 nm.

  Next, as shown in FIG. 6C, Si is selectively epitaxially grown on the second semiconductor layer 14 in the opening of the silicon oxide film 21 by, for example, the CVD method to form the third semiconductor layer 15. . Here, the third semiconductor layer 15 has one or more columnar structures having a quadrilateral cross section. However, the third semiconductor layer 15 may have a stripe structure or a wall-like structure that is a lattice shape in plan view. Only one third semiconductor layer 15 having a columnar structure may be provided on the second semiconductor layer 14. Further, the thickness of the third semiconductor layer 15 and the distance between the third semiconductor layers 15 adjacent to each other depend on the design value of the thickness of the fourth semiconductor layer 16. In the example shown in FIG. 6C, the shape of the third semiconductor layer 15 is columnar, the thickness is about 500 nm, and the interval is about 200 nm. However, the present invention is not limited to this.

  Next, as shown in FIG. 7A, a portion of the silicon oxide film 21 located on the region for forming the photoelectric conversion element is removed by using a lithography method and an etching method, and the second semiconductor is removed. N-type SiGe or Ge is selectively epitaxially grown by, for example, a CVD method so as to cover the layer 14 and the third semiconductor layer 15 to form the fourth semiconductor layer 16. Thus, a photoelectric conversion element 206 having a part of the first semiconductor layer 13, the second semiconductor layer 14, the third semiconductor layer 15, and the fourth semiconductor layer 16 is formed. The thickness of the fourth semiconductor layer 16 is, for example, about 100 to 200 nm when the Ge composition ratio is 20%. Here, although the preferable film thickness range of the fourth semiconductor layer 16 varies depending on the Ge composition ratio of the fourth semiconductor layer 16, the fourth semiconductor layer 16 is at least thick enough not to exceed the critical film thickness. Good.

In the CVD method used in this step, the substrate temperature is heated to about 400 ° C. or more and 700 ° C. or less, and Si ₂ H ₆ gas and GeH ₄ are mixed to have a desired composition to epitaxially grow the semiconductor layer. For example, if the Ge composition ratio is 25%, the source gas may be supplied into the apparatus so that Si ₂ H ₆ / GeH ₄ = 0.29. Incidentally, when the conductivity type of the semiconductor layer to the p-type, the incorporation of B ₂ H ₆ gas during growth of the semiconductor layer. Further, when the conductivity type of the semiconductor layer is n-type, PH ₃ gas may be mixed during the growth of the semiconductor layer. The third semiconductor layer 15 and the fourth semiconductor layer 16 are formed by the CVD method performed under the above conditions.

  Subsequently, as shown in FIG. 7B, the entire upper surface of the substrate including the fourth semiconductor layer 16 (the solid-state imaging device under fabrication) is covered with the silicon oxide film 22 and is included in the fourth semiconductor layer 16. This prevents Ge from diffusing into the transistor portion (transfer transistor 207 and the like) and peripheral circuits.

  Next, as shown in FIG. 7C, the silicon oxide film 22 is planarized by etch back or CMP, and then the upper surfaces of the gate electrode 10 and the gate wiring 20 are exposed by a lithography method and an etching method. Then, a silicide layer is formed on the gate electrode 10 and the gate wiring 20. Thereafter, a first interlayer insulating film 23 is formed by a CVD method or the like. Next, the upper surface of the first interlayer insulating film 23 is planarized by CMP (Chemical Mechanical Polishing). Then, the resist is patterned using a lithography method, and a contact hole is formed by a dry etching method using the resist. Next, after a contact 25 is formed by embedding a metal such as tungsten in the contact hole by a known method, the upper surface of the contact 25 is flattened by a CMP method. Then, after forming a metal film made of aluminum or the like on the first interlayer insulating film 23, the metal film is patterned using a lithography method and a dry etching method, thereby forming the wiring 26.

  Thereafter, when it is desired to increase the number of wiring layers, an interlayer insulating film, contacts and wiring are formed by the same method as described above, and finally a pad region (not shown) made of a conductor such as metal is formed. The film is formed by lithography and dry etching. As described above, the solid-state imaging device of the present embodiment is manufactured.

  If the wirings 26 and 28 (see FIG. 2) are copper wirings, the wirings 26 and 28 can be formed using a general damascene process or a dual damascene process.

(Second Embodiment)
FIG. 8 is a cross-sectional view showing an example of a part of a pixel of a solid-state imaging device according to the second embodiment of the present invention. Here, a cross section passing through the photoelectric conversion element 206, the gate electrode 10 of the transfer transistor 207, and the FD portion 11 is shown.

  The solid-state imaging device of the present embodiment includes a plurality of pixels including the photoelectric conversion element 206 formed on the semiconductor substrate 12a made of the first material (for example, Si in the present embodiment). The photoelectric conversion element 206 is made of a first material, is stacked in a three-dimensional manner on a first semiconductor portion having a recess, and a recess in the first semiconductor portion, and has a lower band gap energy than the first material. It is made of a second material (for example, SiGe or Ge in the present embodiment), and has a second semiconductor portion having the same conductivity type as the first semiconductor portion.

  In the example shown in FIG. 8, the first semiconductor portion is constituted by the second semiconductor layer 14, and the concave portion is formed on the second semiconductor layer 14. The second semiconductor portion is composed of the fourth semiconductor layer 16. Next, the configuration of the solid-state imaging device will be described more specifically.

As shown in FIG. 8, in the pixel of the solid-state imaging device according to the second embodiment, a photoelectric conversion element 206 is formed on a substrate 12 made of silicon. The photoelectric conversion element 206 includes a part of the p ⁻ -type first semiconductor layer 13 provided on the substrate 12 and an n-type second semiconductor layer provided on a part of the first semiconductor layer 13. 14 and an n-type fourth semiconductor layer 16 provided on the upper surface of the second semiconductor layer 14 and made of, for example, single-crystal Si _x Ge _(1-x) (0 ≦ x <1). ing. However, the fourth semiconductor layer 16 may contain carbon as necessary.

The impurity concentration of the second semiconductor layer 14 and the fourth semiconductor layer 16 is about 1 × 10 ¹³ to 1 × 10 ¹⁸ (pieces / cm ³ ). The impurity concentration of the first semiconductor layer 13 is about 1 × 10 ¹³ to 1 × 10 ¹⁷ (pieces / cm ³ ).

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device according to the first embodiment in that a concave portion is formed on the second semiconductor layer 14 and the fourth semiconductor layer 16 covering the concave portion is provided. It is formed in a three-dimensional shape. This effect will be described later. The concave portion may be a hole shape or a groove shape, and the planar shape may be a lattice shape or a stripe shape.

  The lower side surface of the second semiconductor layer 14 is in contact with the p-type stopper layers 17 and 19, and the upper side surface of the second semiconductor layer 14 is the element isolation region 18 having the STI structure and the p-type stopper layer 19a. Surrounded by

Further, an impurity diffusion layer (not shown), a gate insulating film (not shown), and the gate electrode 10 are provided on the p-type surface layer 31 formed on the p-type stopper layer 19a. A transfer transistor 207 is provided. The side surface and the bottom surface of the element isolation region 18 are covered with a thin p ⁺ type sidewall layer 30. A gate wiring 20 made of the same polysilicon as the gate electrode 10 is provided on the element isolation region 18. A silicon oxide film 21 is provided on the side surfaces of the gate electrode 10 and the gate wiring 20, and a silicon oxide film 22 is provided on the photoelectric conversion element 206 and the silicon oxide film 21. A first interlayer insulating film 23 and a second interlayer insulating film 24 are respectively provided on the silicon oxide film 22 and the gate wiring 20.

  Further, in the solid-state imaging device, a contact 25 that is connected to the gate electrode 10 and penetrates the first interlayer insulating film 23, and aluminum (Al) that is connected to the contact 25 and is disposed on the first interlayer insulating film 23. ) And the like, a contact 27 connected to the wiring 26 and penetrating the second interlayer insulating film 24, a wiring 28 connected to the contact 27 and on the second interlayer insulating film 24, and at least the wiring 28 A protective film 29 is provided from above to the second interlayer insulating film 24.

  The effect of the solid-state imaging device of the present embodiment having the above configuration will be described.

  When light enters the photoelectric conversion element 206, holes and electrons are generated, and charges (electrons) corresponding to the amount of incident light are stored in a pn junction capacitor formed by a depletion layer that spreads from the pn interface. Here, the depletion layer is generated by joining the p-type stopper layers 19 and 19a, the first semiconductor layer 13 and the sidewall layer 30, and the n-type second semiconductor layer 14, respectively.

  The Ge composition ratio of the fourth semiconductor layer 16 can be set arbitrarily, but light having a wavelength up to about 1800 nm can be absorbed by increasing the Ge composition ratio.

  As already described with reference to FIG. 3, SiGe or Ge can absorb long-wavelength light having a wavelength of 1100 nm or more that cannot be absorbed by Si. In addition, even for light having a wavelength that can be absorbed by Si, since the absorption coefficient of SiGe or Ge is larger than that of silicon, the photoelectric conversion element of this embodiment has very high sensitivity. In particular, the sensitivity to light in the long wavelength region is greatly improved as compared with the case of using Si. Single-crystal SiGe and Ge can be formed more easily than Si by using a CVD (Chemical Vapor Deposition) method. Further, SiGe or Ge formed on a semiconductor layer made of Si can be selectively grown only in a desired region by using a mask.

  As described above with reference to FIG. 4, when the fourth semiconductor layer 16 made of SiGe or Ge is epitaxially grown on the second semiconductor layer 14 made of Si, the lattice constant differs between Si and Ge. When the critical film thickness is exceeded, cracks due to crystal defects occur. Therefore, it is preferable that the fourth semiconductor layer 16 has a critical film thickness or less. Therefore, conventionally, it has been difficult to increase sensitivity by increasing the thickness of the fourth semiconductor layer 16.

  In the solid-state imaging device of the present embodiment, the fourth semiconductor layer 16 is formed in a three-dimensional manner on the recess provided in the second semiconductor layer 14. Since light from the outside is incident in a vertical direction or an oblique direction with respect to the substrate surface of the semiconductor substrate 12a, the fourth semiconductor layer 16 through which the light passes compared to the case where the fourth semiconductor layer 16 is made flat. The effective film thickness can be increased. For example, when light parallel to the slope of the concave portion is incident on a portion of the fourth semiconductor layer 16 formed on the concave portion formed on the second semiconductor layer 14, the concave portion is formed. The length of the inclined surface is the effective film thickness of the portion of the fourth semiconductor layer 16.

  For this reason, even in the case where the thickness of the fourth semiconductor layer 16 having a large light absorption coefficient is limited, the fourth semiconductor layer 16 in the fourth semiconductor layer 16 is compared with the case where the fourth semiconductor layer 16 is formed flat. The amount of light absorption can be greatly increased. Therefore, the sensitivity of the photoelectric conversion element 206 is greatly improved as compared with the conventional solid-state imaging device. In particular, the sensitivity to visible light in the long wavelength region and light in the infrared region can be significantly improved.

  Note that the recess formed in the upper portion of the second semiconductor layer 14 may be a hole or a groove, and the planar shape may be a lattice shape or a stripe shape. If formed, the fourth semiconductor layer 16 covering this can be formed into a three-dimensional shape. It is sufficient that at least one recess is formed.

  In the case of the configuration shown in FIG. 8, the width of the groove formed in the upper part of the second semiconductor layer 14 can be determined by the thickness of the fourth semiconductor layer 16. When the Ge composition ratio is 20%, if the thickness of the fourth semiconductor layer 16 is about 200 nm, which is equal to the critical film thickness, the width of the groove formed in the second semiconductor layer 14 is about 400 nm or more. The interval can be about 400 nm or more. Note that the groove spacing is preferably set to the minimum width that can be patterned, since increasing the number of grooves per unit area can increase sensitivity. In this way, the proportion of the portion where the effective thickness of the fourth semiconductor layer 16 is larger than the absorption length of incident light increases, and the sensitivity of the photoelectric conversion element 206 can be further improved. In addition, since the effective thickness of the fourth semiconductor layer 16 corresponding to the incident direction of light varies depending on the depth of the groove formed in the second semiconductor layer 14, the depth of the groove is required. It may be set according to the sensitivity.

  The grooves constituting the recesses are formed by dry etching using a fluorine-based gas or wet etching using a potassium hydroxide (KOH) solution, TMAH (Tetra Methyl Ammonium Hydroxide), or the like above the second semiconductor layer 14. To be formed. Since dry etching is anisotropic, when this is used, the second semiconductor layer 14 is etched substantially perpendicular to the substrate surface of the semiconductor substrate 12a, and wet etching is isotropic. When used, the second semiconductor layer 14 is etched obliquely.

  In the solid-state imaging device of the present embodiment, the depth of the groove formed in the second semiconductor layer 14 is about 150 nm as an example. Further, FIG. 8 shows a shape when the concave portion is formed by wet etching. According to such a configuration, it is possible to improve the sensitivity while suppressing the noise current. Note that when the fourth semiconductor layer 16 is made of SiGe, carbon atoms (not shown) may be added. When carbon atoms are added to the fourth semiconductor layer 16, the number of charges generated in the dark can be reduced. This is because a carbon atom is substituted for a Ge atom that is larger than a Si atom, thereby reducing the stress generated in the fourth semiconductor layer 16 and reducing a defect region that induces an increase in the number of charges in the dark. is there.

  In the example described above, the wirings 26 and 28 are made of a metal such as aluminum, but may be made of copper or a metal mainly composed of copper. In this case, the wirings 26 and 28 are embedded in the upper part of the first interlayer insulating film 23 and the upper part of the second interlayer insulating film 24, respectively. Further, the contacts 25 and 27 may be made of a metal such as tungsten, but when using a copper wiring, the contacts 25 and 27 may be made of copper formed integrally with the wiring.

  Further, in the solid-state imaging device of the present embodiment, the photoelectric conversion element can function even when the conductivity types of the semiconductor layers constituting the pixels are all reversed.

  If the solid-state imaging device of the present embodiment having the above configuration is used, the following effects can be specifically realized. That is, in the solid-state imaging device according to the second embodiment shown in FIG. 8, the dark noise current caused by the crack generated by the difference in lattice constant can be suppressed by about two digits or more. When the fourth semiconductor layer 16 is made of SiGe having a thickness of the fourth semiconductor layer 16 of about 500 nm, an interval between the recesses of about 500 nm, and a Ge composition ratio of about 20%, for example, light having a wavelength of 800 nm or more. The sensitivity of the solid-state imaging device of the present embodiment has increased by about 1.5 times.

  This effect is a value in the solid-state imaging device according to an example of the present embodiment, and the Ge composition ratio in the fourth semiconductor layer 16 is increased, the thickness of the fourth semiconductor layer 16 is increased, or the first The sensitivity is further improved by increasing the depth of the groove formed in the second semiconductor layer 14.

-Manufacturing method of solid-state imaging device-
Next, a method for manufacturing the solid-state imaging device according to the second embodiment shown in FIG. 8 will be described with reference to the drawings. Here, as an example, a method of forming a groove by wet etching is shown.

  9A to 9D are cross-sectional views illustrating the manufacturing process of the solid-state imaging device according to the second embodiment. In the manufacturing method according to the present embodiment, the steps shown in FIGS. 5A to 6A are the same as those in the manufacturing method according to the first embodiment, and thus the description thereof is omitted. The process after the process of processing the upper part will be described.

  First, as shown in FIG. 9A, a gate electrode 10 and a gate wiring 20 for transferring charges generated by photoelectric conversion to the FD portion 11 are formed. Next, using a lithography method and an etching method, a silicon oxide film 21 having a thickness of about 100 nm having an opening in a region where the photoelectric conversion element is to be formed is formed on a substrate (a solid-state imaging device being manufactured).

  Next, as shown in FIG. 9B, the upper portion of the second semiconductor layer 14 in the opening of the silicon oxide film 21 is used with, for example, TMAH, KOH solution or the like as an etchant and the silicon oxide film 21 as a mask. Processed by wet etching. As a result, a recess is formed in the upper part of the second semiconductor layer 14.

  Here, the shape of the concave portion may be a hole shape or a groove shape, and the planar shape may be a lattice shape or a stripe shape. Alternatively, the upper part of the second semiconductor layer 14 may be columnar. The shape of the recess can be changed by the shape of the opening of the silicon oxide film 21 and the etching method. When wet etching is performed, the etching rate varies depending on the crystal plane of the semiconductor substrate 12a. For example, when a silicon substrate having a (100) plane as a main surface is used, etching is performed so that the (111) plane appears. It is also possible to process the second semiconductor layer 14 by dry etching. In this case, the etching proceeds in a direction perpendicular to the substrate surface of the semiconductor substrate 12a. Therefore, the cross section of the groove may be not only V-shaped but also U-shaped.

  Next, as shown in FIG. 9B, a portion of the silicon oxide film 21 provided on the second semiconductor layer 14 is selectively removed by using a lithography method and an etching method. Next, n-type SiGe or Ge is selectively epitaxially grown by, for example, a CVD method so as to cover the upper surface of the second semiconductor layer 14, thereby forming the fourth semiconductor layer 16. As a result, a photoelectric conversion element 206 having a part of the first semiconductor layer 13, the second semiconductor layer 14, and the fourth semiconductor layer 16 is formed.

  Subsequently, as illustrated in FIG. 9C, the entire upper surface of the substrate including the fourth semiconductor layer 16 (the solid-state imaging device under manufacture) is covered with the silicon oxide film 22 and is included in the fourth semiconductor layer 16. This prevents Ge from diffusing into the transistor portion and peripheral circuits.

  Next, as shown in FIG. 9D, the silicon oxide film 22 is planarized, and then the upper surfaces of the gate electrode 10 and the gate wiring 20 are exposed by a lithography method and an etching method. A silicide layer is formed on the gate wiring 20. Thereafter, the first interlayer insulating film 23 is formed by the CVD method or the like for forming the first interlayer insulating film 23 by the CVD method or the like. Thereafter, the upper surface of the first interlayer insulating film 23 is planarized by CMP. Then, the resist is patterned using a lithography method, and a contact hole is formed by a dry etching method using the resist. Next, after a contact 25 is formed by embedding a metal such as tungsten in the contact hole by a known method, the upper surface of the contact 25 is flattened by a CMP method. Then, after forming a metal film made of aluminum or the like on the first interlayer insulating film 23, the metal film is patterned using a lithography method and a dry etching method, thereby forming the wiring 26.

(Third embodiment)
FIG. 10 is a cross-sectional view showing part of a pixel of a solid-state imaging device according to the third embodiment of the present invention. Although the basic structure is the same as that of the solid-state imaging device according to the first embodiment, the solid-state imaging device of this embodiment further includes a p ⁺ -type fifth semiconductor layer 50 that covers the fourth semiconductor layer 16. ing. The impurity concentration of the fifth semiconductor layer 50 is about 1 × 10 ¹⁵ to 1 × 10 ²⁰ (pieces / cm ³ ), and the thickness of the fifth semiconductor layer 50 is about 5 nm to 100 nm.

  In the solid-state imaging device of the present embodiment, the fifth semiconductor layer 50 covers the fourth semiconductor layer 16, so that the depletion layer is prevented from spreading to the fifth semiconductor layer 50, so The influence of charges generated in the vicinity of the upper surface of the conversion element 206 can be reduced. Other effects are the same as those of the solid-state imaging device of the first embodiment.

  10 shows an example in which the fifth semiconductor layer 50 that covers the fourth semiconductor layer 16 of the solid-state imaging device according to the first embodiment is provided, the solid state according to the second embodiment shown in FIG. In the imaging device, even if the fifth semiconductor layer 50 covering the fourth semiconductor layer 16 is provided, the above-described effects can be obtained.

In the solid-state imaging device of the present embodiment, after the fourth semiconductor layer 16 is formed in the step shown in FIG. 7A, the fourth semiconductor layer 16 is made of p ⁺ type Si, SiGe, or Ge so as to cover the fourth semiconductor layer. 5 semiconductor layers 50 are epitaxially grown. When the fifth semiconductor layer 50 is composed of SiGe, the flow rate of B ₂ H ₆ gas is supplied while Si ₂ H ₆ gas and GeH ₄ are supplied into the growth apparatus, and the source gas of B (boron) is supplied. The fifth semiconductor layer 50 may be grown under the condition that exists in a high concentration.

  The solid-state imaging device and the manufacturing method thereof according to the present invention are useful for imaging devices such as various digital cameras, mobile phones, video cameras, surveillance cameras, and the like that perform image capturing and the manufacturing thereof.

10 Gate electrode 11 FD section
12 substrate 12a semiconductor substrate 13 first semiconductor layer 14 second semiconductor layer 15 third semiconductor layer 16 fourth semiconductor layers 17, 19, 19a stopper layer 18 element isolation region 20 gate wiring 21 silicon oxide film 22 silicon oxide Film 23 First interlayer insulating film 24 Second interlayer insulating film 25, 27 Contacts 26, 28 Wiring 29 Protective film 30 Side wall layer 31 Surface layer 50 Fifth semiconductor layer 201 Pixel 202 Imaging region 203 Vertical shift register 204 Output signal Line 205 Horizontal shift register 206 Photoelectric conversion element 207 Transfer transistor 208 Amplification transistor 209 Power supply voltage supply unit 210 Reset transistor 211 Selection transistor 212, 213, 214 Output pulse line 301 Pad insulation film 302 Oxidation resistance film

Claims (10)

A solid-state imaging device including a plurality of pixels including photoelectric conversion elements formed on a semiconductor substrate made of a first material,
The photoelectric conversion element is made of the first material, and is laminated in a three-dimensional manner on a first semiconductor portion having a concave portion or a convex portion, and on the concave portion or the convex portion of the first semiconductor portion, A solid-state imaging device including a second semiconductor portion made of a second material having a band gap energy smaller than that of the first material and having the same conductivity type as the first semiconductor portion. The solid-state imaging device according to claim 1,
The first semiconductor portion has the convex portion,
The second semiconductor portion is stacked on the convex portion of the first semiconductor portion;
The photoelectric conversion element is
A portion of a first semiconductor layer of a second conductivity type provided on the semiconductor substrate;
A second semiconductor layer of a second conductivity type provided on a part of the first semiconductor layer;
A third semiconductor layer of a second conductivity type made of the first material selectively provided on the second semiconductor layer;
A second conductivity type fourth semiconductor layer made of the second material provided on the second semiconductor layer and the third semiconductor layer, and
The first semiconductor portion is composed of the second semiconductor layer and the third semiconductor layer which is the convex portion,
The solid-state imaging device, wherein the second semiconductor portion is constituted by the fourth semiconductor layer. The solid-state imaging device according to claim 2,
The solid-state imaging device, wherein the third semiconductor layer has a columnar structure, a stripe structure, or a wall-like structure that has a lattice shape in plan view. The solid-state imaging device according to claim 1,
The first semiconductor portion has the recess;
The second semiconductor portion is stacked on the recess of the first semiconductor portion;
The photoelectric conversion element is
A portion of a first semiconductor layer of a first conductivity type provided on the semiconductor substrate;
A second semiconductor layer which is provided on a part of the first semiconductor layer, the recess is formed in an upper portion thereof, and constitutes the first semiconductor portion;
A solid-state imaging device comprising: a fourth semiconductor layer provided on the second semiconductor layer and constituting the second semiconductor portion. The solid-state imaging device according to claim 4,
The solid-state imaging device, wherein the concave portion is formed by selectively etching an upper portion of the second semiconductor layer. The solid-state imaging device according to claim 4 or 5,
The solid-state imaging device, wherein the concave portion has a hole shape or a groove shape, and a planar shape is a lattice shape or a stripe shape. In the solid-state imaging device according to any one of claims 2 to 6,
The photoelectric conversion element further includes a fifth semiconductor layer of a first conductivity type that covers the fourth semiconductor layer. In the solid-state imaging device according to any one of claims 1 to 7,
The first material is silicon;
The solid-state imaging device, wherein the second material is Si _x Ge _(1-x) (0 ≦ x <1). A manufacturing method of a solid-state imaging device including a plurality of pixels including photoelectric conversion elements formed on a semiconductor substrate made of a first material,
Forming a first semiconductor layer of a first conductivity type on the semiconductor substrate;
Forming a second conductivity type second semiconductor layer in a region of the semiconductor substrate located on the first semiconductor layer;
Forming an insulating film having one or more openings on the second semiconductor layer (c);
Forming a second conductive type third semiconductor layer by selectively epitaxially growing the first material on a region of the second semiconductor layer located in the opening using the insulating film as a mask; (D) and
After removing the insulating film, a second material having a bandgap energy smaller than that of the first material is epitaxially grown on the second semiconductor layer and the third semiconductor layer, and second conductivity type second And a step (e) of forming the four semiconductor layers in a three-dimensional shape. A manufacturing method of a solid-state imaging device including a plurality of pixels including photoelectric conversion elements formed on a semiconductor substrate made of a first material,
Forming a first semiconductor layer of a first conductivity type on the semiconductor substrate;
Forming a second conductivity type second semiconductor layer in a region of the semiconductor substrate located on the first semiconductor layer;
Forming an insulating film having one or more openings on the second semiconductor layer (c);
Using the insulating film as a mask, selectively etching a portion of the upper portion of the second semiconductor layer located in the opening to form a groove-shaped recess in the upper portion of the second semiconductor layer (D) and
After removing the insulating film, a second material having a band gap energy smaller than that of the first material is epitaxially grown on the upper surface of the second semiconductor layer including the concave portion, and a second conductivity type fourth material is obtained. And (e) forming a semiconductor layer in a three-dimensional form.

Images