JP2006019756A - Solid-state image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that, in a CCD-type solid-state image sensor comprising a charge transfer device having a so-called overlay transfer electrode structure and a micro lens, the focal position of the micro lens gets away from a photoelectric conversion device accompanied by the high integration of the photoelectric conversion device and sensitivity is deteriorated. <P>SOLUTION: An interlayer insulating film formed of a silicon oxide system material and having a flat top surface is formed such that the interlayer insulating film covers a light shield film having an opening above aphotoelectric conversion device. A passivation film is formed on the interlayer insulating film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device.

  Active elements such as MOS (metal-oxide-semiconductor) type field effect transistors and charge coupled devices (CCD), and passive elements such as photoelectric conversion elements and capacitive elements are formed on one surface of a semiconductor substrate. A semiconductor device having a desired function can be obtained by electrically connecting each other by wiring or by connecting a signal line to these elements and supplying a predetermined signal from the outside.

  For example, a large number of photoelectric conversion elements on one surface of a semiconductor substrate, one or two kinds of charge transfer elements that read and transfer charges accumulated in these photoelectric conversion elements, and output from the charge transfer elements A solid-state imaging device can be obtained by forming a charge detection circuit that detects and amplifies the charge. Conventionally, solid-state imaging devices have been widely used as linear image sensors or area image sensors.

  In the CCD type solid-state imaging device, the charge transfer device is constituted by a CCD. A CCD can be obtained by forming a channel on one surface of a semiconductor substrate and arranging a plurality of electrodes (hereinafter referred to as “transfer electrodes”) in parallel on the channel via an electrical insulating film. In order to increase the charge transfer efficiency of the CCD, it is desirable to arrange adjacent transfer electrodes as close as possible.

  For this reason, a CCD used as a charge transfer element in a solid-state imaging device generally has a so-called overlapping transfer electrode structure. In this structure, the line widths of the other transfer electrodes adjacent to this transfer electrode are arranged between the adjacent edges of the transfer electrodes selected in the line width direction in the plan view of the adjacent photoelectric conversion elements. Overlapping edge of direction.

  In recent years, especially in solid-state image sensors used as area image sensors, the integration of photoelectric conversion elements has been advanced in order to achieve high resolution, and the size of each photoelectric conversion element has been reduced accordingly. Yes.

JP 2001-308299 A

  In a solid-state imaging device used as an area image sensor, in particular, a single-plate solid-state imaging device, in general, one microlens is arranged above each photoelectric conversion element via a passivation film and an organic flattening film, This microlens increases the light collection efficiency. Also in a solid-state imaging device used as a linear image sensor, one microlens is disposed above each photoelectric conversion element via an organic flattening film as necessary.

  In these microlenses, for example, a transparent resin (including a photoresist) layer is partitioned into a predetermined shape by a photolithography method or the like, then the transparent resin layer in each partition is melted by heat treatment, and corners are rounded by surface tension. Obtained after cooling. One section is molded into one microlens. The size of these microlenses is steadily decreasing as the photoelectric conversion elements are highly integrated.

  When a microlens having a small size is manufactured by the above-described method, the focal position tends to be higher (microlens side) than the desired position. In order to set the focal position of the microlens to a desired position, it is desirable to shorten the distance between the microlens and the corresponding photoelectric conversion element.

  However, if a charge transfer element for a solid-state image sensor is formed by a CCD having a so-called superimposed transfer electrode structure, it is difficult to shorten the distance.

  If the CCD has a single-layer electrode structure, that is, if the transfer electrode for CCD is formed by patterning one conductive film, the distance can be shortened.

  However, when a transfer electrode is formed by patterning one conductive film using photolithography technology, the distance between adjacent transfer electrodes becomes relatively long. In order to obtain a CCD having a single-layer electrode structure having a practically sufficient charge transfer efficiency, it is desired that the distance between adjacent transfer electrodes is, for example, about 0.2 μm or shorter.

  Of course, if advanced photolithography technology is used, the distance between adjacent transfer electrodes can be reduced to about 0.13 μm. It is possible to obtain a CCD having a single-layer electrode structure having a desired charge transfer efficiency. However, the manufacturing cost increases.

  An object of the present invention is to provide a solid-state imaging device in which the distance between the microlens and the photoelectric conversion element can be easily shortened and the manufacturing cost is relatively low even when the microlens is disposed above the photoelectric conversion element. It is to be.

  According to one aspect of the present invention, (I) a semiconductor substrate, (II) a plurality of photoelectric conversion elements arranged in a matrix over a plurality of rows and columns on one surface of the semiconductor substrate, and (III ) A first charge transfer element that is arranged corresponding to one photoelectric conversion element array, each of which can read and transfer charges from each of the corresponding photoelectric conversion elements And (IV) a second charge transfer element that can be electrically connected to each of the first charge transfer elements, and (V) all of the first charge transfer elements and the second charge transfer element. A light shielding film that is electrically separated from each other and covers each of the first charge transfer elements and the second charge transfer elements in a plan view, and has one opening above each of the photoelectric conversion elements; (VI) formed of a silicon oxide material and covering the light shielding film and the opening in a plan view , An interlayer insulating film having a flat upper surface, the solid-state imaging device that includes a passivation film disposed on the (VII) the interlayer insulating film is provided.

  According to another aspect of the present invention, (I) a semiconductor substrate, (II) a plurality of photoelectric conversion elements arranged in at least one row on one surface of the semiconductor substrate, and (III) one row of photoelectric conversion A charge transfer element disposed corresponding to each element row; and (IV) an interlayer insulating film formed of a silicon oxide material and covering all of the charge transfer elements in plan view and having a flat upper surface. And (V) a solid-state imaging device provided with a passivation film disposed on the interlayer insulating film.

  When the interlayer insulating film is used as a foundation layer of the passivation film, the interlayer insulating film is formed of a silicon oxide-based material and the upper surface thereof is flattened, so that the thickness of the passivation film can be made substantially uniform, There is no need to form an organic planarizing film on the passivation film.

  As a result, even when a microlens is disposed above the photoelectric conversion element, for example, the distance between the microlens and the photoelectric conversion element can be easily shortened, and even when the photoelectric conversion element is highly integrated, It becomes easy to set the focal position of the microlens to a desired position. For example, even if the passivation film is formed of a material having a high refractive index, the refraction of light in the passivation film becomes almost uniform, so that it becomes easy to make more light incident on the photoelectric conversion element. .

  As used herein, “silicon oxide-based material” refers to silicon oxide (including spin-on glass), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and borosilicate glass (BSG). It is a general term.

  FIG. 1 shows a photoelectric conversion element 10, a first charge transfer element (hereinafter referred to as “vertical charge transfer element”) 20, a read gate 30, and a second charge transfer in the solid-state imaging device 100 according to the first reference example. A planar arrangement of an element (hereinafter referred to as “horizontal charge transfer element”) 40 and a charge detection circuit 50 is schematically shown. Although not shown in the figure, one microlens is arranged above each photoelectric conversion element 10 via a predetermined layer.

  The illustrated solid-state image sensor 100 is a solid-state image sensor used as an area image sensor. In the solid-state image sensor 100, a large number of photoelectric conversion elements 10 are arranged in a plurality of rows and columns on one surface of a semiconductor substrate 1. The pixels are shifted. The total number of photoelectric conversion elements 10 in an actual solid-state imaging element used as an area image sensor is, for example, several hundred thousand to several million.

  Here, “pixel shifting arrangement” in this specification means that each photoelectric conversion element in the even numbered photoelectric conversion element array is photoelectrically converted with respect to each photoelectric conversion element in the odd numbered photoelectric conversion element array. About 1/2 of the pitch of the photoelectric conversion elements in the element column, shifted in the column direction, and for each photoelectric conversion element in the odd-numbered photoelectric conversion element row, the photoelectric conversion element in the even-numbered photoelectric conversion element row Each of the photoelectric conversion element rows is shifted by about ½ of the pitch of the photoelectric conversion elements in the photoelectric conversion element row, and each of the photoelectric conversion element columns includes only odd-numbered or even-numbered photoelectric conversion elements. It means the arrangement of photoelectric conversion elements. “Pixel shifting arrangement” is a form in which a large number of photoelectric conversion elements are arranged in a matrix over a plurality of rows and columns.

  The above-mentioned “about 1/2 of the pitch of the photoelectric conversion elements in the photoelectric conversion element array” includes 1/2, as well as factors such as manufacturing errors, pixel position rounding errors that occur in design or mask manufacturing, and the like. Although it is deviated from 1/2, a value that can be regarded as substantially equivalent to 1/2 in view of the performance of the obtained solid-state imaging device and the image quality of the image is also included. The same applies to the above-mentioned “about 1/2 of the pitch of the photoelectric conversion elements in the photoelectric conversion element row”.

  Each photoelectric conversion element 10 is configured by, for example, an embedded pn photodiode and has, for example, an octagonal shape in plan view. When light enters the photoelectric conversion element 10, charges are accumulated in the photoelectric conversion element 10.

  In order to transfer the charges accumulated in the individual photoelectric conversion elements 10 to the charge detection circuit 50, the vertical charge transfer elements 20 are arranged along one photoelectric conversion element array, one for each photoelectric conversion element array. .

  Each vertical charge transfer element 20 is constituted by a CCD, and is driven by, for example, eight-phase drive signals φV1 to φV8 to perform charge transfer. In FIG. 1, four drive signals φV1, φV3, φV5, and φV7 out of the eight-phase drive signals V1 to φV8 are further divided into two types A and B, respectively, depending on the timing at which the readout pulse is superimposed. An example of wiring when supplying is shown.

  In order to control reading of charges from the photoelectric conversion element 10 to the vertical charge transfer element 20, one read gate 30 is arranged adjacent to each photoelectric conversion element 10. Each read gate 30 includes a read gate channel region (not shown) formed in the semiconductor substrate 1 and a region of the first transfer electrode 25a covering the channel region in plan view. In FIG. 1, each read gate 30 is hatched so that the position of the read gate 30 can be easily understood.

  When a read pulse (potential is about 15 V, for example) is supplied to the first transfer electrode 25a, charges are read from each of the photoelectric conversion elements 10 corresponding to the first transfer electrode 25a to each vertical charge transfer element 20. Reading of charges from the photoelectric conversion element 10 to the vertical charge transfer element 20 is performed in units of photoelectric conversion element rows.

  The charges read to each vertical charge transfer element 20 in units of photoelectric conversion element rows are transferred to the horizontal charge transfer element 40 by the vertical charge transfer elements 20 under the same phase.

  The horizontal charge transfer element 40 is also constituted by a CCD, and is driven by, for example, two-phase drive signals φH1 to φH2 to sequentially transfer charges received from the vertical charge transfer elements 20 to the charge detection circuit 50.

  The charge detection circuit 50 detects a charge transferred from the horizontal charge transfer element 40 to generate a signal voltage, and amplifies the signal voltage to generate a pixel signal. This pixel signal becomes the output of the solid-state image sensor 100.

  Hereinafter, the configuration of the vertical charge transfer element 20 which is one of the characteristic parts of the solid-state imaging element 100 will be described in detail.

As shown in FIG. 1, each vertical charge transfer element 20 includes a single first charge transfer channel 23 (hereinafter, also referred to as “vertical charge transfer channel 23”) formed in the semiconductor substrate 1, and a semiconductor. and a five first transfer electrode 25a~25e the first electrical insulating film on the substrate 1 (not shown.) are formed through co-exist on the photoelectric conversion element column D _V.

Each of the vertical charge transfer channels 23 is configured by, for example, an n-type channel. Individual vertical charge transfer channel 23, while meandering along a corresponding photoelectric conversion element column, extending in the photoelectric conversion element column D _V as a whole one channel.

  One first transfer electrode 25a is arranged on the downstream side of each photoelectric conversion element row, one first transfer electrode 25b is arranged on the upstream side, and three are arranged on the downstream side of the most downstream first transfer electrode 25a. First transfer electrodes 25c to 25e are arranged in parallel in this order. Each of these first transfer electrodes 25a to 25e crosses each of the vertical charge transfer channels 23 in plan view. The individual first transfer electrodes 25 a to 25 e constitute a part of all the vertical charge transfer elements 20.

  In this specification, the movement of charges transferred from the photoelectric conversion element 10 to the charge detection circuit 50 is regarded as one flow, and the relative positions of individual members and the like are set to “any upstream” as necessary. "," What downstream "and the like.

  FIG. 2 schematically shows the configuration and arrangement of the first transfer electrodes 25a and 25b in a cross section taken along the line II-II shown in FIG.

  As shown in the figure, the first transfer electrodes 25 a and 25 b are disposed on one surface of the semiconductor substrate 1 via the first electrical insulating layer 5.

  Each of the first transfer electrodes 25a includes a first main electrode layer 25aM having a strip shape, and a first sub electrode layer 25aS formed on a side surface of the first main electrode layer 25aM and having a cross-sectional shape with rounded shoulders. The same applies to the first transfer electrode 25b. The first main electrode layer in the first transfer electrode 25b is denoted by reference numeral 25bM, and the first sub-electrode layer is denoted by reference numeral 25bS.

  The first main electrode layers 25aM and 25bM are formed of, for example, polysilicon (including polysilicon to which a donor or acceptor is added; the same applies hereinafter), a metal such as aluminum, tungsten, or titanium, or a metal silicide such as tungsten silicide. Is done.

  The same applies to the first sub electrode layers 25aS and 25bS. When the first main electrode layers 25aM and 25bM are formed of polysilicon, the first sub electrode layers 25aS and 25bS made of metal silicide can be formed by a method described later, for example. When the first main electrode layers 25aM and 25bM and the first sub electrode layers 25aS and 25bS are formed of polysilicon, a metal silicide layer can be formed on these electrode layers. Examples of the metal silicide include cobalt silicide, chromium silicide, nickel silicide, tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide, and the like.

  The first transfer electrodes 25a and 25b are both separated from the adjacent first transfer electrodes 25a and 25b by, for example, about 0.1 μm. The upper surfaces of the first transfer electrodes 25a and 25b are substantially located on the same plane. Each first transfer electrode 25a, 25b is covered with an electrically insulating film (for example, a thermal oxide film) IF.

  For example, the first electrical insulating layer 5 includes a silicon oxide film having a thickness of about 10 to 70 nm, a silicon nitride film having a thickness of about 20 to 80 nm, and a silicon oxide film having a thickness of about 5 to 50 nm. When the first sub-electrode layers 25aS and 25bS are formed, the upper silicon oxide film in the ONO film is formed when the first sub-electrode layers 25aS and 25bS are formed when the first sub-electrode layers 25aS and 25bS are formed. And the middle silicon nitride film may be locally removed. FIG. 2 shows an example of this.

  For example, in a region where a charge transfer channel is formed between adjacent first transfer electrodes, the potential of the charge transfer channel may change during the process of manufacturing the first transfer electrode. There may be a difference between the potential below the adjacent first transfer electrodes and the potential below the first transfer electrodes. In order to alleviate or eliminate this difference, it is desirable to add an impurity having a predetermined conductivity type below between adjacent first transfer electrodes. When the first electrical insulating film 5 is thinned between the adjacent first transfer electrodes, it becomes easier to inject impurities below this portion.

  Although not shown in FIG. 2, each of the first transfer electrodes 25 c to 25 d also has a strip-shaped first main electrode layer and the first main electrode layer, like the first transfer electrodes 25 a and 25 b described above. And a first sub-electrode layer having a cross-sectional shape with rounded shoulders. The first transfer electrodes 25c to 25e are also covered with an electrical insulating film (for example, a thermal oxide film).

  The first transfer electrodes 25c to 25e are also separated from other adjacent first transfer electrodes by about 0.1 μm, for example. The upper surfaces of the first transfer electrodes 25c to 25e are substantially located on the same plane as the upper surfaces of the first transfer electrodes 25a and 25b.

  The first transfer electrodes 25a to 25e having the above-described configuration can be manufactured as follows, for example. The following description will be made with reference to the reference numerals used in FIG. 1 or FIG.

  3A to 3E conceptually show the manufacturing process of the first transfer electrodes 25a to 25e, respectively.

  First, an impurity-added region such as a vertical charge transfer channel 23 and a channel stop and a horizontal charge transfer channel, which will be described later, is formed at a predetermined position on one surface of the semiconductor substrate 1, and the first electrically insulating layer 5 and the element are formed thereon. An isolation insulating film (not shown) is formed. The first electrical insulating layer 5 is disposed in a region where the photoelectric conversion element 10, the vertical charge transfer element 20, and the horizontal charge transfer element 40 are to be formed, and an element isolation insulating film is disposed around the first electrically insulating layer 5.

  As shown in FIG. 3A, a first conductive layer 110 used as a material for the main electrode layer is deposited on the first electrically insulating layer 5, and a second conductive layer to be described later is etched thereon. (Hereinafter abbreviated as “RIE”), a layer (hereinafter referred to as “stopper layer”) 115 functioning as an etching stopper is deposited. When the first conductive layer 110 is formed of polysilicon, the film thickness can be, for example, about 0.4 μm. As the stopper layer 115, for example, a silicon nitride film having a thickness of about 0.05 μm can be used.

  As shown in FIG. 3B, a resist mask 120 having a slit-like opening OP at a predetermined position is formed over the stopper layer 115, and the stopper layer 115 and the first layer are formed using the resist mask 120 as an etching mask. The conductive layer 110 is etched. A main electrode layer EM for the first transfer electrode is obtained.

  The resist mask 120 can be produced, for example, by exposing a predetermined portion of the photoresist layer by photolithography and then performing development processing. The width of the opening OP can be set to, for example, about 0.3 μm. After forming the main electrode layer EM, the resist mask 120 is removed.

  As shown in FIG. 3C, a second conductive layer 125 used as a material for the sub-electrode layer is deposited on the stopper layer 115 and the exposed surface of the first electrical insulating layer 5. The thickness of the second conductive layer 125 on the main electrode layer EM is preferably less than ½ of the distance between two adjacent main electrode layers EM.

  When the interval between the adjacent main electrode layers EM is narrow, the film thickness of the second conductive layer 125 becomes relatively thick on the main electrode layer EM, and the first electrically insulating layer 5 between the adjacent main electrode layers EM. It tends to be relatively thin on top. FIG. 3C shows this example.

  When the first conductive layer 110 is formed of polysilicon, the natural oxide film formed on the surface of the main electrode layer EM is removed by, for example, vapor-phase hydrofluoric acid treatment prior to the deposition of the second conductive layer 125. To do.

  Alternatively, after the second conductive layer 125 is deposited or a sub-electrode layer ES described later is formed, a donor such as phosphorus is diffused from the second conductive layer 125 or the sub-electrode layer ES to the main electrode layer EM. . In this case, the second conductive layer 125 is also preferably formed of polysilicon.

  As shown in FIG. 3D, anisotropic etching such as RIE is performed using the stopper layer 115 as an etching stopper, and the second conductive layer 125 is left only on the side surface of each main electrode layer EM. The second conductive layer 125 remaining on the side surface of the main electrode layer EM becomes the sub electrode layer ES, and a first transfer electrode having the main electrode layer EM and the sub electrode layer ES is obtained. The sub-electrode layer ES has a cross-sectional shape with a rounded shoulder.

  At this time, since the second conductive layer 125 is patterned by RIE, the microloading effect is hardly exhibited. It is easy to pattern the second conductive film 125 into a desired shape.

In the case where the second conductive layer 125 is etched by RIE, an etching gas used in RIE is appropriately selected according to the material of the second conductive layer 125. For example, when the second conductive layer 125 is formed of polysilicon, RIE can be performed using chlorine gas. When the second conductive layer 125 is formed of tungsten, RIE can be performed using, for example, sulfur hexafluoride (SF ₆ ) gas or tetrafluoromethane (CF ₄ ) gas.

  When the first electrically insulating layer 5 is composed of the ONO film, as shown in FIG. 2, the upper silicon oxide film and the middle silicon nitride film in the ONO film are connected to the second conductive layer 125. It may be removed locally during the etching. If the second conductive layer 125 is relatively thick on the main electrode layer EM and relatively thin on the first electrical insulating layer 5 between the adjacent main electrode layers EM, the second conductive layer 125 is formed. When the layer 125 is etched, the upper silicon oxide film and the middle silicon nitride film of the ONO film can be easily removed between the adjacent main electrode layers EM.

  For example, when the charge transfer channel is formed by the n-type impurity doped region, the potential of the charge transfer channel is deepened below the adjacent first transfer electrodes due to the etching of the second conductive layer 125, and the charge accumulation is caused here. May be formed. In such a case, a p-type impurity such as boron is injected into the charge transfer channel via the first electrical insulating layer 5 interposed between the adjacent first transfer electrodes in plan view, and the first transfer electrode It is preferable that the potential of the charge transfer channel below the first transfer electrode and the potential of the charge transfer channel below the adjacent first transfer electrodes are substantially the same.

  When the photoelectric conversion element 10 is formed after the transfer electrode is formed, generally, prior to the formation of the photoelectric conversion element 10, the surface of the semiconductor substrate 1 is exposed in a region where the photoelectric conversion element 10 is to be formed. A new silicon oxide film (for example, a thermal oxide film) is formed. If the first electrically insulating layer 5 interposed between the adjacent first transfer electrodes in plan view is thinned during the etching of the second conductive layer 125, the photoelectric conversion element 10 can be produced even after that. It becomes easy to form the silicon oxide film on the region where the conversion element 10 is to be formed.

  As shown in FIG. 3E, the stopper layer 115 is removed. For example, when a silicon nitride film is used as the stopper layer 115, the stopper layer 115 (silicon nitride film) can be removed by hot phosphoric acid.

  When the first transfer electrodes 25a to 25e are manufactured by the illustrated method, the sub-electrode layer ES having a film thickness substantially equivalent to the film thickness of the second conductive film 125 (film thickness on the side surface of the main electrode layer EM) is formed. Since it is formed on the side surface of the main electrode layer EM, even if each main electrode layer EM is formed at intervals of about 0.3 μm as described above using photolithography technology, it is finally obtained. The interval between the first transfer electrodes 25a to 25e can be easily reduced to less than 0.3 μm. The film thickness of the second conductive layer 125 is easy to control with higher accuracy than the patterning accuracy using photolithography technology. It is easy to arrange the plurality of first transfer electrodes 25a to 25e under a desired interval.

  If the interval between the adjacent first transfer electrodes is set to approximately 0.2 μm or less, it is possible to obtain the vertical charge transfer element 20 having a practically sufficient charge transfer efficiency. If the interval between the adjacent first transfer electrodes is set to approximately 0.1 μm or less, for example, the vertical drive signals φV1 to φV8 each have a high level of 0 (zero) V and a low level of −8 V. Even in the case of driving the battery, practically sufficient charge transfer efficiency can be easily obtained.

By configuring the first transfer electrodes 25a to 25e as described above, even when one microlens is arranged above each photoelectric conversion element 10, the first transfer electrode has a so-called overlapping transfer electrode structure. 4 and 5, in which the distance between the microlens and the photoelectric conversion element 10 can be easily shortened compared to the case, the cross-sectional structure of the solid-state imaging element 100 including the microlens not shown in FIG. Shown schematically. 4 shows a cross section taken along line IV-IV shown in FIG. 1, and FIG. 5 shows a cross section taken along line II-II shown in FIG. Among the constituent elements shown in these figures, the constituent elements already shown in FIG. 1 or FIG. 2 are given the same reference numerals as those used in FIG. 1 or FIG.

As shown in these drawings, the semiconductor substrate 1 has, for example, an n-type silicon substrate 1a and a p ⁻ -type impurity added region 1b formed on one surface thereof. In the following description, in order to distinguish the magnitude of the impurity concentration between impurity doped regions having the same conductivity type, the p ⁻ type, p type, p ⁺ type, Alternatively, they are expressed as n ⁻ type, n type, and n ⁺ type.

The photoelectric conversion element 10 is formed, for example, by providing an n-type impurity addition region 10a at a predetermined position of the p ⁻ -type impurity addition region 1b and providing a p ⁺ -type impurity addition region 10b on the n-type impurity addition region 10a. It is composed of embedded photodiodes. The n-type impurity added region 10a functions as a charge storage region.

  One p-type impurity addition region 30a is arranged along the right edge of FIG. 4 in each photoelectric conversion element 10 (n-type impurity addition region 10a). The p-type impurity doped region 30a is used as a channel region for the read gate 30 (hereinafter referred to as “channel region 30a”).

  If necessary, a p-type impurity doped region 23 a is also disposed below each vertical charge transfer channel 23.

Except for the location where the channel region 30a is formed, the channel stop region CS has a periphery in the plan view of each photoelectric conversion element 10, a periphery in the plan view of each vertical charge transfer channel 23, and a horizontal charge transfer channel 43 (described later). It is formed around the plan view of FIG. This channel stop region CS is constituted by, for example, a p ⁺ -type impurity doped region.

Each impurity added region can be formed by, for example, ion implantation of a desired impurity and subsequent annealing. The p ⁻ -type impurity doped region 1b can also be formed by an epitaxial growth method. Each photoelectric conversion element 10 can be formed before the vertical charge transfer element 20 is manufactured, or can be formed after the vertical charge transfer element 20 is manufactured.

  Above each vertical charge transfer element 20, horizontal charge transfer element 40 (see FIG. 1), and each photoelectric conversion element 10, a second electrical insulating film 60, a light shielding film 65, an interlayer insulating film 70, and a passivation film. 75, the first planarizing film 80, the color filter array 85, and the second planarizing film 90 are sequentially formed in this order. On the second planarization film 90, the above-described microlens 95 is disposed.

  The second electrically insulating layer 60 is made of, for example, silicon oxide, and sufficiently separates the light shielding film 65 from the first transfer electrodes 25a to 25e therebelow.

  The light shielding film 65 is formed of a metal material such as tungsten, aluminum, chromium, titanium, or molybdenum, or an alloy material composed of two or more of these metals, and covers each vertical charge transfer element 20 and the horizontal charge transfer element 40. This prevents unnecessary photoelectric conversion from being performed in a region other than the photoelectric conversion element 10. The light shielding film 65 has one opening 65 a above each photoelectric conversion element 10. A region located on the surface of each photoelectric conversion element 10 in the opening 65 a in a plan view is a light incident surface in the photoelectric conversion element 10.

  When the wiring for supplying the driving signal for the vertical charge transfer element 20 and the wiring for supplying the driving signal for the horizontal charge transfer element 40 are formed of a material different from the material of the light shielding film 65, FIG. As shown in FIG. 5, an interlayer insulating film 70 is formed. The interlayer insulating film 70 is formed of, for example, a silicon oxide film, and short-circuits between the first transfer electrodes 25a to 25e and the wiring, and short-circuits between the transfer electrode constituting the horizontal charge transfer element 40 and the wiring. To prevent. When the wiring is formed of the same material as that of the light shielding film 65, the second electrical insulation film 60 is thickened instead of omitting the interlayer insulation film 70, and the second electrical insulation is performed. It is also possible to use the layer as an interlayer insulating film.

  The passivation film 75 is made of, for example, a silicon nitride film and protects the underlying member.

  The first planarization film 80 is formed of an organic material such as a photoresist and provides a flat surface for forming the color filter array 85.

  The color filter array 85 is disposed on a solid-state image sensor for color photography. In a solid-state imaging device for monochrome photography, the color filter array can be omitted. In a single-plate solid-state imaging device for color photography, a primary color type or complementary color type color filter array is used. In FIG. 4, two green filters 85G are shown, and in FIG. 5, one blue filter 85B and one red filter 85R are shown.

  The second planarization film 90 is formed of an organic material such as a photoresist, and provides a flat surface for forming the microlens 95.

  One macro lens 95 is arranged corresponding to one photoelectric conversion element 10 one by one. For example, as described above, these microlenses 95 are formed by partitioning a transparent resin (including a photoresist) layer into a predetermined shape by a photolithography method or the like, and then melting the transparent resin layer in each partition by heat treatment to obtain a surface tension. Is obtained by cooling after rounding the corners. One section is formed into one microlens 95.

  As can be easily understood from FIGS. 4 and 5, a relatively large number of layers are interposed between the upper surface of the photoelectric conversion element 10 and the lower surface of the microlens 95 corresponding to the photoelectric conversion element 10. The number of layers interposed here does not change even if the integration degree of the photoelectric conversion element 10 is increased.

  When the size of each photoelectric conversion element 10 (size in plan view) is reduced due to high integration of the photoelectric conversion elements 10, the size of the microlens 95 is also reduced. Therefore, when the microlens is manufactured by the above-described method. The focal point tends to be above the desired position (on the microlens 95 side).

  However, when the first transfer electrodes 25a to 25e are configured as described above, the upper surface of the photoelectric conversion element 10 and the first transfer electrodes 25a to 25e are compared with the case where the first transfer electrode has a so-called overlapping transfer electrode structure. The maximum difference with the upper surface can be reduced. The distance between the upper surface of the photoelectric conversion element 10 and the lower surface of the microlens 95 corresponding to the photoelectric conversion element 10 can be made relatively short.

  For this reason, even if the size of the photoelectric conversion element 10 is reduced, it is easy to control the focal position of the microlens 95 to a desired position.

  In addition, since the step formed around the photoelectric conversion element 10, particularly the step formed in the photoelectric conversion element row direction, is lower than in the case where the first transfer electrode has a so-called overlapping transfer electrode structure. Light having a large incident angle with respect to the surface of the substrate 1 is likely to enter the photoelectric conversion element 10.

  For these reasons, it is easy to improve the resolution of the solid-state image sensor 100 by increasing the integration of the photoelectric conversion elements 10 while suppressing the decrease in sensitivity of the solid-state image sensor 100. Further, in the imaging apparatus using the solid-state imaging device 100, the sensitivity of the solid-state imaging device 100 is also prevented from greatly fluctuating according to the F value of the imaging optical system.

  In general, the first transfer electrodes 25a to 25e constituting the vertical charge transfer element 20 and the transfer electrode constituting the horizontal charge transfer element 40 (hereinafter referred to as “second transfer electrode”) are manufactured in the same process. . When the first transfer electrodes 25a to 25e are configured as described above, it is preferable that the second transfer electrodes have the same configuration.

  FIG. 6 schematically shows an example of the horizontal charge transfer element 40 (hereinafter, referred to as “horizontal charge transfer element 40A”) in which the second transfer electrode has the same configuration as the first transfer electrodes 25a to 25e. In the figure, an example of a specific configuration of the charge detection circuit 50 is also shown.

  Among the constituent elements shown in the figure, the constituent elements already shown in FIG. 1 are given the same reference numerals as those used in FIG.

  The illustrated horizontal charge transfer element 40A includes one second charge transfer channel 43 (hereinafter referred to as “horizontal charge transfer channel 43”) formed in the semiconductor substrate 1 and the horizontal charge transfer channel 43 in plan view. Two types of second transfer electrodes 45a to 45b traversing are provided.

The horizontal charge transfer channel 43 has, for example, a configuration in which an n-type impurity addition region 43a and an n ⁻ -type impurity addition region 43b are repeatedly arranged in this order from the downstream side to the upstream side. Two n ^- type impurity doped regions 43 a and two n ⁻ -type impurity doped regions 43 b correspond to one vertical charge transfer element 20. In FIG. 6, the n-type impurity added region 43a is hatched to make it easy to understand the n-type impurity added region 43a and the n ⁻ -type impurity added region 43b.

For each vertical charge transfer element 20, two types of second transfer electrodes 45a to 45b are arranged one by one from the downstream side toward the upstream side in this order. One second transfer electrode 45a or 45b covers one n-type impurity added region 43a and one n ⁻ -type impurity added region 43b arranged on the upstream side in plan view.

  Each of the second transfer electrodes 45a is supplied with a horizontal drive signal φH2, and each of the second transfer electrodes 45b is supplied with a horizontal drive signal φH1. Each second transfer electrode 45b also functions as a gate electrode that controls transfer of charges from the vertical charge transfer element 20 to the horizontal charge transfer element 40A.

  Each of these second transfer electrodes 45a to 45b has a strip-like main electrode layer (hereinafter referred to as “second main electrode layer”), similarly to the first transfer electrodes 25a and 25b described with reference to FIG. And a sub-electrode layer formed on the side surface of the second main electrode layer and having a cross-sectional shape with a rounded shoulder (hereinafter also referred to as “second sub-electrode layer”). The upper surfaces of the second transfer electrodes 45a to 45b are substantially located on the same plane.

  The individual second transfer electrodes 45a to 45b are covered with an electrical insulating film made of, for example, a silicon oxide film (thermal oxide film).

  When the horizontal charge transfer element 40A is configured as described above, the number of photomasks required in the manufacturing process is reduced by one compared to the case where the horizontal charge transfer element 40 has a so-called overlapping transfer electrode structure. be able to.

  The horizontal charge transfer element 40A is driven by two-phase horizontal drive signals φH1 and φH2, and sequentially transfers charges received from each of the vertical charge transfer elements 20 to the charge detection circuit 50.

  The charge detection circuit 50 includes an output gate 51 connected to the output terminal of the horizontal charge transfer element 40A, and a floating diffusion region 52 (hereinafter referred to as “FD region 52”) formed in the semiconductor substrate 1 adjacent to the output gate 51. A floating diffusion amplifier 53 (hereinafter abbreviated as “FDA 53”) electrically connected to the FD region 52, a reset gate 54 disposed adjacent to the FD region 52, and a reset. A drain region 55 formed in the semiconductor substrate 1 is adjacent to the gate 54. The FD region 52, the reset gate 54, and the drain region 55 constitute a reset transistor.

The output gate 51 receives the supply of the DC voltage V _OG and performs charge transfer from the horizontal charge transfer element 40 </ b> A to the FD region 52.

  The FDA 53 detects the charge transferred from the horizontal charge transfer element 40A to the FD region 52 based on the potential fluctuation of the FD region 52, generates a signal voltage, amplifies the signal voltage, and generates a pixel signal. This pixel signal becomes an output from the solid-state image sensor 100.

The charge detected by the FDA 53 or the charge that does not need to be detected by the FDA 53 is swept out to the drain region 55 through the reset gate 54 and is absorbed by, for example, the power supply voltage V _DD . The operation of the reset gate 54 is controlled by the drive signal φRS.

  Next, the solid-state image sensor according to the first embodiment will be described. FIG. 7 schematically shows a cross-sectional structure of the solid-state imaging device 150 according to the first embodiment. Among the constituent elements shown in the figure, those already in common with the constituent elements shown in FIG. 5 are given the same reference numerals as those used in FIG. 5 and their description is omitted. However, a new reference numeral 70A is given to the interlayer insulating film.

  As is clear from the comparison between FIG. 7 and FIG. 5, the solid-state imaging device 150 includes (i) the point that the interlayer insulating film 70 </ b> A and the passivation film 75 have flat upper surfaces, and (ii) the first planarization film 80. Is significantly different in configuration from the solid-state imaging device 100 according to the first reference example.

  The interlayer insulating film 70A is formed of, for example, a silicon oxide material, that is, BPSG, PSG, BSG, or silicon oxide (including spin-on glass). The interlayer insulating film 70A is slightly thicker than the interlayer insulating film 70 shown in FIG. 5, and the film thickness above the central portion of the photoelectric conversion element 10 is, for example, about 1 μm.

  The planarization of the interlayer insulating film 70A can be performed by reflow, etch back, chemical mechanical drilling, or the like. When the interlayer insulating film 70A is formed of spin-on glass, the upper surface of the photoelectric conversion element 10 can be planarized without performing any particular planarization treatment if the degree of integration of the photoelectric conversion elements 10 is high to some extent.

  By planarizing the interlayer insulating film 70A, the passivation film 75 formed thereon is naturally planarized. The first planarizing film 80 shown in FIG. 5 can be omitted, and the color filter array 85, the second planarizing film 90, and the microlens 95 can be sequentially formed on the passivation film 75.

  Compared with the case of the layer configuration shown in FIG. 5, the distance between the upper surface of the photoelectric conversion element 10 and the lower surface of the microlens 95 corresponding to the photoelectric conversion element 10 can be shortened. Even when the size of the photoelectric conversion element 10 is reduced, the focal position of the microlens 95 can be controlled more easily.

  As in the case of the layer configuration shown in FIG. 5, light having a large incident angle with respect to the surface of the semiconductor substrate 1 is likely to enter the photoelectric conversion element 10. Further, since the thickness of the passivation film 75 is substantially constant, the refraction of light in the passivation film 75 becomes substantially uniform, and more light can be incident on the photoelectric conversion element 10.

  In the illustrated solid-state imaging device 150, compared to the solid-state imaging device 100 described above, it is easy to improve the resolution by increasing the integration of the photoelectric conversion device 10 while suppressing a decrease in sensitivity. In addition, in the imaging device using the solid-state imaging device 150, it is possible to suppress the sensitivity from fluctuating greatly according to the F value of the imaging optical system, compared to the imaging device using the solid-state imaging device 100.

  Regarding a solid-state imaging device having a vertical charge transfer device with a so-called superposition transfer electrode structure, changes in sensitivity and horizontal shading rate due to planarization of the interlayer insulating film are verified, and the relationship between the F value and sensitivity of the imaging optical system Verified.

  FIG. 8 shows the photoelectric conversion element 10, the vertical charge transfer element 20, the read gate 30, the horizontal charge transfer element 40, and the charge detection circuit 50 in the solid-state imaging element 200 (hereinafter referred to as “test product”) used for verification. The plane arrangement of is schematically shown. Although not shown in FIG. 8, one red, green, or blue color filter is disposed above each photoelectric conversion element 10, and one microlens is disposed thereon. Yes. In the test product, the number of photoelectric conversion element columns is larger than the number of photoelectric conversion element rows, and the width in the photoelectric conversion element row direction is wider than the width in the photoelectric conversion element column direction.

  FIG. 9 schematically shows a cross-sectional structure of a test article including a microlens not shown in FIG. This figure corresponds to a cross section taken along line IX-IX shown in FIG.

  The solid-state imaging device 200 shown in these drawings is greatly different from the solid-state imaging device 100 shown in FIG. 1 or FIG. 4 in that the vertical charge transfer device 20 has a so-called overlapping transfer electrode structure. For the solid-state imaging device 200, the same reference numerals as those used in FIG. 1 or FIG. 4 are used except that each of the first transfer electrodes is given a new reference numeral obtained by adding 100 to the reference numeral used in FIG. A description thereof will be omitted.

  As shown in FIGS. 8 and 9, in the solid-state imaging device 200, the edge of the first transfer electrode 125a in the line width direction overlaps the edge of the adjacent first transfer electrode 125b in the line width direction. The interlayer insulating film 70A is formed of a BPSG film having a thickness of about 1.7 μm above the central portion of the photoelectric conversion element 10, and the passivation film 75 is formed of a silicon nitride film having a thickness of about 0.2 μm. .

  The opening 65a formed in the light shielding film 65 on each photoelectric conversion element 10 has a substantially rectangular shape in plan view, and its size is approximately 0.8 × 1.0 μm. The distance from the upper surface of each photoelectric conversion element 10 to the lower surface of the microlens 95 is about 3.5 μm. Each microlens 95 has a substantially rectangular shape in plan view, and its size is approximately 2.85 × 2.85 μm.

  For comparison, (i) a point having the first planarizing film 80 shown in FIG. 4 and (ii) a point in which the unevenness of the base is reflected on the upper surfaces of the interlayer insulating film and the passivation film. A solid-state imaging device (hereinafter referred to as “control product”) having the same configuration as that of the test product except for the respective components was prepared.

  In this control product, an interlayer insulating film is formed by a BPSG film having a film thickness of approximately 0.7 μm above the center of the photoelectric conversion element, and silicon having a film thickness of approximately 0.2 μm above the center of the photoelectric conversion element. A passivation film is formed by the nitride film. The first planarization film is formed by a photoresist layer having a thickness of about 2.0 μm above the center of the photoelectric conversion element, and the distance from the upper surface of the photoelectric conversion element to the lower surface of the microlens is about 4.5 μm. It is.

  FIG. 10 shows the sensitivity of the test product with respect to white light having a color temperature of 5100 ° K as a relative value when the sensitivity of the control product is 1. The sensitivity was measured for each of the red pixel, the green pixel, and the blue pixel for both the test product and the control product.

  Here, the red pixel means a photoelectric conversion element in which a red color filter is arranged above, and the green pixel means a photoelectric conversion element in which a green color filter is arranged above, and a blue pixel and Means a photoelectric conversion element in which a blue color filter is disposed above.

  As is clear from the figure, in the test product, the sensitivity of each of the red pixel, the green pixel, and the blue pixel is 10% or more higher than the sensitivity of the control product.

  FIG. 11 shows the horizontal shading rate of the test product as a relative value when the horizontal shading rate of the control product is 1.

  The horizontal shading rate is measured by measuring the value of the pixel signal for one frame output from the charge detection circuit 50 when the uniform light is irradiated for both the test product and the control product. Calculation was performed for each pixel and blue pixel.

  As is clear from the figure, in the test product, the horizontal shading rate of each of the red pixel, the green pixel, and the blue pixel is 20% or more lower than that of the control product.

  FIG. 12 shows the relationship between the F value of the imaging optical system in the imaging apparatus using the solid-state imaging device and the sensitivity of the test product and the control product, relative to each sensitivity when the F value is 8, Shown by value.

  As is clear from the figure, the test product is less sensitive to the F value than the control product.

  The improvement in the sensitivity of the test article, the reduction in the horizontal shading rate, and the reduction in the dependence of the sensitivity on the F value of the imaging optical system are all (i) photoelectricity associated with omitting the first planarization film 80. By shortening the distance between the conversion element 10 and the microlens 95, the focal position of the microlens 95 approaches the photoelectric conversion element 10, and the amount of incident light on the photoelectric conversion element 10 increases, and (ii) the interlayer insulating film 70A By making the thickness of the passivation film 75 uniform along with the planarization of light, light that is refracted in an undesired direction by the passivation film is reduced, and the amount of incident light on the photoelectric conversion element 10 is increased. Inferred.

  Since the above-described effect is obtained in the test product (solid-state imaging device 200) including a vertical charge transfer device having a so-called superimposed transfer electrode structure, in the solid-state imaging device 150 according to the first embodiment shown in FIG. Further improvement in sensitivity, reduction in horizontal shading rate, and reduction in sensitivity dependency on the F value of the imaging optical system are expected.

  Alternatively, even when the integration degree of the photoelectric conversion element 10 is further increased, it is expected that it is possible to easily suppress a decrease in sensitivity, an increase in the horizontal shading rate, and an increase in sensitivity dependency on the F value of the imaging optical system. The

  Next, a solid-state image sensor according to the second embodiment will be described. FIG. 13 schematically shows a planar arrangement of a photoelectric conversion element, a charge transfer element, a readout gate, a charge detection circuit, and a discharge drain in the solid-state imaging device according to the second embodiment. Among the constituent elements shown in the figure, those structurally common to the constituent elements shown in FIG. 1 or FIG. 6 are given the same reference numerals as those used in FIG. 1 or FIG. Is omitted.

  A solid-state image pickup device 300 shown in the figure is a solid-state image pickup device used as a linear image sensor for black and white and color photography. In the solid-state image pickup device 300, a large number of photoelectric conversion devices are formed on one surface of a semiconductor substrate 1. 10 are arranged in four rows.

  A channel region for a read gate is formed on the semiconductor substrate 1 corresponding to each photoelectric conversion element 10 one by one. Each of the readout gate channel regions corresponding to one photoelectric conversion element row is covered in plan view by one readout gate electrode 335 disposed on the semiconductor substrate 1 via an electrical insulating film, A read gate 30 is configured. The operation of each read gate 30 is controlled by a drive signal φR1, φR2, φR3, or φR4 supplied to the read gate electrode 335. In FIG. 13, the individual read gates 30 are hatched for easy understanding of the position of the read gate 30.

  One charge transfer element 40B is arranged along each photoelectric conversion element array, one for each photoelectric conversion element array. Each charge transfer element 40B has, for example, four transfer electrodes per photoelectric conversion element 10, and instead of the second transfer electrode 45b shown in FIG. 6, for example, the second transfer electrode 45a shown in FIG. It is constituted by a two-phase drive type CCD having a transfer electrode having the same shape.

  Each of the charge transfer elements 40 </ b> B can be electrically connected to the corresponding photoelectric conversion element 10 via the read gate 30. One charge detection circuit 50 is connected to the output terminal of each charge transfer element 40B.

One drain region 360 is arranged along one photoelectric conversion element array, one for each photoelectric conversion element array. Each drain region 360 is configured by, for example, an n ⁺ -type impurity doped region formed in the semiconductor substrate 1. A channel region is interposed between one drain region 360 and a corresponding photoelectric conversion element array. This channel region is covered in plan view by a single discharge gate electrode 365 disposed on the semiconductor substrate 1 via an electrical insulating film, thereby forming a discharge gate. The operation of each sweep gate is controlled by a drive signal φD1, φD2, φD3, or φD4 supplied to the sweep gate electrode 365.

  In the solid-state imaging device 300 shown in the drawing, a color image pixel signal is generated based on the charges accumulated in the upper three photoelectric conversion element rows. A red color filter is disposed above one photoelectric conversion element array, a green color filter is disposed above the other photoelectric conversion element array, and above the remaining one photoelectric conversion element array. A blue color filter is arranged. The charge transfer elements 40B corresponding to these photoelectric conversion element arrays are driven by the two-phase drive signals φ1 and φ2, and transfer the charges read from the corresponding photoelectric conversion elements 10 to the charge detection circuit 50.

  The electric charge accumulated in the remaining one photoelectric conversion element array is used to generate a pixel signal for a monochrome image. Above this photoelectric conversion element array, for example, a monochromatic colored layer corresponding to a color filter used for color photography, or a transparent layer instead of this colored layer is arranged. The charge transfer element 40 </ b> B corresponding to the photoelectric conversion element array is driven by the two-phase drive signals φ <b> 3 and φ <b> 4 and transfers the charges read from the corresponding photoelectric conversion elements 10 to the charge detection circuit 50.

  In a solid-state imaging device used as a linear image sensor, a light shielding film is often not provided. In many cases, a condensing element is not disposed above the solid-state imaging element. A light shielding film and a microlens are provided as needed. Instead of the microlens, one cylindrical lens may be arranged for each photoelectric conversion element array.

  For this reason, compared with a solid-state image sensor used as an area image sensor, a solid-state image sensor used as a linear image sensor can shorten the distance between the upper surface of the photoelectric conversion element and the lower surface of the light condensing element. Few cases are needed.

  However, if the transfer electrodes constituting the charge transfer element are configured similarly to the second transfer electrodes 45a to 45b shown in FIG. 6, for example, when one microlens is arranged above each photoelectric conversion element. The same effects as those of the solid-state imaging device 100 according to the first reference example described above can be obtained.

  Moreover, it becomes easy to reduce manufacturing cost. For example, in order to form a transfer electrode having a superimposed transfer electrode structure using photolithography technology, a process of manufacturing a first-layer transfer electrode and a process of manufacturing a second-layer transfer electrode In each case, it is necessary to prepare a mask having a predetermined shape necessary for patterning the conductive layer.

  On the other hand, if the transfer electrode has the same configuration as the second transfer electrodes 45a to 45b described above, the number of masks necessary for manufacturing these transfer electrodes can be reduced by one.

  Further, if the interlayer insulating film is planarized as shown in FIG. 7, a desired layer can be formed in the subsequent process without considering the base pattern dependency, and the first planarizing film is omitted. It is easy to improve the yield.

  For these reasons, it becomes easy to reduce the manufacturing cost. The same applies to the solid-state imaging device used as an area image, such as the solid-state imaging device 100 according to the first reference example and the solid-state imaging device 150 according to the first embodiment.

  Next, a semiconductor device according to a second reference example will be described. FIG. 14 schematically shows a cross-sectional structure of a semiconductor device according to a second reference example. The semiconductor device 400 shown in the figure includes a p-type semiconductor substrate 401, a field oxide film 410 formed on one surface of the p-type semiconductor substrate 401 to define first and second active regions 403 and 406, and an active region A p-channel MOS field effect transistor (hereinafter abbreviated as “p-channel MOSFET”) 420 disposed in 403, and an n-channel MOS field effect transistor (hereinafter referred to as this transistor) disposed in the active region 406. Is abbreviated as “n-channel MOSFET”) 430, a plurality of signal lines 450 disposed on the field oxide film 410, and an interlayer insulating film 460 covering these.

  The first active region 403 is constituted by an n-type well region, in which a p-type first drain region 421 and a p-type first source region 422 are formed with a space therebetween. For example, the first gate electrode 425 formed of polysilicon is disposed on the first active region 403 via the first gate insulating film 427. The first drain region 421, the first source region 422, the first gate insulating film 427, and the first gate electrode 425 constitute a p-channel MOSFET 420.

  The second active region 406 is constituted by a p-type well region, in which an n-type second drain region 431 and an n-type second source region 432 are formed with a space therebetween. For example, the second gate electrode 435 formed of polysilicon is disposed on the second active region 406 via the second gate insulating film 437. The second drain region 431, the second source region 432, the second gate insulating film 437, and the second gate electrode 435 constitute an n-channel MOSFET 430.

  The first drain region 421 and the second drain region 431 include the first contact plug P1 that passes through the interlayer insulating film 460 and the first gate electrode 427 and is in contact with the first drain region 421, and the interlayer insulating film 460 and the second gate. The second contact plug P2 that penetrates the electrode 437 and contacts the second drain region 431 is electrically connected to the first upper layer wiring 470. The p-channel MOSFET 420 and the n-channel MOSFET 430 constitute a complementary MOS field effect transistor 440.

  The first source region 422 is connected to the second upper layer wiring 471 by a third contact plug that penetrates the interlayer insulating film 460 and the first gate electrode 427, and the second source region 432 is connected to the interlayer insulating film 460 and the second gate electrode. A fourth contact plug passing through 437 is connected to the third upper layer wiring 472.

  Like the first transfer electrodes 25a and 25b shown in FIG. 2, each of the signal lines 450 is formed in a strip-like main electrode layer 450M and a side surface of the main electrode layer 450M, and has a cross-sectional shape with rounded shoulders. A sub-electrode layer 450S. Each signal line 450 is covered with a separate electrical insulating film IF.

  In the semiconductor device 400 shown in the figure, even if each of the main electrode layers 450M is formed under an interval of about 0.3 μm, the interval between adjacent signal lines 450 can be easily reduced to about 0.2 μm or even smaller. It is also easy to reduce the interval to about 0.1 μm or even smaller. It is easy to increase the degree of integration at a relatively low manufacturing cost.

  The solid-state imaging device according to the embodiment has been described above, but the present invention is not limited to the above-described embodiment.

  In particular, various configurations other than the configuration and arrangement of the transfer electrodes constituting the charge transfer element can be variously changed.

  For example, a solid-state imaging device used as an area image may be a device in which a large number of photoelectric conversion elements are arranged in a square matrix over a plurality of rows and a plurality of columns. Here, the “square matrix shape” includes a case where the number of rows and the number of columns are different.

  In addition, a charge transfer element used as a vertical charge transfer element in a solid-state imaging device used as an area image may have one, or three or more transfer electrodes in one photoelectric conversion element row. Good. A charge transfer element used as a horizontal charge transfer element can be configured by arranging two or more transfer electrodes per vertical charge transfer element.

  The number of transfer electrodes corresponding to one photoelectric conversion element row or the number of transfer electrodes corresponding to one vertical charge transfer element depends on the number of phases of driving signals for driving the vertical charge transfer element and the horizontal charge transfer element. Or, it can be appropriately selected according to the driving method of the vertical charge transfer element or the horizontal charge transfer element. The same applies to a charge transfer element in a solid-state image sensor used as a linear image sensor.

  The number of photoelectric conversion element arrays in a solid-state image sensor used as a linear image sensor can be appropriately selected according to the application.

  The method of manufacturing the transfer electrode is not limited to the method described with reference to FIGS. 3A to 3E, and is appropriately selected according to the materials of the main electrode layer and the sub electrode layer.

  For example, FIGS. 15A to 15E conceptually show a manufacturing process when the main electrode layer EM is formed of polysilicon and the sub-electrode layer ES is formed of metal silicide. Among the constituent elements shown in these drawings, those common to the constituent elements shown in FIGS. 3 (A) to 3 (E) are designated by the reference numerals used in FIGS. 3 (A) to 3 (E). The same reference numerals are given and description thereof is omitted.

  First, as shown in FIGS. 15A and 15B, the first conductive layer 110 is patterned by performing the same processes as those shown in FIGS. 3A and 3B. A main electrode layer EM is formed. At this time, on the first conductive layer 110, a second electrical insulating layer such as a silicon oxide film or a silicon nitride film is used instead of the stopper layer 115 shown in FIGS. 3A and 3B. 115A is deposited. The second electrically insulating layer 115A may or may not have a function as an etching stopper. After forming the main electrode layer EM, the resist mask 120 is removed.

  As shown in FIG. 15C, the second conductive layer 130 used as the material for the sub-electrode layer is deposited on the second electrically insulating layer 115A and on the exposed surface of the first electrically insulating layer 5. .

  The second conductive layer 130 is formed of a metal that can be silicide, such as cobalt, chromium, nickel, tungsten, titanium, molybdenum, and tantalum. The film thickness of the second conductive layer 130 is preferably less than ½ of the distance between two adjacent main electrode layers EM.

  When the first conductive layer 110 is formed of polysilicon, the natural oxide film formed on the surface of the main electrode layer EM is removed by, for example, vapor-phase hydrofluoric acid treatment prior to the deposition of the second conductive layer 125. It is preferable to do.

  Thereafter, the second conductive layer 130 is subjected to a heat treatment using a short time annealing apparatus (RTA) or the like. This heat treatment is performed in an inert gas atmosphere such as nitrogen gas or argon gas. The heat treatment condition is appropriately selected according to what the second conductive layer 130 is formed by.

  By the above heat treatment, the second conductive layer 130 is silicided over the range corresponding to the heat treatment conditions from the main electrode layer EM side only in the region where the main electrode layer EM and the second conductive layer 130 are in direct contact with each other. become. In other places, the second conductive layer 130 does not become silicide. This is so-called salicide (self-aligned silicide).

  As shown in FIG. 15D, the second conductive layer 130 that has not been silicided is removed using ammonia, hydrogen peroxide, or the like, and only the side surfaces of the main electrode layers EM are silicided. Two conductive layers 130 are left. The silicided second conductive layer 130 becomes the sub-electrode layer ES. A transfer electrode having the main electrode layer EM and the sub electrode layer ES is obtained.

  As shown in FIG. 15E, the second electrically insulating layer 115A is removed. For example, when a silicon nitride film is used as the second electrically insulating layer 115A, the second electrically insulating layer 115A can be removed with hot phosphoric acid.

  After forming the sub-electrode layer ES, if necessary, the sub-electrode layer ES is subjected to a heat treatment using a short time annealing device or the like to improve its conductivity. This heat treatment is performed in an inert gas atmosphere such as nitrogen gas or argon gas, and the conditions are appropriately selected according to the composition of the sub-electrode layer ES. The heat treatment can be performed before the step illustrated in FIG. 15E or can be performed after the step illustrated in FIG.

  If the second electrical insulating film 115A is omitted, a metal silicide layer can be formed also on the main electrode layer EM.

  The sub-electrode layer ES made of metal silicide can be formed by depositing a metal silicide phase as the second conductive layer 125 shown in FIG. 3 in addition to the salicide technique. it can.

  The configuration and arrangement of the transfer electrode described with reference to FIGS. 2, 3A to 3E, and 15A to 15E are used in various semiconductor devices other than the solid-state imaging device. Can also be applied as the configuration and arrangement of signal lines. If signal lines are formed using this configuration and arrangement, the degree of integration of the semiconductor device can be improved.

  It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.

It is the schematic which shows the planar arrangement | positioning of the photoelectric conversion element in the solid-state image sensor by a 1st reference example, a 1st charge transfer element, a read gate, a 2nd charge transfer element, and a charge detection circuit. It is the schematic which shows the structure and arrangement | positioning of the 1st transfer electrode in the cross section along the II-II line shown in FIG. FIG. 3A to FIG. 3E are conceptual diagrams illustrating an example of the manufacturing process of the first transfer electrode. It is the schematic which shows the cross section along the IV-IV line | wire shown in FIG. It is the schematic which shows the cross section along the II-II line | wire shown in FIG. FIG. 3 is a schematic diagram illustrating an example of a horizontal charge transfer element in which the configuration and arrangement of a second transfer electrode are the same as those of the first transfer electrode illustrated in FIG. 2. It is the schematic which shows the cross-section of the solid-state image sensor by a 1st Example. FIG. 3 is a schematic diagram showing a planar arrangement of a photoelectric conversion element, a vertical charge transfer element, a readout gate, a horizontal charge transfer element, and a charge detection circuit in a solid-state imaging device used for verifying an effect accompanying planarization of an interlayer insulating film is there. It is the schematic which shows the cross section along the IX-IX line shown in FIG. The sensitivity of each of the red pixel, the green pixel, and the blue pixel in the solid-state imaging device illustrated in FIG. 8 is expressed as a relative value when the sensitivity of each of the red pixel, the green pixel, and the blue pixel in the control product is 1. It is a graph. When the horizontal shading rates of the red pixel, the green pixel, and the blue pixel in the solid-state imaging device shown in FIG. It is a graph shown with a relative value. 9 is a graph showing the relationship between the sensitivity of the solid-state imaging device shown in FIG. 8 and the F value of the imaging optical system as a relative value when the sensitivity when the F value is 8 is 1. It is the schematic which shows the planar arrangement | positioning of the photoelectric conversion element in the solid-state image sensor by a 2nd Example, a charge transfer element, a read gate, a charge detection circuit, and a discharge drain. It is sectional drawing which shows roughly the structure and arrangement | positioning of a signal wire | line in the semiconductor device by a 2nd reference example. FIG. 15A to FIG. 15E are conceptual diagrams showing an example of a manufacturing process when the main electrode layer of the transfer electrode is formed of polysilicon and the sub-electrode layer is formed of metal silicide.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 10 ... Photoelectric conversion element, 20 ... 1st charge transfer element, 23 ... 1st charge transfer channel (vertical charge transfer channel), 25a-25e ... 1st transfer electrode, 25aM, 25bM, EM ... Main electrode layer, 25aS, 25bS, ES ... sub-electrode layer, 30 ... read gate, 40, 40A ... second charge transfer element, 40B ... charge transfer element, 43 ... second charge transfer element (horizontal charge transfer element) 45a to 45b ... second transfer electrode, 50 ... charge detection circuit, 65 ... light shielding film, 70, 70A ... interlayer insulating film, 75 ... passivation film, 80 ... first planarization film, 95 ... microlens, 100 , 150, 200, 300 ... solid-state imaging device, 110 ... first conductive layer, 125, 130 ... second conductive layer.

Claims (2)

A semiconductor substrate;
A plurality of photoelectric conversion elements arranged in a matrix over a plurality of rows and columns on one surface of the semiconductor substrate;
A first charge transfer element that is arranged corresponding to one photoelectric conversion element row, and each of which can read out charges from the corresponding photoelectric conversion elements and transfer the charges; ,
A second charge transfer element electrically connectable to each of the first charge transfer elements;
All of the first charge transfer elements and the second charge transfer elements are electrically separated from each other to cover each of the first charge transfer elements and the second charge transfer elements in plan view, and A light shielding film having one opening above each of the conversion elements;
An interlayer insulating film formed of a silicon oxide-based material, covering the light shielding film and the opening in plan view, and having a flat upper surface;
A solid-state imaging device comprising: a passivation film disposed on the interlayer insulating film. A semiconductor substrate;
A plurality of photoelectric conversion elements arranged in at least one row on one surface of the semiconductor substrate;
A charge transfer element disposed corresponding to each one photoelectric conversion element array;
An interlayer insulating film that is formed of a silicon oxide-based material and covers all of the charge transfer elements in plan view, and has a flat upper surface;
A solid-state imaging device comprising: a passivation film disposed on the interlayer insulating film.

Images