JP2010225769A - Solid-state imaging element and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element capable of further enhancing sensitivity while keeping chip size. <P>SOLUTION: The solid-state imaging element 10, in which a plurality of photoelectric conversion part columns each comprising a plurality of photoelectric conversion parts 1 arranged in a column line in a semiconductor substrate 11 are arranged in a row direction orthogonal to the column direction, includes: vertical charge transfer paths 3 each used for transferring, in the column direction, charge generated in the respective photoelectric conversion parts 1 in the photoelectric conversion part column; and overflow drains (OFD) 4 each used for discharging excessive charge accumulated in the respective photoelectric conversion parts of the photoelectric conversion part column, wherein the vertical charge transfer paths 3 and the OFDs 4 are alternately arranged in the row direction between the plurality of photoelectric conversion part columns, each vertical charge transfer path 3 is shared between two of the photoelectric conversion part columns adjacent to the vertical charge transfer path 3, and each OFD 4 is shared between two of the photoelectric conversion part columns adjacent to the OFD 4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus.

  In a solid-state imaging device such as a CCD image sensor, an overflow drain (OFD) is generally provided in order to discharge an excessive charge of a photodiode.

  Patent Document 1 discloses a so-called lateral OFD in which an OFD is provided next to a photodiode. Such a lateral OFD is disadvantageous for miniaturization because a space for forming the OFD is required separately from the photodiode. Patent Document 1 also discloses a configuration in which an electrode is provided on the overflow gate between the OFD and the photodiode, and the potential of the overflow gate is controlled by this electrode so that the saturation capacitance of the photodiode can be changed. ing. However, as the miniaturization progressed, it became difficult to form this electrode.

  For these reasons, the horizontal OFD is no longer used in solid-state imaging devices that have been miniaturized in recent years, and a so-called vertical OFD in which an OFD is provided directly below the photodiode is used. It has become mainstream (see Patent Document 2).

  FIG. 5 is a schematic cross-sectional view of a pixel portion having a vertical OFD. The pixel portion shown in FIG. 5 has a configuration having an n-type impurity layer 102 formed in a p-well layer 101 on an n-type silicon substrate 100 and a p-type impurity layer 103 provided on the surface thereof. . A photodiode is constituted by a pn junction between the n-type impurity layer 102 and the p-well layer 101.

  FIG. 6 is a diagram showing the potential along the substrate depth direction in the a-a ′ cross section shown in FIG. 5. As shown in FIG. 6, the p-well layer 101 forms a potential barrier peak on the substrate side of the photodiode, and charges generated in response to light incident at a position deeper than the potential barrier peak are Without being accumulated in n-type impurity layer 102, it is discharged to n-type silicon substrate 100.

  On the other hand, FIG. 7 is a schematic cross-sectional view of a pixel portion having a horizontal OFD. The pixel portion shown in FIG. 7 has an n-type impurity layer 202 formed in the p-type silicon substrate 200 and a p-type impurity layer 203 provided on the surface thereof. A photodiode is configured by a pn junction between the n-type impurity layer 202 and the p-type silicon substrate 200.

  FIG. 8 is a diagram showing the potential along the substrate depth direction in the b-b ′ cross section shown in FIG. 7. As shown in FIG. 8, the potential barrier peak on the substrate side of the photodiode exists at a position deeper than the vertical OFD. Therefore, according to the structure employing the horizontal OFD, charges generated deeper in the p-type silicon substrate 200 can be accumulated in the n-type impurity layer 202 of the photodiode than in the structure employing the vertical OFD. There is an advantage that can be improved.

  As described above, the horizontal OFD is advantageous in terms of sensitivity improvement. However, since it is difficult to cope with miniaturization as described above, in recent years, the vertical OFD has been adopted and the shape of the transfer path has been devised. The sensitivity was improved by expanding the photodiode aperture and increasing the saturation capacitance. However, the expansion of the saturation capacity is approaching its limit, and a new structure for further enhancement of sensitivity has been demanded.

Japanese Patent Laid-Open No. 56-1005727 JP-A-57-55672

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of further increasing the sensitivity while maintaining the chip size and an imaging apparatus including the same.

  The solid-state imaging device of the present invention is a solid-state imaging device in which a plurality of photoelectric conversion unit columns each including a plurality of photoelectric conversion units arranged in a column direction in a semiconductor substrate are arranged in a row direction orthogonal to the column direction. A charge transfer unit that transfers charges generated in each photoelectric conversion unit of the photoelectric conversion unit column in the column direction, and an overflow for discharging excess charge accumulated in each photoelectric conversion unit of the photoelectric conversion unit column A drain, and between the plurality of photoelectric conversion unit rows, any one of the charge transfer unit and the overflow drain is disposed, and the charge transfer unit and the overflow drain include the plurality of photoelectric conversion unit rows The two photoelectric conversion units arranged adjacent to each other in the row direction are shared by the two photoelectric conversion unit columns adjacent to the charge transfer unit and adjacent to the overflow drain. Share the said overflow drain in parts column.

  The imaging device of the present invention includes the solid-state imaging device.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can achieve further high sensitivity, maintaining an chip size, and an imaging device provided with the same can be provided.

1 is a schematic plan view of a solid-state image sensor for explaining an embodiment of the present invention. Sectional schematic diagram of the B-B 'line of the solid-state imaging device shown in FIG. Sectional schematic diagram which shows the 1st modification of the solid-state image sensor shown in FIG. Plane schematic diagram showing a second modification of the solid-state imaging device shown in FIG. Cross-sectional schematic diagram of a pixel portion having a vertical OFD The figure which showed the electric potential along the substrate depth direction in the a-a 'cross section shown in FIG. Cross-sectional schematic diagram of a pixel portion having a horizontal OFD The figure which showed the electric potential along the board | substrate depth direction in the b-b 'cross section shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic plan view of a solid-state imaging device for explaining an embodiment of the present invention. The solid-state imaging device is used by being mounted on an imaging device such as a digital camera or a video camera, an electronic endoscope or a camera-equipped mobile phone.

  A solid-state imaging device 10 shown in FIG. 1 includes a plurality of photoelectric conversion units 1 that are two-dimensionally arranged in a column direction in a p-type silicon substrate 11 and a row direction perpendicular thereto. The plurality of photoelectric conversion units 1 are arranged by arranging a plurality of photoelectric conversion unit columns including a plurality of photoelectric conversion units 1 arranged in the column direction in the row direction.

  The solid-state imaging device 10 accumulates in the vertical charge transfer path 3 that is a charge transfer unit that transfers charges generated in each photoelectric conversion unit 1 in the photoelectric conversion unit row in the column direction, and in each photoelectric conversion unit 1 in the photoelectric conversion unit row. And an overflow drain (hereinafter abbreviated as OFD) 4 for discharging the excess charge.

  The vertical charge transfer paths 3 and OFDs 4 are alternately arranged in the row direction between the photoelectric conversion unit columns arranged in the row direction. In the solid-state imaging device 10, two vertical photoelectric transfer unit columns adjacent to the vertical charge transfer channel 3 share the vertical charge transfer channel 3, and two photoelectric conversion unit columns adjacent to the OFD 4 share the OFD 4. It is a feature.

  “Two photoelectric conversion unit columns adjacent to the vertical charge transfer channel 3 share the vertical charge transfer channel 3” means that the charge generated and accumulated in each photoelectric conversion unit 1 of the two photoelectric conversion unit columns This means that the vertical charge transfer path 3 transfers in the column direction. For this reason, a read gate 2 is formed between the vertical charge transfer path 3 and each photoelectric conversion unit 1 of the two photoelectric conversion unit columns adjacent to the vertical charge transfer path 3. Charges can be read from the conversion unit row to the vertical charge transfer path 3 between them. Note that the readout gate 2 is formed at positions different from each other in the column direction between the photoelectric conversion units 1 adjacent to each other in the row direction, and two photoelectric conversion unit columns sharing the same with respect to one vertical charge transfer path 3. The charges can be read independently from each other.

  “Two photoelectric conversion unit rows adjacent to OFD 4 share this OFD 4” means that excess charge accumulated in each photoelectric conversion unit 1 of these two photoelectric conversion unit columns is discharged to this OFD 4. means. Therefore, an overflow gate (hereinafter abbreviated as “OFG”) 5 is formed between the OFD 4 and each photoelectric conversion unit 1 of the two photoelectric conversion unit columns adjacent to the OFD 4. Excess charge can be discharged from the photoelectric conversion unit array to the OFD 4 between them.

  The solid-state imaging device 10 further includes a horizontal charge transfer path 6 for transferring the charge transferred through the vertical charge transfer path 3 in the row direction, and a charge transferred through the horizontal charge transfer path 6 as a charge amount. And an output unit 7 that converts the signal into a signal corresponding to the output.

  FIG. 2 is a schematic cross-sectional view taken along line B-B ′ of the solid-state imaging device shown in FIG. 1. As shown in FIG. 2, the photoelectric conversion unit 1 is formed in a p-type silicon substrate 11. An n-type impurity layer 1b is formed in the p-type silicon substrate 11, and the pn junction between the n-type impurity layer 1b and the p-type silicon substrate 11 generates charges corresponding to incident light. The photoelectric conversion part 1 (photodiode) which accumulate | stores is comprised. The photoelectric conversion unit 1 is a so-called embedded photodiode in which a high-concentration p-type impurity layer 1a is provided on the surface of an n-type impurity layer 1b.

  An n-type impurity layer is formed between the two photoelectric conversion units 1 sharing the vertical charge transfer path 3, and this constitutes the vertical charge transfer path 3. A p-type impurity layer is formed between the vertical charge transfer path 3 and the left photoelectric conversion unit 1 among the two photoelectric conversion units 1 adjacent to the vertical charge transfer path 3. Between the vertical charge transfer path 3 and the right photoelectric conversion unit 1 of the two photoelectric conversion units 1 adjacent thereto, an element isolation region 8 made of a high-concentration p-type impurity layer is formed. The element isolation region 8 is also formed in a portion other than the region where the photoelectric conversion unit 1, the read gate 2, the vertical charge transfer path 3, the OFD 4, and the OFG 5 are formed.

  A transfer electrode 12 is formed on the read gate 2 and the vertical charge transfer path 3 via an insulating film 14. For example, two transfer electrodes 12 are provided for each photoelectric conversion unit 1, and the charges read to the vertical charge transfer path 3 can be transferred in the column direction by controlling the pulses applied thereto. Further, since the transfer electrode 12 also has a portion that overlaps with the read gate 2, the charge can be read from the photoelectric conversion unit 1 to the vertical charge transfer path 3 by applying a read pulse here.

  An n-type impurity layer is formed between the two photoelectric conversion units 1 sharing the OFD 4, and this constitutes the OFD 4. A p-type impurity layer is formed between the OFD 4 and the two photoelectric conversion units 1 adjacent to the OFD 4, and constitutes the OFG 5. The OFG 5 is configured to have a conductivity type opposite to that of the n-type impurity layer 1b serving as a charge storage unit of the photoelectric conversion unit 1, and forms a potential barrier between the photoelectric conversion unit 1 and the OFD 4. Since the photoelectric conversion unit 1 is covered with the element isolation region 8 and the read gate 2, the potential barrier between the photoelectric conversion unit 1 and the surrounding elements is obtained in a state where no read pulse is applied to the transfer electrode 12. In this case, the deepest one formed by the OFG 5 becomes the deepest, and excess charges (charges exceeding the saturation capacity) that cannot be accumulated in the photoelectric conversion unit 1 are discharged to the OFD 4 through this potential barrier.

  On the insulating film 14, a light shielding film 9 made of tungsten or the like having an opening K formed above the photoelectric conversion unit 1 is provided. On the light shielding film 9, a color filter, a microlens, and the like (not shown) are provided.

  In the solid-state imaging device 10 configured as described above, when light is incident, charges are generated and accumulated in the photoelectric conversion unit 1 accordingly. Excess charge exceeding the saturation capacity of the photoelectric conversion unit 1 is discharged to the OFD 4 through the OFG 5. After the exposure is completed, a read pulse is applied to the transfer electrode 12, and charges are read from the photoelectric conversion unit 1 to the vertical charge transfer path 3 via the read gate 2. The read charges are transferred to the output unit 7 via the horizontal charge transfer path 6 and output from there as a signal.

  As described above, according to the solid-state imaging device 10, since the vertical charge transfer path 3 is shared by two photoelectric conversion section rows adjacent to the vertical charge transfer path 3, one photoelectric conversion section row is used. In comparison with the conventional configuration in which one vertical charge transfer path is provided, the number of vertical charge transfer paths can be reduced to about half, and a space can be secured. In this space, an OFD 4 shared by two adjacent photoelectric conversion unit rows is formed, and a so-called horizontal OFD is realized. As a result, charges generated deep in the silicon substrate 11 can be accumulated in the photoelectric conversion unit 1, and sensitivity can be improved as compared with the configuration employing the vertical OFD. As described above, according to the solid-state imaging device 10, the chip size is the same as that of the miniaturized conventional configuration in which one vertical charge transfer path is provided for one photoelectric conversion unit row and the vertical OFD is adopted. In addition, the sensitivity can be improved.

  The solid-state imaging device 10 has a configuration in which the OFD 4 and the two OFGs 5 are formed in the region where the element isolation region 8, the vertical charge transfer path 3, and the readout gate 2 are formed in the conventional configuration. Unlike the vertical charge transfer path 3, the OFD 4 and the two OFGs 5 do not need to consider the charge storage capacity. Therefore, the width in the row direction of the OFD 4 and the two OFGs 5 can be made narrower than the width in the row direction of the element isolation region 8, the vertical charge transfer path 3, and the read gate 2.

  Therefore, in the solid-state imaging device 10, the width in the row direction including the OFD 4 and the two OFGs 5 is narrower than the width in the row direction including the element isolation region 8, the vertical charge transfer path 3, and the readout gate 2. . That is, the distance d1 in the row direction between the two photoelectric conversion units 1 adjacent to each other with the OFD 4 interposed therebetween is smaller than the distance d2 in the row direction between the two photoelectric conversion units 1 adjacent to each other with the vertical charge transfer path 3 interposed therebetween. ing. By doing so, the width of the solid-state imaging device 10 in the row direction can be made smaller than that of the conventional configuration, and the chip size can be reduced. If the chip size is not changed, the number of pixels can be increased.

  If the chip size is not changed, the photoelectric conversion unit 1 can be expanded to the region where the OFD 4 and the two OFGs 5 are formed to further improve sensitivity. For example, the sensitivity can be improved by enlarging the photoelectric conversion unit 1 and the opening K of the light shielding film 9 toward the region where the OFD 4 and the two OFGs 5 are formed. In addition, when the opening K of the light shielding film 9 is enlarged toward the region where the OFD 4 and the two OFGs 5 are formed in accordance with the enlargement of the photoelectric conversion unit 1, the vertical charge transfer path 3 is sandwiched as shown in FIG. The distance P1 in the row direction between the centers of the openings K above the two adjacent photoelectric conversion units 1 is greater than the distance P2 in the row direction between the centers of the openings K above the two adjacent photoelectric conversion units 1 across the OFD 4. And the sampling points in the row direction are not evenly spaced.

  Therefore, it is preferable to set d1 = d2. As a result, P1 = P2 and sampling points in the row direction can be equally spaced, so that good imaging is possible. Even in this case, since the OFD 4 and OFG 5 are provided in a space in which the vertical charge transfer path 3 is omitted in the conventional configuration, the sensitivity can be improved while the number of pixels and the chip size are equal to those in the conventional configuration. .

  When the vertical OFD is used instead of OFD4 and OFG5, the distance d1 can be further reduced, so that the opening K can be further widened to achieve higher sensitivity. However, in this case, the distance P2 becomes smaller, and the sampling point shift becomes remarkable. The present inventor pays attention to the fact that the horizontal OFD can improve the sensitivity compared to the vertical OFD, and the sensitivity is improved by the horizontal OFD, so that the distance d1 is made the same as the distance d2 to suppress the deviation of the sampling point. By focusing on this, high-sensitivity and high-quality elements have been realized.

  Hereinafter, modifications of the solid-state imaging device 10 shown in FIG. 1 will be described.

(First modification)
The solid-state imaging device of this modification has a configuration in which a control electrode 13 for controlling the potential of the OFG 5 is provided above the OFG 5 of the solid-state imaging device 10 shown in FIG. The plan view of the solid-state image sensor is the same as that in FIG.

  FIG. 3 is a schematic cross-sectional view corresponding to the line B-B ′ shown in FIG. 1 of the solid-state imaging device of the first modification. The difference from FIG. 2 is that a control electrode 13 is provided on the OFD 4 and OFG 5 via an insulating film 14, and the control electrode 13 is shielded by the light shielding film 9.

  The control electrode 13 provided above each of the two OFGs 5 adjacent to each other with the OFD 4 in between is formed from one upper side of the two OFGs 5 to the upper side of the other OFGs 5 across the OFD 4. There are two electrodes. The control electrode 13 has a linear shape extending in the column direction so as to overlap the OFD 4 and OFG 5 extending in the column direction.

  According to the solid-state imaging device of the first modified example configured as described above, the potential of the OFG 5 can be controlled by the voltage applied to the control electrode 13. For example, the saturation capacity of the photoelectric conversion unit 1 can be reduced by increasing the potential of the OFG 5, and the saturation capacity of the photoelectric conversion unit 1 can be increased by decreasing the potential of the OFG 5. By controlling the potential of the OFG 5 according to the imaging conditions, it is possible to perform optimal imaging that meets the conditions. Further, since the potential of the OFG 5 can be controlled, an electronic shutter function can be realized.

  Further, since the control electrode 13 is shared by two OFGs 5 adjacent to each other with the OFD 4 interposed therebetween, a conventional configuration in which one OFD 4, OFG 5, and the control electrode 13 are provided for one photoelectric conversion unit array. As compared with, the number of control electrodes 13 can be greatly reduced. As a result, even if the widths of OFD 4 and OFG 5 are the same as those of the conventional configuration, the width of the control electrode 13 in the row direction is wider in the configuration of the first modification. For this reason, the electrical resistance of the control electrode 13 is reduced, the delay of the pulse is reduced, and the discharge rate of excess charges from the photoelectric conversion unit 1 can be increased. In addition, since the width of the control electrode 13 in the row direction is increased, the control electrode 13 can be easily formed even with a chip size that is currently miniaturized.

(Second modification)
The solid-state imaging device of the second modification includes an odd-numbered photoelectric conversion unit row and an even-numbered photoelectric conversion unit row among the plurality of photoelectric conversion unit rows of the solid-state imaging device 10 illustrated in FIG. The photoelectric conversion units in the columns are arranged so as to be shifted in the column direction by 1/2 of the arrangement pitch in the column direction.

  FIG. 4 is a schematic plan view showing a second modification of the solid-state imaging device shown in FIG. A solid-state imaging device 20 shown in FIG. 4 includes a plurality of photoelectric conversion units 21 arranged two-dimensionally in a column direction in a p-type silicon substrate 28 and in a row direction orthogonal thereto. The arrangement of the plurality of photoelectric conversion units 21 is such that a plurality of photoelectric conversion unit columns composed of a plurality of photoelectric conversion units 21 arranged in the column direction are arranged in the row direction. Among the plurality of photoelectric conversion unit columns, the odd-numbered photoelectric conversion unit column and the even-numbered photoelectric conversion unit column are arranged in the column direction by ½ of the arrangement pitch in the column direction of each photoelectric conversion unit of the photoelectric conversion unit column. They are offset. Among the photoelectric conversion unit rows including the plurality of photoelectric conversion units 21 arranged in the row direction, the odd-numbered photoelectric conversion unit rows and the even-numbered photoelectric conversion unit rows are photoelectric conversions of the photoelectric conversion unit rows. The arrangement is shifted in the row direction by ½ of the array pitch in the row direction.

  The solid-state imaging device 20 accumulates in the vertical charge transfer path 23 that is a charge transfer unit that transfers charges generated in each photoelectric conversion unit 1 of the photoelectric conversion unit column in the column direction, and in each photoelectric conversion unit 21 of the photoelectric conversion unit column. OFD 24 for discharging the generated excess charge.

  Vertical charge transfer paths 23 and OFDs 24 are alternately arranged in the row direction between the photoelectric conversion unit columns arranged in the row direction. In this solid-state imaging device 20, two vertical photoelectric transfer unit rows adjacent to the vertical charge transfer channel 23 share the vertical charge transfer channel 23, and two photoelectric conversion unit columns adjacent to the OFD 24 share the OFD 24. .

  A readout gate 22 is formed between the vertical charge transfer path 23 and each photoelectric conversion unit 21 of the two photoelectric conversion unit rows adjacent to the vertical charge transfer path 23, and the two photoelectric conversion unit rows are connected via the read gate 22. Thus, charges can be read out to the vertical charge transfer path 23 between them.

  An OFG 25 is formed between the OFD 24 and each of the photoelectric conversion units 21 of the two photoelectric conversion unit columns adjacent to the OFD 24, and the OFD 24 between the two photoelectric conversion unit columns via the OFG 25. Excess charge can be discharged.

  The solid-state imaging device 20 further includes a horizontal charge transfer path 26 for transferring the charge transferred through the vertical charge transfer path 23 in the row direction, and a charge transferred through the horizontal charge transfer path 26 as a charge amount. And an output unit 27 that converts the signal into a signal corresponding to the output.

  Even with the solid-state imaging device having such a configuration, the effects described in the solid-state imaging device 10 can be obtained.

  As described above, the following items are disclosed in this specification.

  The disclosed solid-state imaging device is a solid-state imaging device in which a plurality of photoelectric conversion unit columns each including a plurality of photoelectric conversion units arranged in a column direction in a semiconductor substrate are arranged in a row direction orthogonal to the column direction. A charge transfer unit that transfers charges generated in each photoelectric conversion unit of the photoelectric conversion unit column in the column direction, and an overflow for discharging excess charge accumulated in each photoelectric conversion unit of the photoelectric conversion unit column A drain, and between the plurality of photoelectric conversion unit rows, any one of the charge transfer unit and the overflow drain is disposed, and the charge transfer unit and the overflow drain include the plurality of photoelectric conversion unit rows The two photoelectric conversion units arranged adjacent to each other in the row direction and sharing the charge transfer unit between the two photoelectric conversion unit columns adjacent to the charge transfer unit and adjacent to the overflow drain Share the said overflow drain in section column.

  According to this configuration, since the charge transfer unit is shared by two photoelectric conversion unit columns adjacent to the charge transfer unit, one charge transfer unit is provided for one photoelectric conversion unit column. Compared to the above, it is possible to secure a space corresponding to the reduced number of charge transfer portions. In this space, an overflow drain shared by two adjacent photoelectric conversion unit rows is formed, and a so-called horizontal OFD is realized. As a result, charges generated deep in the substrate can be accumulated in the photoelectric conversion unit, and sensitivity can be improved. Thus, according to the above configuration, the chip size and the number of pixels of the solid-state imaging device are the same as those in the conventional configuration in which one charge transfer unit is provided for one photoelectric conversion unit column, and the sensitivity is improved. Will be able to.

  The disclosed solid-state imaging device includes a distance d1 between two photoelectric conversion unit columns adjacent to each other with the overflow drain interposed therebetween, and a distance d2 between two photoelectric conversion unit columns adjacent to each other with the charge transfer unit interposed therebetween. Are the same.

  With this configuration, the sampling points can be equally spaced while realizing high sensitivity.

  The disclosed solid-state imaging device is provided between the overflow drain and the photoelectric conversion unit row adjacent thereto, and an overflow gate for forming a potential barrier between the overflow drain and the photoelectric conversion unit, A control electrode for controlling the potential of the overflow gate provided above the overflow gate of the semiconductor substrate, and provided above each of the two adjacent overflow gates across the overflow drain The control electrode is a single electrode formed from one upper side of the two overflow gates to the upper side of the other two overflow gates across the overflow drain.

  With this configuration, the potential of the overflow gate can be controlled, and an electronic shutter function, control of the saturation capacity of the photoelectric conversion unit, and the like can be realized. Further, since the control electrode is shared by two overflow gates adjacent to each other with the overflow drain interposed therebetween, a conventional configuration in which one overflow drain, overflow gate, and control electrode are provided for one photoelectric conversion unit row As compared with, the number of control electrodes can be greatly reduced. As a result, even if the width of the overflow drain and the overflow gate is the same as the conventional configuration, the width of the control electrode in the row direction is wider in the above configuration, so that the electrical resistance of the control electrode is reduced and the pulse delay is reduced As a result, the discharge rate of excess charges from the photoelectric conversion unit can be increased. In addition, since the width of the control electrode in the row direction is increased, the control electrode can be easily formed even if the chip size is currently miniaturized. In particular, when d1 = d2, the width of the control electrode can be made sufficiently large, so that its manufacture is easy.

  In the disclosed solid-state imaging device, among the plurality of photoelectric conversion unit columns, odd-numbered photoelectric conversion unit columns and even-numbered photoelectric conversion unit columns are arranged in the column direction of each photoelectric conversion unit of the photoelectric conversion unit column. Are arranged so as to be shifted in the column direction by ½ of the arrangement pitch.

  With this configuration, since the opening of the photoelectric conversion unit can be increased, it is possible to increase the sensitivity in combination with the improvement in sensitivity by providing the overflow drain adjacent to the photoelectric conversion unit.

  The disclosed imaging device includes the solid-state imaging device.

  With this configuration, a small and highly sensitive imaging device can be realized.

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion part 3 Vertical charge transfer path 4 Overflow drain 10 Solid-state image sensor 11 p-type silicon substrate

Claims (5)

A plurality of photoelectric conversion unit columns formed of a plurality of photoelectric conversion units disposed in a column direction in a semiconductor substrate are solid-state imaging devices arranged in a row direction orthogonal to the column direction,
A charge transfer unit that transfers charges generated in each photoelectric conversion unit of the photoelectric conversion unit column in the column direction;
An overflow drain for discharging excess charge accumulated in each photoelectric conversion unit of the photoelectric conversion unit row,
Between the plurality of photoelectric conversion unit rows, either the charge transfer unit or the overflow drain is disposed,
The charge transfer unit and the overflow drain are alternately arranged in the row direction between the plurality of photoelectric conversion unit columns,
Sharing the charge transfer unit between two photoelectric conversion unit rows adjacent to the charge transfer unit;
A solid-state image pickup device in which the two drains adjacent to the overflow drain share the overflow drain. The solid-state imaging device according to claim 1,
Solid-state imaging in which the distance d1 between the two photoelectric conversion unit columns adjacent to each other with the overflow drain interposed therebetween is the same as the distance d2 between the two photoelectric conversion unit columns adjacent to each other with the charge transfer unit interposed therebetween element. The solid-state imaging device according to claim 1 or 2,
An overflow gate provided between the overflow drain and the photoelectric conversion unit row adjacent to the overflow drain to form a potential barrier between the overflow drain and the photoelectric conversion unit;
Provided above the overflow gate of the semiconductor substrate, and a control electrode for controlling the potential of the overflow gate;
The control electrode provided above each of the two overflow gates adjacent to each other across the overflow drain extends from one of the two overflow gates across the overflow drain. The solid-state image sensor which becomes one electrode formed up to the other. The solid-state image sensor according to any one of claims 1 to 3,
Of the plurality of photoelectric conversion unit columns, odd-numbered photoelectric conversion unit columns and even-numbered photoelectric conversion unit columns are only ½ of the arrangement pitch in the column direction of the photoelectric conversion units of the photoelectric conversion unit column. A solid-state imaging device arranged so as to be shifted in the column direction.   An imaging device provided with the solid-state image sensor of any one of Claims 1-4.

Images