WO2014203456A1 - Solid-state imaging device and method for driving same - Google Patents

Abstract

This invention provides a solid-state imaging device in which exposure durations for two groups of photoelectric conversion units can be controlled independently. Said solid-state imaging device is provided with the following: an imaging unit that has groups of photoelectric conversion units laid out in an offset subsampling pattern; light-receiving sections; a plurality of transfer channels that extend vertically; first through fourth transfer electrodes laid out in a repeating fashion along the transfer channels; and a plurality of vertical shift registers that vertically transfer signal charge outputted from the photoelectric conversion units. The first through fourth transfer electrodes are laid out in an arbitrary order so as to repeat three times in an interval equal to twice the spacing with which the photoelectric conversion units and the light-receiving sections are arranged, and the arrangement order of the first through fourth transfer electrodes is offset by two electrodes between two vertical shift registers.

Description

Solid-state imaging device and driving method thereof

The present disclosure relates to a solid-state imaging device and a driving method thereof.

Generates and accumulates signal charges (photoelectrons) by detecting electromagnetic waves input from outside, such as visible light and radiation, using an image pickup unit in which multiple photodiodes, which are photoelectric conversion elements, are arranged in a line or matrix form However, solid-state imaging devices that output image information are used in various fields.

Here, in the case of a solid-state imaging device for the purpose of obtaining a visible light color image, a pixel is configured by arranging on the photodiode a color filter that transmits only a specific visible light wavelength component. It is the current mainstream to restore a necessary color component by a set of pixels.

Specifically, for example, a color filter that transmits three primary colors of red (R), green (G), and blue (B) as a set of pixels is arranged on a photodiode, and the three primary colors are different from each other. Each pixel is individually detected, and wavelength data is complemented by neighboring pixels by signal processing to generate a color image.

On the other hand, in recent years, a mechanism for realizing a new application that cannot be realized when only a visible light component is detected by detecting a wavelength component outside the visible light region has been considered.

As an example, for infrared light irradiated from a light source that performs blinking operation or emission intensity modulation, the amount of light that is reflected by the object in the irradiation space and reaches the solid-state imaging device is measured, and from the result, the solid-state imaging device is measured. A system that realizes distance image sensing of the so-called Time-of-Flight method that calculates the distance to the distance is proposed (for example, see Patent Document 1). In a solid-state imaging device suitable for this application, only the infrared light component is transmitted so that the infrared light signal to be detected is not buried in the signal generated by the light (environment light) emitted from the surroundings of the object. A pixel having a configuration in which a filter is arranged on a photodiode is used.

Japanese Patent No. 3758618 JP-A-9-172156

In order to simultaneously capture a visible light color image and sense a distance image with a single solid-state imaging device, a photoelectric conversion unit (visible light conversion unit) with a visible light filter and an infrared light filter are installed. It is necessary to dispose the photoelectric conversion unit (infrared light conversion unit) in the same imaging plane. In order to sample image information with high resolution equally in both the horizontal direction and the vertical direction for both image signals output from the two photoelectric conversion unit groups arranged in the same imaging plane. It is desirable that the two photoelectric conversion unit groups are arranged in an offset sub-sampling manner, and they are arranged in combination by shifting one phase in both the horizontal direction and the vertical direction.

Here, in order to obtain a good image quality in imaging using the visible light conversion unit, it is necessary to control the exposure time according to the brightness around the subject. On the other hand, the infrared light conversion unit is required to control the exposure time in synchronization with the light emission operation of the infrared light source regardless of the brightness around the subject. Therefore, the timing for applying the readout drive pulse to the signal readout gate electrode installed in the photodiode of each of the visible light conversion unit and the infrared light conversion unit is determined independently for each of the visible light conversion unit and the infrared light conversion unit. Must be controlled.

However, in the conventional general CCD (Charge Coupled Device) type image sensor as shown in Patent Document 2, since the gate electrode film is connected by the pixels in the horizontal direction, the visible light conversion unit / infrared light conversion unit The application timing of each read drive pulse cannot be controlled independently.

Here, if the gate electrode for signal readout is divided and arranged in a floating island shape, and the gate electrode is connected by a metal wiring formed above the gate electrode film, it can be visualized by designing the wiring layer layout. It is possible to independently control the application timing of the read drive pulse in each of the light conversion unit and the infrared light conversion unit.

However, in this case, the area occupied by the wiring layer with respect to the area of the photoelectric conversion unit is increased as compared with the conventional case, so that the aperture ratio of the photoelectric conversion unit is reduced and the sensitivity to detect visible light / infrared light is increased. It will decline. In addition, it is conceivable to reduce the wiring width in order to avoid an increase in the wiring layer area. However, in this case, the manufacturing cost increases, and the propagation delay of the read drive pulse between the center and the outer edge of the imaging unit is increased. It becomes more conspicuous and good image information cannot be obtained.

In recent years, CMOS (Complementary Metal-Oxide Semiconductor) type image sensors have been developed for backside illumination structures, optical waveguide structures, etc., and even if the number of wires increases slightly, sensitivity reduction and propagation delay of read drive pulses are not a problem. . However, the CMOS image sensor has a fatal problem for distance image sensing that it is difficult to unify the exposure time in all the photoelectric conversion units.

In view of the above-described problems, the present disclosure includes an imaging unit in which two photoelectric conversion unit groups arranged in an offset sub-sampling manner are combined by shifting one phase in both the horizontal direction and the vertical direction. Solid-state imaging that can independently control the timing of applying a read drive pulse to the signal readout gate electrode of each group, and that can simultaneously control the photoelectric conversion units in one photoelectric conversion unit group An object is to provide an apparatus.

In order to achieve the above-described object, a solid-state imaging device according to an embodiment of the present disclosure includes a photoelectric conversion unit that is arranged in an offset sub-sampling manner in the horizontal direction and the vertical direction, and converts incident light into signal charges by photoelectric conversion. Each of the photoelectric conversion units included in the first photoelectric conversion unit group and the photoelectric conversion unit included in the first photoelectric conversion unit group has a first photoelectric conversion unit group and a second photoelectric conversion unit group. However, the surface of the semiconductor substrate on which the imaging unit arranged so as to form a square lattice as a whole is combined by shifting the phase by one in both the horizontal direction and the vertical direction, and the photoelectric conversion unit A light receiving portion from which a light shielding film is excluded so that light is irradiated to the light receiving portion, a plurality of transfer channels arranged between the light receiving portions and extending in the vertical direction, and a front surface in the same plane on the transfer channel. The first transfer electrode, the second transfer electrode, the third transfer electrode, and the fourth transfer electrode, which are repeatedly arranged in the vertical direction, the transfer channel, and the first to fourth transfer electrodes, A high voltage pulse is applied to any one of the fourth transfer electrodes once or continuously several times, and is output from the photoelectric conversion unit moved from the photoelectric conversion unit group to the transfer channel. A plurality of vertical shift registers that transfer signal charges in the vertical direction of the imaging unit and a horizontal line that is connected to the last stage of the vertical shift registers and transfers signal charges transferred from the vertical shift registers in the horizontal direction. A shift register; and a charge detection unit that is connected to the last stage of the horizontal shift register and converts a signal charge transferred from the horizontal shift register into a voltage signal. The first to fourth transfer electrodes are repeatedly arranged three times in an arbitrary order within a section equal to a distance twice as long as the interval in which the light receiving portions are arranged in the square lattice shape, In any two vertical shift registers arranged adjacent to each other, the arrangement order of the first to fourth transfer electrodes is an offset of two electrodes.

According to this aspect, in the imaging unit in which two photoelectric conversion unit groups arranged in an offset sub-sampling manner are combined by shifting the phase by one in both the horizontal direction and the vertical direction, each photodiode in one photoelectric conversion unit group When the transfer electrode located at the closest distance from the center of (PD) and having the largest area in contact with the PD is set as a signal read gate electrode and a read drive pulse is applied, each of the PDs in the other photoelectric conversion unit group A read drive pulse is applied to a transfer electrode that is located at a distance from the center and has a small area in contact with the PD. Therefore, only the signal charge of one photoelectric conversion unit group is read out to the transfer channel, and the signal charge of the other photoelectric conversion unit group can be held in the PD. Therefore, in each of the two photoelectric conversion unit groups, the read drive pulse can be applied at an appropriate timing, and the exposure time can be set to an optimum time.

It is the top view which showed typically the principal part of the solid-state imaging device which concerns on 1st Embodiment. It is a principal part top view of the solid-state imaging device concerning a 1st embodiment. It is a principal part top view of the solid-state imaging device concerning a 1st embodiment. FIG. 4 is a cross-sectional view taken along line A-A ′ of FIG. 3. FIG. 4 is a sectional view taken along line B-B ′ of FIG. 3. FIG. 4 is a sectional view taken along line C-C ′ of FIG. 3. 3 is a timing chart illustrating an operation example of the solid-state imaging device of FIG. 1. 8 is a timing chart showing an example of a timing chart in the charge readout period of FIG. FIG. 8 is a timing chart showing another example of the timing chart in the charge reading period of FIG. 7. FIG. 8 is a timing chart showing an example of a timing chart in the horizontal scanning period of FIG. 7. It is a principal part top view of the solid-state imaging device which concerns on 2nd Embodiment. It is a principal part top view of the solid-state imaging device which concerns on 2nd Embodiment. FIG. 13 is a cross-sectional view taken along line A-A ′ of FIG. 12. FIG. 13 is a sectional view taken along line B-B ′ of FIG. 12. FIG. 13 is a cross-sectional view taken along line C-C ′ of FIG. 12. It is a principal part top view of the solid-state imaging device which concerns on 3rd Embodiment. It is a principal part top view of the solid-state imaging device which concerns on 3rd Embodiment. FIG. 18 is a cross-sectional view taken along line A-A ′ of FIG. 17. FIG. 18 is a cross-sectional view taken along line B-B ′ of FIG. 17. It is a principal part top view of the solid-state imaging device concerning 4th Embodiment. It is a principal part top view of the solid-state imaging device concerning 4th Embodiment. FIG. 22 is a cross-sectional view taken along line A-A ′ of FIG. 21. FIG. 22 is a cross-sectional view taken along line B-B ′ of FIG. 21.

Hereinafter, each embodiment will be described with reference to the drawings. In addition, although this indication is demonstrated using the following embodiment and drawing, this is for the purpose of illustration and this indication is not intended to be limited to these. That is, the numbers, constituent elements, the arrangement positions of the constituent elements, the material of the constituent elements, the connection form of the constituent elements, the timing, the order of the timings, and the like shown in the following embodiments are merely examples, Absent.

This disclosure is limited only by the claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are not necessarily required to achieve the problems of the present disclosure, but are more preferable. It will be described as constituting a form. In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals.

(First embodiment)
FIG. 1 is a configuration diagram illustrating an example of a main part of the solid-state imaging device according to the first embodiment.

This solid-state imaging device is arranged in a matrix on a semiconductor substrate, and is provided corresponding to a plurality of photoelectric conversion units 100 (100a, 100b) that convert incident light into signal charges, and columns of photoelectric conversion units 100. A vertical shift register 101 that transfers signal charges read from the conversion unit 100 in the column direction (vertical direction), and a horizontal shift register 102 that transfers signal charges transferred by the vertical shift register 101 in the row direction (horizontal direction). And a charge detection unit 103 that converts the signal charge transferred by the horizontal shift register 102 into a voltage signal and outputs the voltage signal.

The photoelectric conversion unit 100 includes photoelectric conversion units 100a and 100b. The photoelectric conversion units 100a and 100b are arranged in an offset sub-sampling manner, and the first photoelectric conversion unit group 104a is formed by a plurality of photoelectric conversion units 100a. The second photoelectric conversion unit group 104b is formed by the plurality of photoelectric conversion units 100b. The imaging unit includes photoelectric conversion unit groups 104a and 104b.

The photoelectric conversion units 100a and 100b included in the photoelectric conversion unit groups 104a and 104b are arranged on the semiconductor substrate by being combined with each other while shifting the phase by one in both the horizontal and vertical directions.

The output terminal of the substrate bias circuit 105 that converts the externally applied voltage DCIN into a desired voltage value is connected to the substrate of the solid-state imaging device via the diode 106, and the potential of the photoelectric conversion unit 100 is held at a value suitable for exposure. Has been.

ΦSUB is input to the substrate of the solid-state imaging device via the coupling capacitor 107. When a high voltage pulse of 20 V, for example, is applied to φSUB, the substrate voltage of the solid-state imaging device rises, the signal charges of the photoelectric conversion unit 100 are all reset and discharged to the substrate, and the high voltage pulse of φSUB falls. This time becomes the exposure start time of the solid-state imaging device.

The vertical shift register 101 is configured by repeatedly arranging transfer electrodes V1 to V4 in a predetermined order. In each of the vertical shift registers 101, the transfer electrodes V1 to V4 are arranged so that their order has an offset of two electrodes.

Corresponding drive pulses φV1, φV2, φV3, and φV4 are supplied to the transfer electrodes V1 to V4 of the vertical shift register 101, respectively. The signal charge generated in the photoelectric conversion unit 100a by exposure moves to the transfer channel 2 of the vertical shift register 101 when a high voltage (H) is applied to φV1. At this time, medium voltage (M) is applied to φV2 and φV4, and low voltage (L) is applied to φV3, and signal charges are held in the transfer channel under the transfer gate to which φV1, φV2, and φV4 are applied. . Reference numeral 110 in FIG. 1 illustrates this state. Although not shown, the signal charge generated in the photoelectric conversion unit 100b moves to the transfer channel of the vertical shift register 101 when a high voltage (H) is applied to φV3. At this time, a medium voltage (M) is applied to φV2 and φV4, and a low voltage (L) is applied to φV1, and signal charges are held in transfer channel 2 below the transfer gate to which φV2, φV3, and φV4 are applied. .

The signal charge that has moved to the vertical shift register 101 moves in the transfer channel 2 by switching the voltages of φV1, φV2, φV3, and φV4 to a medium voltage (M) and a low voltage (L) in a predetermined order. The shift register 102 is reached. The signal charge that has reached the horizontal shift register 102 moves to the end of the horizontal shift register 102 by switching the voltages of φH1, φH2, and φHL between a high voltage (H) and a medium voltage (H) in a predetermined order.

The terminal of the horizontal shift register 102 is connected to the power supply voltage VDD when a high voltage (H) is applied from φR, and is determined to be a constant potential. However, when φR is switched to a low voltage, the terminal shifts to a floating state. Become. When the signal charge reaches this state, a signal voltage corresponding to the amount of charge is output from the Vout terminal to the outside of the solid-state imaging device via the charge detection unit 103. The charge detection unit 103 includes, for example, a buffer amplifier that lowers the output impedance and sends out a signal.

2 and 3 are plan views of the main part of the solid-state imaging device according to the first embodiment. In the present embodiment, a solid-state imaging device that employs four-phase driving in the vertical shift register 101 will be described.

The light receiving unit 1 (1a, 1b) is disposed on the semiconductor substrate. The light receiving unit 1 includes light receiving units 1a and 1b, and photoelectric conversion units 100a and 100b including photodiodes are formed on a semiconductor substrate below the light receiving units 1a and 1b. As a result, signal charges corresponding to the amount of incident light are generated and accumulated for a certain period. The light receiving unit 1a corresponds to the photoelectric conversion unit 100a, and the light receiving unit 1b corresponds to the photoelectric conversion unit 100b.

A transfer channel 2 extending in the vertical direction is arranged between the two light receiving portions 1a and 1b arranged in the horizontal direction. The transfer channel 2 generates a potential distribution that transfers signal charges in the vertical direction.

On the transfer channel 2 extending in the vertical direction, transfer electrodes 3 to which transfer pulses φV1, φV2, φV3, and φV4 having different phases are arranged. In this embodiment, the transfer electrode 3 refers to a conductive film such as polysilicon formed on the transfer channel 2 via an oxide film. What is formed at a position off the transfer channel 2 is regarded as a wiring even if it is integrally formed of the same material as the transfer electrode 3. The transfer electrode 3 includes a first transfer electrode 3-1 to which a transfer pulse φV1 is supplied, a second transfer electrode 3-2 to which a transfer pulse φV2 is supplied, and a third transfer electrode 3- to which a transfer pulse φV3 is supplied. 3 and a fourth transfer electrode 3-4 to which a transfer pulse φV4 is supplied. Note that when there is no need to distinguish between them, they are simply referred to as transfer electrodes 3. The transfer pulses φV1, φV2, φV3, φV4 are, for example, −6V to 0V.

Further, the first transfer electrode 3-1 to the fourth transfer electrode 3-4 correspond to the transfer electrodes V1 to V4 in FIG. 1, respectively.

In the present embodiment, the second transfer electrode 3-2 and the fourth transfer electrode 3-4 are formed on the same plane, and the insulating film 21 is formed on the surfaces of the second transfer electrode 3-2 and the fourth transfer electrode 3-4. Thereafter, a two-layer transfer electrode structure in which the first transfer electrode 3-1 and the third transfer electrode 3-3 are formed on the insulating film 21 is employed.

The first transfer electrode 3-1, the second transfer electrode 3-2, the third transfer electrode 3-3, and the fourth transfer electrode 3-4 are arranged in such a manner that the first transfer electrode 3-1, the second transfer electrode 3-4 A transfer electrode 3-2, a third transfer electrode 3-3, and a fourth transfer electrode 3-4, which are arranged in this order, are arranged repeatedly in the vertical direction with a basic configuration. Here, “upward” described in this paper indicates a direction reversed 180 ° from a direction toward the horizontal shift register 102 on the surface of the semiconductor substrate, and “downward” indicates a direction toward the horizontal shift register 102. The transfer electrode 3 and the transfer channel 2 constitute a vertical shift register 101 arranged in common for each column of the light receiving units 1 arranged in the vertical direction. Twelve transfer electrodes 3 are arranged so as to correspond to one set of light receiving unit 1a and light receiving unit 1b.

Between the light receiving portions 1a and 1b arranged in the vertical direction, an inter-light receiving portion wiring 4 is formed. The transfer electrode 3 is connected by the inter-light receiving portion wiring 4 made of polysilicon formed integrally with the transfer electrode 3 in two vertical shift registers 101 adjacent in the horizontal direction.

Specifically, the first transfer electrode 3-1 is connected by the light receiving portion wiring 4-1. The second transfer electrode 3-2 is connected by a light receiving portion wiring 4-2. The third transfer electrode 3-3 is connected by a light receiving portion wiring 4-3. The fourth transfer electrode 3-4 is connected by a light receiving portion wiring 4-4. In addition, when it is not necessary to distinguish in particular, it will be simply referred to as the light receiving portion wiring 4.

The light receiving unit wirings 4-1 and 4-2 are formed in a region between the light receiving units in which the light receiving unit 1a is disposed above and the light receiving unit 1b is disposed below. The light receiving unit wirings 4-3 and 4-4 are formed in the region between the light receiving units in which the light receiving unit 1b is disposed above and the light receiving unit 1a is disposed below.

The light receiving portion wiring 4-1 is formed in an upper layer of the insulating film 21 formed on the surface of the light receiving portion wiring 4-2. The light receiving portion wiring 4-3 is formed in an upper layer of the insulating film 21 formed on the surface of the light receiving portion wiring 4-4.

Hereinafter, the arrangement of the transfer electrode 3 and the light receiving portion wiring 4 will be described.

In FIG. 2, the inter-light-receiving-unit wiring 4-1 disposed between the 2N + 1th (N is an integer equal to or greater than 0) vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 is the 2N + 1th vertical Two first transfer electrodes 3-1 included in the shift register 101 are connected to one first transfer electrode 3-1 included in the 2 (N + 1) th vertical shift register 101. Of the two first transfer electrodes 3-1 connected in the 2N + 1-th vertical shift register 101, the one located above has a distance from the center of the light receiving unit 1 a among the transfer electrodes 3 in the vicinity of the light receiving unit 1 a. the nearest. Hereinafter, the transfer electrode 3 having the shortest distance from the center of the light receiving unit 1 among the transfer electrodes 3 in the vicinity of the light receiving unit 1 in any light receiving unit 1 will be referred to as “the closest electrode of the light receiving unit 1”. .

The inter-light-receiving portion wiring 4-2 arranged between the 2N + 1th vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 includes two second transfer electrodes included in the 2N + 1th vertical shift register 101. 3-2 is connected to one second transfer electrode 3-2 included in the 2 (N + 1) th vertical shift register 101. Of the two second transfer electrodes 3-2 connected in the 2N + 1-th vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1 a below.

The inter-light-receiving portion wiring 4-3 disposed between the 2N + 1th vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 includes two third transfer electrodes included in the 2N + 1th vertical shift register 101. 3-3 is connected to two third transfer electrodes 3-3 included in the 2 (N + 1) th vertical shift register 101. Of the two third transfer electrodes 3-3 connected in the 2N + 1-th vertical shift register 101, the one positioned above is the closest electrode of the light receiving unit 1b. Of the two third transfer electrodes 3-3 connected in the 2 (N + 1) th vertical shift register 101, the one positioned below is the closest electrode of the light receiving unit 1b.

The inter-light-receiving-unit wiring 4-4 disposed between the 2N + 1th vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 includes two fourth transfer electrodes included in the 2N + 1th vertical shift register 101. 3-4 is connected to two fourth transfer electrodes 3-4 included in the 2 (N + 1) th vertical shift register 101. Among these, the upper one of the two fourth transfer electrodes 3-4 connected in the 2N + 1-th vertical shift register 101 is adjacent to the nearest electrode of the light receiving unit 1b below. Of the two fourth transfer electrodes 3-4 connected in the 2 (N + 1) th vertical shift register 101, the one positioned below is adjacent to the nearest electrode of the light receiving unit 1b below. .

The inter-light-receiving-unit wiring 4-1 arranged between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 includes two second light receiving lines included in the 2 (N + 1) th vertical shift register 101. One transfer electrode 3-1 and two first transfer electrodes 3-1 included in the 2N + 3rd vertical shift register 101 are connected. Of the two first transfer electrodes 3-1 connected in the 2 (N + 1) th vertical shift register 101, the one located above is the closest electrode of the light receiving unit 1 a.

The inter-light-receiving-unit wiring 4-2 arranged between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 includes two second second lines included in the 2 (N + 1) th vertical shift register 101. The transfer electrode 3-2 is connected to two second transfer electrodes 3-2 included in the 2N + 3rd vertical shift register 101. Of the two second transfer electrodes 3-2 connected in the 2 (N + 1) -th vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1a below.

An inter-light-receiving portion wiring 4-3 disposed between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 is provided by two 2nd (N + 1) th vertical shift registers 101. The third transfer electrode 3-3 is connected to one third transfer electrode 3-3 included in the 2N + 3rd vertical shift register 101. Of the two third transfer electrodes 3-3 connected in the 2 (N + 1) th vertical shift register 101, the one located above is the closest electrode of the light receiving unit 1b.

The inter-light-receiving-unit wiring 4-4 disposed between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 has two second shift bits included in the 2 (N + 1) th vertical shift register 101. The four transfer electrodes 3-4 are connected to one fourth transfer electrode 3-4 included in the 2N + 3rd vertical shift register 101. Of the two fourth transfer electrodes 3-4 connected in the 2 (N + 1) th vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1b below.

Further, as shown in FIG. 3, a shunt wiring 5 (transfer electrode driving second wiring) is disposed on the transfer electrode 3 via an insulating film. The shunt wiring 5 is wired in a direction parallel to the vertical direction of the vertical shift register 101, and projects in the horizontal direction in the gap of the light receiving unit 1, and the direction in which every other pixel projects is 180 ° different.

The shunt wiring 5 is connected to the light receiving section wiring 4 at the contact section 6. Specifically, the shunt wiring 5 includes a first shunt wiring 5-1 supplied with the transfer pulse φV1, a second shunt wiring 5-2 supplied with the transfer pulse φV2, and a third shunt supplied with the transfer pulse φV3. The wiring 5-3 and the fourth shunt wiring 5-4 to which the transfer pulse φV4 is supplied. In addition, when it is not necessary to distinguish in particular, it will be simply referred to as shunt wiring 5. The contact portion 6 includes a contact portion 6-1 connected to the first shunt wiring 5-1, a contact portion 6-2 connected to the second shunt wiring 5-2, and a contact connected to the third shunt wiring 5-3. And a contact portion 6-4 connected to the fourth shunt wiring 5-4. In addition, when it is not necessary to distinguish in particular, it will only be described as the contact portion 6.

The shunt wiring 5 is formed of a metal material such as polysilicon or tungsten. When a metal material is used as the shunt wiring 5, an equivalent resistance value can be obtained even if the film thickness and the wiring width are reduced as compared with the case where polysilicon is used. There is an advantage that can be relaxed.

4 is a cross-sectional view taken along line AA ′ of FIG. 3, FIG. 5 is a cross-sectional view taken along line BB ′ of FIG. 3, and FIG. 6 is a cross-sectional view taken along line CC ′ of FIG. . 4 to 6 are cross-sectional views of the light receiving unit 1a shown in FIG. 3, but for the cross-sectional view of the light receiving unit 1b shown in FIG. 3, the symbols in FIGS. 4 to 6 correspond to the light receiving unit 1b. What is necessary is just to replace with the part to do.

In the present embodiment, a semiconductor substrate 10 made of, for example, n-type silicon is used. A p-type well 11 is formed in the semiconductor substrate 10. An n-type region 12 is formed in the p-type well 11, and a p-type region 13 is formed on the surface side of the n-type region 12. The light receiving portion 1 is constituted by a photodiode having a pn junction between the n-type region 12 and the p-type well 11. Since the p-type region 13 is formed on the surface side of the n-type region 12, an embedded photodiode with reduced dark current is configured.

A p-type well 14 is formed adjacent to the n-type region 12, and a transfer channel 2 composed of the n-type region is formed in the p-type well 14. Adjacent to the transfer channel 2, a p-type channel stop portion 16 is formed for preventing signal charges from flowing in and out between the adjacent light receiving portions 1. In the example shown in the figure, the readout channel 17 is between the light receiving unit 1 and the transfer channel 2 on the left side of the light receiving unit 1.

On the semiconductor substrate 10 on which various semiconductor regions are formed, the transfer electrode 3 made of polysilicon is formed via the gate insulating film 20. If the readout channel 17 has the potential distribution controlled by the voltage of the first transfer electrode 3-1, the readout channel 17 a has the signal charge of the light receiving unit 1 a when the potential distribution of the readout channel 17 a is controlled. Read to left transfer channel 2. Although the read channel 17a is not shown, the reference numeral 17 in FIG. 4 may be read as the read channel 17a.

On the other hand, if the readout channel 17b has the potential distribution controlled by the voltage of the third transfer electrode 3-3 among the readout channels 17, the signal charge of the light receiving portion 1b is obtained when the potential distribution of the readout channel 17b is controlled. To the left transfer channel 2. That is, the readout channel 17b corresponds to the reference numeral 17 in FIG. 4 when the light receiving portion 1b in FIG. 3 is cut in the A-A ′ direction.

An insulating film 21 made of, for example, silicon oxide is formed so as to cover the second transfer electrode 3-2, the fourth transfer electrode 3-4, and the light receiving portion wirings 4-2 and 4-4. Inter-light-receiving portion wirings 4-1 and 4-3 are formed on the inter-light-receiving portion wirings 4-2 and 4-4 with an insulating film 21 interposed therebetween. A light shielding film 7 is formed on the insulating films 21 and 22. A shunt wiring 5 is formed on the light shielding film 7 via a planarizing film 23.

The insulating film 21 and the light shielding film 7 thereabove have openings formed in part of the contact portions 6-2 and 6-4, and the shunt wiring 5 and the transfer electrode 3 are connected inside the openings. . The insulating film 22 and the light shielding film 7 thereabove have openings in the contact portions 6-1 and 6-3, and the shunt wiring 5 and the transfer electrode 3 are connected inside the openings. When a metal material such as tungsten is used as the shunt wiring 5, a barrier metal may be interposed without directly connecting the metal material constituting the shunt wiring 5 and the transfer electrode 3 in the contact portion 6. .

Although not shown, a planarizing film, a color filter, and an on-chip lens may be formed on the light shielding film 7 as necessary.

Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

FIG. 7 is a timing chart showing an operation example of the solid-state imaging device according to the present embodiment, and FIG. 8 is an example of a timing chart in the charge readout period shown in FIG. 9 is an example of a timing chart in the charge reading period shown in FIG. 7, and FIG. 10 is an example of a timing chart in the horizontal scanning period shown in FIG.

When light enters the light receiving unit 1, the photoelectric conversion unit 100 generates a signal charge (electrons in this example) corresponding to the amount of incident light by photoelectric conversion and accumulates the signal charge in the n-type region 12 of the photoelectric conversion unit 100 for a certain period. The

First, a case where the signal charge generated by photoelectric conversion by the photoelectric conversion unit 100a is read will be described.

For example, in FIG. 7 to FIG. 9, when φV1 becomes H and a read pulse is supplied to the first transfer electrode 3-1, the potential distribution of the read channel 17a of the photoelectric conversion unit 100a is controlled, and the photoelectric conversion unit 100a All the signal charges stored in are transferred to the transfer channel 2. The voltage of the read pulse is 13V, for example. At this time, φV3 in FIGS. 7 to 9 is L, and −6V is applied to the third transfer electrode 3-3. 7 to 9, both φV2 and φV4 are M, and 0 V is applied to the second transfer electrode 3-2 and the fourth transfer electrode 3-4.

In FIG. 7 to FIG. 9, when φV1 transitions from H to M, the readout pulse application period ends, and when the voltage applied to the first transfer electrode 3-1 is switched to 0V, it accumulates in the photoelectric conversion unit 100a. The signal charges that have been stored are accumulated in the transfer channel 2 below the fourth transfer electrode 3-4, the first transfer electrode 3-1, and the second transfer electrode 3-2 adjacent to the photoelectric conversion unit 100a. (See reference numeral 110 in FIG. 1).

After the signal charge of the photoelectric conversion unit 100a is read out to the transfer channel 2, four-phase transfer pulses φV1 to φV4 are supplied to the transfer electrode 3, the potential distribution of the transfer channel 2 is controlled, and the signal charge is Forwarded to In this transfer, the signal charge moves downward by two electrodes from the read position, and is transferred below the second transfer electrode 3-2, the third transfer electrode 3-3, and the fourth transfer electrode 3-4. This is performed until the channel 2 is accumulated.

Next, a case where signal charges generated by photoelectric conversion by the photoelectric conversion unit 100b are read will be described.

7 to 9, when φV3 becomes H and a read pulse is supplied to the third transfer electrode 3-3, the potential distribution of the read channel 17b of the photoelectric conversion unit 100b is controlled and accumulated in the photoelectric conversion unit 100b. All the signal charges are read out to the transfer channel 2. At this time, φV1 in FIGS. 7 to 9 is L, and −6V is applied to the first transfer electrode 3-1. In FIGS. 7 to 9, φV2 and φV4 are M, and 0V is applied to the second transfer electrode 3-2 and the fourth transfer electrode 3-4. At this time, the signal charges of the photoelectric conversion unit 100a previously read to the transfer channel 2 are the second transfer electrode 3-2 and the third transfer electrode 3 which are positioned one stage above the read channel 17b of the photoelectric conversion unit 100b. −3, since it is accumulated in the transfer channel 2 below the fourth transfer electrode 3-4, it is separated from the read channel 17b, so that it mixes with the signal charge of the photoelectric conversion unit 100b even when a read pulse is applied. There is no.

In FIG. 7 to FIG. 9, when φV3 transitions from H to M, the readout pulse application period ends, and when the voltage applied to the third transfer electrode 3-3 is switched to 0 V, the voltage is accumulated in the photoelectric conversion unit 100b. The signal charge thus stored is accumulated in the transfer channel 2 below the second transfer electrode 3-2, the third transfer electrode 3-3, and the fourth transfer electrode 3-4 adjacent to the photoelectric conversion unit 100b.

Here, the exposure time is the time when the application of the readout pulse is completed, or a high voltage (for example, 25 V) is applied to the n-type well in the deep part of the semiconductor substrate 10 to deplete all the photoelectric conversion units 100 at the same time. This is equivalent to the time when the time when the applied voltage to the n-type well is switched to a low voltage (for example, 6V) after that is the start time and the time when the signal charge is read out to the transfer channel 2 is the end time.

Accordingly, in the present embodiment, since the signal charges accumulated in the photoelectric conversion unit 100a and the photoelectric conversion unit 100b can be read out to the transfer channel 2 at different times, exposure relating to the photoelectric conversion unit 100a and the photoelectric conversion unit 100b is performed. It is possible to set different times.

In this embodiment, as shown in FIGS. 8 and 9, the signal charge of the photoelectric conversion unit 100a is read first, and the signal charge of the photoelectric conversion unit 100b is read later, but this order may be reversed. Further, the signal charge of either one of the photoelectric conversion units 100a and 100b may be read twice. The two exposure times may be different.

Here, when the signal charges of the photoelectric conversion units 100a and 100b are each read once, or the signal charges of either one of the photoelectric conversion units 100a and 100b are read twice, the vertical shift register 101 stores the signal charges. In this case, an area (see reference numeral 120 in FIG. 2) in which one of the photoelectric conversion units 100a and 100b can be read one more time and accumulated in the transfer channel 2 is left.

When reading and accumulating signal charges in this region, first, four-phase transfer pulses φV1 to φV4 are supplied to the transfer electrode 3 to control the potential distribution of the transfer channel 2 and transfer the signal charges in the vertical direction. For example, when reading the signal charge of the photoelectric conversion unit 100a (see FIG. 8), the fourth transfer electrode 3-4, the first transfer electrode 3-1 and the second transfer electrode 3-2 adjacent to the photoelectric conversion unit 100a The signal charge is transferred in the vertical direction until a region where no charge is accumulated moves to the lower transfer channel 2. Then, a read pulse is applied to the first transfer electrode 3-1, and the signal charge of the photoelectric conversion unit 100a is read. The readout pulse can be set at an arbitrary time, and therefore the exposure time can be different from the previous one.

On the other hand, when reading the signal charge of the photoelectric conversion unit 100b (see FIG. 9), the second transfer electrode 3-2, the third transfer electrode 3-3, and the fourth transfer electrode 3-4 adjacent to the photoelectric conversion unit 100b. The signal charge is transferred in the vertical direction until a region where no charge is accumulated moves to the lower transfer channel 2. Then, a read pulse is applied to the third transfer electrode 3-3 to read the signal charge of the photoelectric conversion unit 100b.

Note that in the horizontal blanking period shown in FIG. 10, the signal charge on the bottom line of the vertical shift register 101 (the bottom row of the photoelectric conversion unit 100) is transferred to the horizontal shift register 102. In the horizontal scanning period shown in FIG. 10 (corresponding to the horizontal line scanning period in FIG. 7), signal charges are transferred in the horizontal direction. As described above, after the signal charge is transferred in the vertical direction, the signal charge is transferred in the horizontal direction by the horizontal shift register 102 and sent to the charge detection unit 103. In the charge detection unit 103, the signal charge is converted into a voltage corresponding to the signal charge amount and output.

Next, effects of the solid-state imaging device according to the present embodiment will be described.

In this embodiment, the signal charge of the photoelectric conversion unit 100 can be read out at three different exposure times. As described above, the three exposure times can be assigned, for example, 2: 1 to the photoelectric conversion unit 100a and the photoelectric conversion unit 100b. The photoelectric conversion unit 100 to which the two exposure times are assigned can make the two exposure times different, for example, by acquiring the signal charges for the long exposure and the short exposure in the same frame. By performing the image composition processing, an image having a wider dynamic range than an image that can be acquired by a normal single exposure can be acquired. At this time, for the other photoelectric conversion unit 100, a normal image can be acquired in the same frame.

Also, it is possible to realize time-of-flight range image sensing using two exposure times. For example, with respect to signal charges accumulated in the photoelectric conversion unit 100 according to the amount of light that is reflected by an object in the irradiation space and reaches the solid-state imaging device when infrared light emitted from a light source that performs pulsed light emission operation is first-time In the exposure time, the signal charge is read after one light emission cycle is completely completed, and in the second exposure time, the signal charge is read in the middle of the light emission cycle. By calculating the image information acquired in this manner, the distance from the object to the solid-state imaging device can be calculated. Also at this time, a normal image can be acquired for the other photoelectric conversion unit 100 in the same frame. That is, in the case of an imaging apparatus in which RGB pixels are allocated to the photoelectric conversion unit 100a and infrared light pixels are allocated to the photoelectric conversion unit 100b, a color image acquired from the photoelectric conversion unit 100a with an optimal exposure time according to the ambient brightness, It is possible to acquire the distance image acquired from the photoelectric conversion unit 100b in the same frame by the intermittent readout operation of the infrared light pixels synchronized with the pulse light emission.

It is also possible to assign three exposure times to the photoelectric conversion unit 100a and the photoelectric conversion unit 100b at 2: 0 or 3: 0. In this case, the signal charges of the photoelectric conversion unit 100 that is not read out may be discarded by applying a high voltage to the n-type well in the deep part of the semiconductor substrate 10. Also in this case, it is possible to acquire an image with a wide dynamic range by acquiring the signal charges of the long exposure and the short exposure in the same frame and performing image composition processing.

Further, the exposure time of 3 times is assigned to the photoelectric conversion unit 100a and the photoelectric conversion unit 100b at 2: 0 or 1: 1, and the signal charge of the remaining exposure time is not read from the photoelectric conversion unit 100, It is also possible to accumulate only spontaneously generated charges in the transfer channel 2. In this case, the amount of noise signals such as smear electrons generated by dark current generated from lattice defects existing inside the transfer channel 2 or the surface of the insulating film 20 or light entering from the gap between the light shielding film 7 and the substrate is measured. If a noise component is subtracted from a normal image, a high-definition image with a good S / N ratio can be acquired.

In addition, since it is possible to simultaneously read out the signal charges for each of all the photoelectric conversion units 100a and all the photoelectric conversion units 100b, even when a mechanical shutter is not mounted on the imaging apparatus, It is possible to acquire image data without distortion.

Assuming that the area not covered with the conductive film such as polysilicon is “opening area”, in this embodiment, the opening area of the light receiving portion 1a is smaller than the opening area of the light receiving portion 1b. However, the opening area is uniform in the photoelectric conversion unit group 104a. Further, the photoelectric conversion unit group 104b has a uniform size. For this reason, if the exposure time is adjusted in accordance with the sensitivity characteristics of the light receiving portions 1a and 1b, it is possible to obtain high-quality images free from spots for the photoelectric conversion portion group 104a and the photoelectric conversion portion group 104b. is there.

(Second Embodiment)
Hereinafter, the solid-state imaging device according to the second embodiment will be described focusing on differences from the first embodiment.

FIG. 11 and FIG. 12 are main part plan views of the solid-state imaging device according to the second embodiment.

In the present embodiment, in the 2N + 1-th and 2 (N + 1) -th vertical shift registers 101 arranged in the horizontal direction, the first transfer electrode 3-1 is connected by the inter-light-receiving unit wiring 4-1a and the inter-light-receiving unit wiring 4-1b. The second transfer electrode 3-2 is connected by the inter-light-receiving portion wiring 4-2a and the inter-light-receiving portion wiring 4-2b.

Specifically, the inter-light-receiving-unit wiring 4-1 a disposed between the 2N + 1-th vertical shift register 101 and the 2 (N + 1) -th vertical shift register 101 is one first included in the 2N + 1-th vertical shift register 101. One transfer electrode 3-1 is connected to two first transfer electrodes 3-1 included in the 2 (N + 1) th vertical shift register 101. Of the two first transfer electrodes 3-1 connected in the 2 (N + 1) th vertical shift register 101, the one located above is the closest electrode of the light receiving unit 1 a.

The inter-light-receiving portion wiring 4-1b disposed between the 2N + 1th vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 includes two first transfer electrodes 3 included in the 2N + 1th vertical shift register 101. −1 and one first transfer electrode 3-1 included in the 2 (N + 1) th vertical shift register 101 are connected. Of the two first transfer electrodes 3-1 connected in the 2N + 1-th vertical shift register 101, the one positioned above is the closest electrode of the light receiving unit 1 a.

The inter-light-receiving-unit wiring 4-2a disposed between the 2N + 1th vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 includes one second transfer electrode 3 included in the 2N + 1th vertical shift register 101. -2 and two second transfer electrodes 3-2 included in the 2 (N + 1) th vertical shift register 101 are connected. Of the two second transfer electrodes 3-2 connected in the 2 (N + 1) -th vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1a below.

The inter-light-receiving-unit wiring 4-2b disposed between the 2N + 1th vertical shift register 101 and the 2 (N + 1) th vertical shift register 101 includes two second transfer electrodes 3 included in the 2N + 1th vertical shift register 101. -2 and one second transfer electrode 3-2 included in the 2 (N + 1) th vertical shift register 101 are connected. Of the two second transfer electrodes 3-2 connected in the 2N + 1-th vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1 a below.

13 is a cross-sectional view taken along line AA ′ in FIG. 12, FIG. 14 is a cross-sectional view taken along line BB ′ in FIG. 12, and FIG. 15 is a cross-sectional view taken along line CC ′ in FIG. FIG.

As shown in FIGS. 11 to 15, the inter-light-receiving portion wiring 4-1a is formed in the upper layer of the insulating film 21 formed on the surface of the inter-light-receiving portion wiring 4-2a in the gap between the light-receiving portions 1 arranged in the vertical direction. The light receiving portion wiring 4-1b is formed in an upper layer of the insulating film 21 formed on the surface of the light receiving portion wiring 4-2b. The inter-light-receiving portion wiring 4-3a is formed on the upper layer of the insulating film 21 formed on the surface of the inter-light-receiving portion wiring 4-4a, and the inter-light-receiving portion wiring 4-3b is formed on the surface of the inter-light-receiving portion wiring 4-4b. It is formed in the upper layer of the formed insulating film 21.

In the 2 (N + 1) th and 2N + 3rd vertical shift registers 101, the third transfer electrode 3-3 is connected by the inter-light-receiving unit wiring 4-3a and the inter-light-receiving unit wiring 4-3b. 3-4 are connected by a light receiving portion wiring 4-4a and a light receiving portion wiring 4-4b.

Specifically, the inter-light-receiving-part wiring 4-3a disposed between the 2 (N + 1) th vertical shift register 101 and the 2N + 3th vertical shift register 101 is included in the 2 (N + 1) th vertical shift register 101. One third transfer electrode 3-3 is connected to two third transfer electrodes 3-3 included in the 2N + 3rd vertical shift register 101. Of the two third transfer electrodes 3-3 connected in the 2N + 3rd vertical shift register 101, the one positioned above is the closest electrode of the light receiving unit 1b.

The inter-light-receiving-unit wiring 4-3b disposed between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 includes two third third circuits included in the 2 (N + 1) th vertical shift register 101. The transfer electrode 3-1 is connected to one third transfer electrode 3-3 included in the 2N + 3rd vertical shift register 101. Of the two third transfer electrodes 3-3 connected in the 2 (N + 1) th vertical shift register 101, the one located above is the closest electrode of the light receiving unit 1b.

The inter-light-receiving-unit wiring 4-4a disposed between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 is one fourth included in the 2 (N + 1) th vertical shift register 101. The transfer electrode 3-4 is connected to the two fourth transfer electrodes 3-4 included in the 2N + 3rd vertical shift register 101. Of the two fourth transfer electrodes 3-4 connected in the 2N + 3rd vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1b below.

The inter-light-receiving-unit wiring 4-4b disposed between the 2 (N + 1) th vertical shift register 101 and the 2N + 3rd vertical shift register 101 includes two fourth fourth shifters included in the 2 (N + 1) th vertical shift register 101. The transfer electrode 3-4 is connected to one fourth transfer electrode 3-4 included in the 2N + 3rd vertical shift register 101. Of the two fourth transfer electrodes 3-4 connected in the 2 (N + 1) th vertical shift register 101, the one located above is adjacent to the nearest electrode of the light receiving unit 1b below.

In FIG. 12, a second shunt wiring 5-2 and a third shunt wiring 5-3 are arranged on the 2N + 1th vertical shift register 101. The second shunt wiring 5-2 is connected to the light receiving section wiring 4-2a and the light receiving section wiring 4-2b through the contact section 6-2. The third shunt wiring 5-3 is connected to the light receiving section wirings 4-3a and 4-3b through the contact section 6-3.

On the 2 (N + 1) th vertical shift register 101, a first shunt wiring 5-1 and a fourth shunt wiring 5-4 are arranged. The first shunt wiring 5-1 is connected to the light receiving section wiring 4-1a and the light receiving section wiring 4-1b through the contact section 6-1. The fourth shunt wiring 5-4 is connected to the light receiving section wiring 4-4a and the light receiving section wiring 4-4b through the contact section 6-4.

As described above, according to the present embodiment, each of the inter-light-receiving portion wirings 4 is connected to the three transfer electrodes 3, so that the area where the inter-light-receiving portion wiring 4 is spread is small, and as a result, the opening area of the light-receiving portion 1 is increased. It is possible. For this reason, it is possible to acquire an image with high sensitivity characteristics for each of the photoelectric conversion unit groups 104a and 104b.

(Third embodiment)
Hereinafter, the solid-state imaging device according to the third embodiment will be described focusing on differences from the first and second embodiments.

FIG. 16 and FIG. 17 are main part plan views of the solid-state imaging device according to the third embodiment.

In the present embodiment, in the 2N + 1-th and 2 (N + 1) -th vertical shift registers 101 arranged in the horizontal direction, the fourth transfer electrode 3-4 is connected by the inter-light-receiving unit wiring 4-4a and the inter-light-receiving unit wiring 4-4b. ing.

Further, in the 2 (N + 1) th and 2N + 3rd vertical shift registers 101, the second transfer electrode 3-2 is connected by the inter-light-receiving unit wiring 4-2a and the inter-light-receiving unit wiring 4-2b.

In each of the vertical shift registers 101, the first transfer electrode 3-1 and the third transfer electrode 3-3 are not connected by the inter-light-receiving portion wiring 4, but are arranged in a floating island shape.

18 is a cross-sectional view taken along the line A-A ′ of FIG. 17, and FIG. 19 is a cross-sectional view taken along the line B-B ′ of FIG. 17.

As shown in FIGS. 16 to 19, on the transfer electrode 3, the first shunt wiring 5-1 and the third shunt wiring 5-3 extending in the vertical direction through the insulating film 21 are disposed, and the contacts are respectively contacted. The parts 6-1 and 6-3 are connected to the first transfer electrode 3-1 and the third transfer electrode 3-3.

An insulating film 22 made of, for example, silicon oxide is formed so as to cover the first shunt wiring 5-1 and the third shunt wiring 5-3. A light shielding film 7 is formed so as to cover the insulating films 21 and 22.

Further, an insulating film 21 is formed on the light receiving portion wirings 4-2a, 4-2b, 4-4a, and 4-4b, and a light shielding film 7 is formed so as to cover the insulating film 21.

Further, a planarizing film 23 made of, for example, silicon oxide is formed so as to cover the light shielding film 7. On the planarizing film 23, a second shunt wiring 5-2 and a fourth shunt wiring 5-4 extending in the vertical direction are arranged. A second shunt wiring 5-2 is disposed on the 2N + 1th transfer channel 2, and a fourth shunt wiring 5-4 is disposed on the 2 (N + 1) th transfer channel 2.

The second shunt wiring 5-2 and the fourth shunt wiring 5-4 project horizontally in the gap between the light receiving portions 1. The second shunt wiring 5-2 is connected to the light receiving section wirings 4-2a and 4-2b at the contact section 6-2, and the fourth shunt wiring 5-4 is connected to the light receiving section wiring 4-4a at the contact section 6-4. , 4-4b.

In the present embodiment, only the second transfer electrode 3-2 and the fourth transfer electrode 3-4, which are the first layer electrode materials, are connected by the inter-light receiving portion wiring 4, and the first layer electrode material is the first layer electrode material. Since the transfer electrode 3-1 and the third transfer electrode 3-3 are not connected by the inter-light-receiving portion wiring 4, there is no region where the first layer electrode material and the second layer electrode material overlap.

Further, when the shunt wiring 5 is formed of a metal film, a wiring having the same signal delay characteristic can be formed with a smaller film thickness than when formed of polysilicon. Therefore, in the present embodiment, it is possible to further reduce the height from the light receiving surface to the uppermost wiring layer, and as a result, light incident from an oblique direction is less likely to be blocked by the wiring layer. A large amount of light reaches the light receiving unit 1. Therefore, in the present embodiment, it is possible to realize a solid-state imaging device capable of acquiring a clear image even when a dark subject is imaged.

(Fourth embodiment)
Hereinafter, the solid-state imaging device according to the fourth embodiment will be described focusing on differences from the third embodiment.

FIG. 20 and FIG. 21 are plan views of main parts of a solid-state imaging device according to the fourth embodiment. 22 is a cross-sectional view taken along the line A-A ′ in FIG. 21, and FIG. 23 is a cross-sectional view taken along the line B-B ′ in FIG. 21.

For example, in the third embodiment, the first shunt wiring 5-1, the third shunt wiring 5-3, and the light shielding film 7 are formed separately, but in the present embodiment, the first shunt wiring 5-1. The third shunt wiring 5-3 is also used as the light shielding film 7.

Specifically, in FIGS. 20 to 23, reference numeral 8-1 denotes a light shielding film / shunt wiring having the functions of the first shunt wiring 5-1 and the light shielding film 7 in the third embodiment. Reference numeral 8-3 denotes a light-shielding film / shunt wiring having functions of the second shunt wiring 5-3 and the light-shielding film 7 in the third embodiment.

As shown in FIGS. 20 to 23, the light shielding film / shunt wirings 8-1 and 8-3 are formed on the transfer electrode 3 with an insulating film 21 interposed therebetween. It is formed to be divided into two. The light shielding film / shunt wirings 8-1 and 8-3 are arranged to extend in a direction parallel to the vertical shift register 101.

In the present embodiment, the height from the light receiving surface to the uppermost wiring layer can be reduced, and as a result, light incident from an oblique direction is less likely to be blocked by the wiring layer, and more The amount of light can reach the light receiving unit. Therefore, in the present embodiment, it is possible to realize a solid-state imaging device capable of acquiring a clear image even with a dark subject.

In each of the above-described embodiments, the structure above the shunt wiring can be variously changed. In addition, various modifications can be made without departing from the scope of the present disclosure.

In the solid-state imaging device according to the present disclosure, the photoelectric conversion units included in the two photoelectric conversion unit groups are arranged in an offset sub-sampling manner, and they are combined by shifting the phase of one pixel in both the horizontal direction and the vertical direction. The present invention can be applied to a solid-state imaging device to be arranged.

1, 1a, 1b Light receiving part 2 Transfer channel 3,3-1,3-2,3-3,3-4 Transfer electrode 4,4-1,4-2,4-3,4-4 Light receiving part wiring 4-1a, 4-1b, 4-2a, 4-2b, 4-3a, 4-3b, 4-4a, 4-4b Light receiving unit wiring 100, 100a, 100b Photoelectric conversion unit 101 Vertical shift register 102 Horizontal shift Register 103 Charge detection unit 104a, 104b Photoelectric conversion unit group

Claims (8)

1. A first photoelectric conversion unit group and a second photoelectric conversion unit group, which are arranged in an offset sub-sampling manner in a horizontal direction and a vertical direction and include a photoelectric conversion unit that converts incident light into a signal charge by photoelectric conversion; Each of the photoelectric conversion units included in one photoelectric conversion unit group and the photoelectric conversion units included in the second photoelectric conversion unit group are combined by shifting the phase by one in both the horizontal direction and the vertical direction. An imaging unit arranged so as to form a square lattice as a whole,
   A light receiving portion from which a light shielding film is excluded so that light is irradiated onto the surface of the semiconductor substrate on which the photoelectric conversion portion is formed;
   A plurality of transfer channels disposed between the light receiving portions and extending in the vertical direction;
   A first transfer electrode, a second transfer electrode, a third transfer electrode, and a fourth transfer electrode, which are repeatedly arranged in the vertical direction on the transfer channel,
   Including the transfer channel and the first to fourth transfer electrodes, and applying a high voltage pulse to one of the first to fourth transfer electrodes once or a plurality of times, A plurality of vertical shift registers that transfer the signal charges moved from the photoelectric conversion unit group to the transfer channel in the vertical direction of the imaging unit;
   A horizontal shift register connected to the final stage of the vertical shift register and transferring the signal charge transferred from the vertical shift register in the horizontal direction;
   A charge detector connected to the last stage of the horizontal shift register and converting a signal charge transferred from the horizontal shift register into a voltage signal;
   The first to fourth transfer electrodes are repeatedly arranged three times in an arbitrary order within a section equal to a distance twice the interval in which the photoelectric conversion unit and the light receiving unit are arranged in a square lattice pattern,
   The solid-state imaging device according to any one of the two vertical shift registers arranged adjacent to each other in the horizontal direction, wherein the arrangement order of the first to fourth transfer electrodes is an offset of two electrodes.
2. The individual imaging apparatus according to claim 1,
   The first to fourth transfer electrodes are composed of a first layer electrode material or a second layer electrode material, and are repeatedly arranged in the horizontal direction in a region between the light receiving portions arranged in a square lattice shape. Three or four of the first to fourth transfer electrodes made of the first layer electrode material or the second layer electrode material arranged on two adjacent transfer channels of the transfer channels. The electrodes are connected by the same electrode material by the inter-light-receiving portion wiring formed integrally with the same electrode material as the first to fourth transfer electrodes,
   In addition, an electrode to which the signal charges of the photoelectric conversion unit group are directly moved when the high voltage pulse is applied, and either the first photoelectric conversion unit group or the second photoelectric conversion unit group among the light receiving units. In a region between the light receiving portion located on the upper surface side in the thickness direction of one semiconductor substrate, a wiring that connects the four electrodes is formed,
   Between the other light receiving unit located on the upper surface side in the thickness direction of the semiconductor substrate of the photoelectric conversion unit group and the electrode to which the signal charge of the photoelectric conversion unit group directly moves when the high voltage is applied The solid-state imaging device is characterized in that a wiring forming a part of the connection of the four electrodes is not formed in the region.
3. The solid-state imaging device according to claim 1,
   The first to fourth transfer electrodes are formed of a first layer electrode material or a second layer electrode material, and in the region between the light receiving portions arranged in a square lattice shape, the first to fourth transfer electrodes Three electrodes which are each of the first to fourth transfer electrodes made of the first layer electrode material or the second layer electrode material are connected by the wiring between the light receiving parts integrally molded with the same electrode material,
   And in the wiring between the light receiving parts of two identical electrode materials adjacent in the vertical direction, the transfer channel in which two of the three electrodes to be connected are located is different,
   In addition, the total of six transfer electrodes to which the adjacent inter-light-receiving-part wirings of the same two electrode materials are connected include any two of the first to fourth transfer electrodes. Imaging device.
4. The solid-state imaging device according to claim 1,
   The first to fourth transfer electrodes are formed of a single layer electrode material, and are integrated with the same electrode material as the first to fourth transfer electrodes in a region between the light receiving portions arranged in a square lattice pattern. Three electrodes are connected by the molded wiring between the light receiving parts,
   And, in the two inter-light receiving portion wirings adjacent in the vertical direction, the transfer channel where the two electrodes among the three electrodes to which the two inter-light receiving portion wirings are connected is different,
   In addition, the total of six transfer electrodes connected by the two adjacent light receiving unit wirings include any two of the first to fourth transfer electrodes,
   The solid-state imaging device is characterized in that the unconnected transfer electrodes are located one by one between the connected transfer electrodes.
5. A method for driving the solid-state imaging device according to claim 1,
   Either one of the first photoelectric conversion unit group or the second photoelectric conversion unit group is applied by applying a high voltage pulse once or a plurality of times to any one of the first to fourth transfer electrodes. An operation of moving the signal charge from one side to the transfer channel and not moving the signal charge of the other photoelectric conversion unit group;
   Repeating the operation once, twice, or three times within a continuous period in which the horizontal shift register is not transferring signal charges;
   Holding the signal charge moved to the transfer channel in a different region in the transfer channel for each repetition of the operation;
   And a step of starting an operation of transferring the signal charge from the vertical shift register to the horizontal shift register after all the repetition of the operation is completed.
6. The solid-state imaging device driving method according to claim 5,
   In the case where the operation is repeated once or twice in a continuous period in which the horizontal shift register does not transfer the signal charge,
   Generating a region not including the signal charge in the transfer channel;
   After the generating step, driving the vertical shift register and the horizontal shift register to convert a noise signal charge mixed in a region not including the signal charge into a voltage signal by the charge detection unit and outputting the voltage signal A method for driving a solid-state imaging device.
7. The solid-state imaging device driving method according to claim 5,
   In the case where the operation is repeated twice or three times within a continuous period in which the horizontal shift register is not transferring signal charges,
   The method for driving a solid-state imaging device, wherein the photoelectric conversion unit groups to which the signal charges are moved to the transfer channel are different between the first and second times or the second and third times of the repetition of the operation .
8. The solid-state imaging device driving method according to claim 5,
   The first to fourth transfer electrodes are composed of a first layer electrode material or a second layer electrode material, and the second layer electrode material is formed after the first layer electrode material is formed in the manufacturing process of the solid-state imaging device. The method of driving a solid-state imaging device, wherein the transfer electrode formed and applied with the high voltage among the first to fourth transfer electrodes is a second layer electrode material.

Images