CN109804617B

CN109804617B - Image sensor and control method thereof

Info

Publication number: CN109804617B
Application number: CN201880003761.9A
Authority: CN
Inventors: 物井诚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-11-05
Filing date: 2018-11-05
Publication date: 2020-07-07
Anticipated expiration: 2038-11-05
Also published as: CN109804617A; WO2020093197A1

Abstract

An image sensor and a control method thereof capable of improving a processing speed while maintaining high sensitivity and high resolution are provided. The image sensor includes: a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein one photoelectric conversion element corresponds to each pixel constituting the pixel block; a plurality of charge/voltage converters for converting charges output from the photoelectric conversion elements included in the pixel block into voltages; and the signal converter is connected with the plurality of charge/voltage converters to convert the voltage signals output by the plurality of charge/voltage converters contained in each pixel block together. In an embodiment, the image sensor includes at least one charge/voltage converter, wherein the at least one charge/voltage converter is shared by at least one photoelectric conversion element corresponding to a pixel arranged separately from the at least one charge/voltage converter.

Description

Image sensor and control method thereof

Technical Field

The present invention relates to an image sensor and a control method thereof, and more particularly, to an image sensor for a camera function of a cellular phone or the like and a control method thereof.

Background

An image sensor, such as a CMOS image sensor, which converts light into an electrical signal includes a plurality of photoelectric conversion elements in a matrix form for each color in a color filter array. The photoelectric conversion element may be realized by, for example, a photodiode, converts incident light into electric charges corresponding to the amount of light, and stores the electric charges. The stored charges are converted into voltages, which are in turn converted into digital signals corresponding to each color to be output.

Recently, in order to meet the demand for image sensors having high sensitivity and high resolution, the number of photoelectric conversion elements provided for each corresponding color is increasing. Accordingly, the number of a plurality of pixels (pixel blocks) corresponding to the photoelectric conversion element of each color is also increasing.

However, as the number of pixels included in a pixel block increases, the number of processing steps required for analog-to-digital conversion (hereinafter referred to as "ADC step") also increases. The increase in the number of processing steps results in an increase in the noise to be read.

Disclosure of Invention

The present invention provides an image sensor capable of improving a processing speed while maintaining high sensitivity and high resolution, and a control method thereof.

A first aspect provides an image sensor comprising:

a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block;

a plurality of charge/voltage converters for converting the charges output from the photoelectric conversion elements in the pixel block into voltages;

a signal converter connected to the plurality of charge/voltage converters to collectively convert voltage signals output from the plurality of charge/voltage converters included in each pixel block;

wherein each pixel in the block of pixels corresponding to the one filter color is connected to the signal converter via an associated one of the plurality of charge-to-voltage converters, wherein the associated charge-to-voltage converter is shared by each pixel.

In a first possible implementation manner of the first aspect, the plurality of pixel blocks are arranged in a matrix.

In a second possible implementation form of the first aspect, the charge-to-voltage converter converts only the charges output by the photoelectric conversion elements in one pixel block into voltages.

In a third possible implementation form of the first aspect, the charge-to-voltage converter is shared by only the photoelectric conversion elements in one pixel block.

In a fourth possible implementation form of the first aspect, the pixel block comprises pixels arranged in a3 × 3 matrix form according to the first aspect or any one of the first to third possible implementation forms of the first aspect.

According to a fourth possible implementation form of the first aspect, in a fifth possible implementation form of the first aspect, the plurality of charge/voltage converters includes at least a first charge/voltage converter shared by two of the photoelectric conversion elements and a second charge/voltage converter shared by three of the photoelectric conversion elements.

According to a fourth possible implementation form of the first aspect, in a sixth possible implementation form of the first aspect, the plurality of charge/voltage converters includes a first charge/voltage converter shared by three of the photoelectric conversion elements and a second charge/voltage converter shared by six of the photoelectric conversion elements.

According to a fourth possible implementation form of the first aspect, in a seventh possible implementation form of the first aspect, the plurality of charge/voltage converters includes a first charge/voltage converter shared by two of the photoelectric conversion elements, a second charge/voltage converter shared by three of the photoelectric conversion elements, and a third charge/voltage converter shared by four of the photoelectric conversion elements.

According to a fourth possible implementation form of the first aspect, in an eighth possible implementation form of the first aspect, the plurality of charge/voltage converters includes three charge/voltage converters, wherein each charge/voltage converter is shared by three photoelectric conversion elements.

In a ninth possible implementation form of the first aspect, the pixel block comprises pixels arranged in a matrix of 2 × 4, according to the first aspect or any one of the first to third possible implementation forms of the first aspect.

According to a ninth possible implementation form of the first aspect, in a tenth possible implementation form of the first aspect, the plurality of charge-to-voltage converters includes two charge-to-voltage converters shared by four of the photoelectric conversion elements.

According to a ninth possible implementation manner or a tenth possible implementation manner of the first aspect, in an eleventh possible implementation manner of the first aspect, the pixel block includes eight pixels, and a longitudinal direction of the pixel block is a horizontal direction or a vertical direction.

In a twelfth possible implementation form of the first aspect according to any of the ninth to eleventh possible implementation form of the first aspect, an array of lenses of size 1/8 pixel blocks is superimposed on the pixel blocks, wherein the lenses are arranged tilted with respect to the pixels by a predetermined angle θ.

According to a twelfth possible implementation manner of the first aspect, in a thirteenth possible implementation manner of the first aspect, the predetermined angle θ is 45 degrees.

In a fourteenth possible implementation manner of the first aspect, according to any one of the fourth to thirteenth possible implementation manners of the first aspect, one lens is superimposed on two or four adjacent pixels included in the pixel block.

A second aspect provides an image sensor comprising:

at least one charge/voltage converter for converting the charge output from the photoelectric conversion element in the pixel block into a voltage;

the signal converter is connected with the at least one charge/voltage converter to convert the voltage signals output by the at least one charge/voltage converter contained in each pixel block together;

wherein each pixel in the pixel block corresponding to the one filter color is connected to the signal converter via the at least one charge-to-voltage converter, wherein the at least one charge-to-voltage converter is shared by each pixel, and the photoelectric conversion element connected to the at least one charge-to-voltage converter includes a photoelectric conversion element corresponding to a pixel arranged separately from the at least one charge-to-voltage converter.

In a first possible implementation manner of the second aspect, the plurality of pixel blocks are arranged in a matrix form.

In a second possible implementation form of the second aspect, the at least one charge-to-voltage converter converts only the charge output by the photoelectric conversion element included in one pixel block into a voltage.

In a third possible implementation form of the second aspect, the at least one charge-to-voltage converter is shared by only the photoelectric conversion elements comprised by one pixel block.

In a fourth possible implementation form of the second aspect, the pixel block comprises an array of eight pixels.

In a fifth possible implementation form of the second aspect, according to the second aspect or the fourth possible implementation form of the second aspect, each row of the pixel blocks includes three pixels, two pixels, and three pixels.

In a sixth possible implementation form of the second aspect, according to the second aspect or the fourth possible implementation form of the second aspect, the pixel block includes four adjacent pixels and four pixels arranged separately.

In a seventh possible implementation form of the method according to the second aspect as such or according to any of the first to fifth possible implementation forms of the second aspect, an array of lenses of size 1/9 pixel blocks is superimposed on the pixel blocks.

A third aspect provides an image sensor comprising:

and the pixel block corresponds to one filtering color and comprises a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels forming the pixel block, and the pixel block comprises eight pixels, and the longitudinal direction of the pixel block is a horizontal direction or a vertical direction.

In a first possible implementation manner of the third aspect, the pixel block includes pixels arranged in a matrix of 2 × 4.

According to a first possible implementation manner of the third aspect, in a second possible implementation manner of the third aspect, the image sensor includes a plurality of pixel blocks, wherein one of the pixel blocks includes eight pixels whose longitudinal directions are horizontal directions, and another one of the pixel blocks includes eight pixels whose longitudinal directions are vertical directions.

In a third possible implementation form of the third aspect according to the third aspect as such or according to the first or second possible implementation form of the third aspect, an array of lenses of size 1/8 pixel blocks is superimposed on the pixel blocks, wherein the lenses are arranged tilted with respect to the pixels by a predetermined angle θ.

According to a third possible implementation manner of the third aspect, in a fourth possible implementation manner of the third aspect, the predetermined angle θ is 45 degrees.

In a fifth possible implementation form of the third aspect or the first or second possible implementation form of the third aspect, a lens is superimposed on two or four adjacent pixels included in the pixel block.

A fourth aspect provides an image sensor comprising:

the pixel block corresponds to one filtering color and comprises a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements correspond to pixels forming the pixel block respectively, and each line of the pixel block comprises three pixels, two pixels and three pixels respectively.

A fifth aspect provides an image sensor comprising:

and a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, and the pixel block includes four adjacent pixels and four pixels arranged separately.

A sixth aspect provides an image sensor comprising:

and a pixel block corresponding to one of the filter colors and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, and the pixel block includes pixels arranged in a3 × 3 matrix form.

In a first possible implementation manner of the sixth aspect, one lens is superimposed on two or four adjacent pixels included in the pixel block.

A seventh aspect provides a signal reading method of an image sensor, wherein the image sensor includes: a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block; a plurality of charge/voltage converters for converting the charges output from the photoelectric conversion elements in the pixel block into voltages; a signal converter connected to the plurality of charge/voltage converters to convert voltage signals output from the plurality of charge/voltage converters included in each pixel block; wherein each pixel in the block of pixels corresponding to the one filter color is connected to the signal converter via an associated one of the plurality of charge-to-voltage converters, wherein the associated charge-to-voltage converter is shared by each pixel; the method comprises the following steps:

providing voltage signals output by a plurality of charge/voltage converters included in a first pixel block to the signal converter in common;

the voltage signals output by the plurality of charge/voltage converters included in the second pixel block are supplied in common to the signal converter.

An eighth aspect provides a signal reading method of an image sensor, wherein the image sensor includes: a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements corresponding to pixels constituting the pixel block; at least one charge/voltage converter for converting the charge output from the photoelectric conversion element in the pixel block into a voltage; the signal converter is connected with the at least one charge/voltage converter to convert the voltage signal output by the at least one charge/voltage converter contained in each pixel block; wherein each pixel in the pixel block corresponding to the one filter color is connected to the signal converter via the at least one charge-to-voltage converter, wherein the at least one charge-to-voltage converter is shared by each pixel, and the photoelectric conversion element connected to the at least one charge-to-voltage converter includes a photoelectric conversion element corresponding to a pixel arranged separately from the at least one charge-to-voltage converter; the method comprises the following steps:

providing voltage signals output by at least one charge/voltage converter contained in the first pixel block to the signal converter in common;

and providing the voltage signals output by at least one charge/voltage converter contained in the second pixel block to the signal converter in a common mode.

A ninth aspect provides a signal reading method of an image sensor, wherein the image sensor includes: a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, the pixel block includes eight pixels, and a longitudinal direction thereof is a horizontal direction or a vertical direction; the method comprises the following steps:

providing voltage signals output by a plurality of photoelectric conversion elements included in the first pixel block to a signal converter in common;

and the voltage signals output by the plurality of photoelectric conversion elements included in the second pixel block are commonly supplied to the signal converter.

A tenth aspect provides a signal reading method of an image sensor, wherein the image sensor includes: the pixel block corresponds to one filtering color and comprises a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels forming the pixel block, and each row of the pixel block respectively comprises three pixels, two pixels and three pixels; the method comprises the following steps:

An eleventh aspect provides a signal reading method of an image sensor, wherein the image sensor includes: a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, and the pixel block includes four adjacent pixels and four pixels arranged separately; the method comprises the following steps:

A twelfth aspect provides a signal reading method of an image sensor including a pixel block corresponding to one filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, the pixel block including pixels arranged in a3 × 3 matrix form, the method including the steps of:

The above configuration can improve the processing speed while maintaining high sensitivity and high resolution.

Drawings

(fig. 1) fig. 1 is a block diagram of a configuration example including a solid-state image sensing device provided for an embodiment;

(fig. 2) fig. 2 is a diagram showing a circuit included in a pixel array of a CMOS image sensor;

(fig. 3A) fig. 3A is a diagram showing a configuration of a signal reading side of the CMOS image sensor;

(FIG. 3B) FIG. 3B is a diagram showing a color filter array on the light receiving side of the circuit of FIG. 3A;

(FIG. 4A) FIG. 4A is a cross-sectional view of the pixel array of FIGS. 3A and 3B along arrow IVA;

(fig. 4B) fig. 4B is a diagram showing the electric potential of the pixel array shown in fig. 4A;

(FIG. 4C) FIG. 4C is a pulse timing diagram of the control signal;

(fig. 5) fig. 5 is a diagram showing an example of a color filter array;

(fig. 6) fig. 6 is a diagram showing an example of a color filter array;

(fig. 7) fig. 7 is a diagram showing an example of a color filter array;

(fig. 8A) fig. 8A is a diagram showing a pixel block of one filter color comprising a pixel array of 2 × 2 pixels;

(fig. 8B) fig. 8B is a graph showing signals read in the ADC step;

(FIG. 8C) FIG. 8C is a pulse timing diagram of the control signal;

(fig. 9A) fig. 9A is a diagram showing a pixel block of one filter color comprising a pixel array of 3 × 3 pixels;

(fig. 9B) fig. 9B is a graph showing signals read in the ADC step;

(fig. 10A) fig. 10A is a diagram showing a configuration of a signal reading side of a pixel array provided by an embodiment;

(fig. 10B) fig. 10B is a graph showing signals read in the ADC step;

(fig. 11A) fig. 11A is a view showing a lens portion superimposed on a pixel array;

(FIG. 11B) FIG. 11B is a cross-sectional view taken along horizontal arrow XIB in FIG. 11A;

(fig. 12) fig. 12 is a diagram showing a configuration of a signal reading side of a pixel array provided by an embodiment;

(fig. 13) fig. 13 is a diagram showing a configuration of a signal reading side of a pixel array provided by an embodiment;

(fig. 14) fig. 14 is a diagram showing a configuration of a signal reading side of a pixel array provided by an embodiment;

(FIG. 15) FIG. 15 is a diagram showing a color filter array provided by an embodiment;

(fig. 16) fig. 16 is a diagram showing a lens portion superimposed on a pixel array;

(fig. 17A) fig. 17A is a diagram showing a configuration of a signal reading side of a pixel array provided by an embodiment;

(FIG. 17B) FIG. 17B is a cross-sectional view taken along vertical arrow XVIIB in FIG. 17A;

(FIG. 17C) FIG. 17C is a cross-sectional view taken along the horizontal direction by arrow XVIII in FIG. 17A;

(FIG. 18) FIG. 18 is a diagram showing a color filter array provided by an embodiment;

(fig. 19A) fig. 19A is a view showing a lens portion superimposed on a pixel array;

(FIG. 19B) FIG. 19B is a cross-sectional view taken along horizontal direction arrow XIXB in FIG. 19A;

(FIG. 20) FIG. 20 is a diagram showing a color filter array provided by an embodiment;

(fig. 21A) fig. 21A is a view showing a lens portion superimposed on a pixel array;

(fig. 21B) fig. 21B is a cross-sectional view along the horizontal direction arrow XXIB in fig. 21A;

(fig. 21C) fig. 21C is a cross-sectional view along vertical direction arrow XXIC in fig. 21A;

(fig. 22) fig. 12 is a diagram showing a configuration of a signal reading side of a pixel array provided by an embodiment;

(fig. 23A) fig. 23A is a view showing a lens portion superimposed on a pixel array;

(FIG. 23B) FIG. 23B is a cross-sectional view taken along the vertical direction arrow XXIIIB in FIG. 23A;

(fig. 24A) fig. 24A is a view explaining the operation of the phase difference AF;

(fig. 24B) fig. 24B is a diagram illustrating the operation of the phase difference AF;

(fig. 25) fig. 25 is a view showing a lens portion superimposed on a pixel array;

(fig. 26A) fig. 26A is a view showing a lens portion superimposed on a pixel array;

(fig. 26B) fig. 26B is a cross-sectional view along horizontal direction arrow XXVIB in fig. 26A;

(fig. 27) fig. 27 is a view showing a lens portion superimposed on a pixel array;

(FIG. 28) FIG. 28 is a diagram showing a color filter array provided by an embodiment;

(fig. 29) fig. 29 is a view showing a lens portion provided in an embodiment;

(fig. 30) fig. 30 is a diagram of an example of a combination of a pixel array and a lens portion;

(FIG. 31) FIG. 31 is a diagram showing a color filter array provided by an embodiment;

(FIG. 32) FIG. 32 is a diagram of an example of a color filter array in combination with a lens portion;

(FIG. 33) FIG. 33 is a diagram of an example of a color filter array in combination with a lens portion;

(fig. 34A) fig. 34A is a diagram showing a configuration of a signal reading side of the pixel array in fig. 33;

(fig. 34B) fig. 34B is a diagram showing a layout example of transistors in the pixel array in fig. 34A;

(FIG. 35) FIG. 35 is a flowchart of a signal reading method according to an embodiment.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention.

It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

First, the operation principle of the present embodiment is described with reference to fig. 1 to 9.

Fig. 1 is a block diagram of an example of a configuration of an image sensor provided in the present embodiment.

The CMOS image sensor 100 includes a pixel array 104, the pixel array 104 includes a plurality of pixel circuits arranged in a two-dimensional form (matrix form) of N rows and × M columns, a vertical scanning circuit 102 that supplies pixel driving signals is provided at one end (left side in the drawing) of the pixel array 104, the pixel array 104 and the vertical scanning circuit 102 are connected together by a transfer gate (hereinafter, abbreviated as "TG") pulse signal line 114, and further, a signal converter 108 and a horizontal scanning circuit 110 connected to each column signal line 116 are provided at the lower end (lower side in the drawing) of an image area.

The CMOS image sensor 100 includes a timing controller 106. The timing controller 106 generates and outputs a master clock or a clock obtained by dividing the master clock. The vertical scanning circuit 102, the signal converter 108, and the horizontal scanning circuit 110 are controlled in synchronization with the clock output from the timing controller 106.

The vertical scanning circuit 102 sets an address and controls vertical scanning. The signal converters 108 each perform signal conversion to convert an analog output of, for example, a pixel into a digital output, and output the digital output to the output circuit 112. The horizontal scanning circuit 110 sequentially selects the signal converters 108 in synchronization with the clock output from the timing controller 106, and reads a signal from the selected signal converters 108 and outputs the signal to the output circuit 112.

The output circuit 112 converts the digital output converted by the signal converter 108 into a signal corresponding to the color arrangement and outputs the signal. The converted signal is output to a display controller 120 for displaying, for example, an image on a display and an AF controller 118 for controlling Auto Focus (AF). The display controller 120 includes a Digital Signal Processor (DSP) and the like. The AF controller 118 includes a Central Processing Unit (CPU) and the like.

Fig. 2 is a diagram showing a circuit included in the pixel array 104 of the CMOS image sensor 100 provided in the present embodiment. In fig. 2, TG pulse signal lines VTG1_ n (hereinafter simply referred to as "VTG 1_ n", etc.), VTG2_ n, VTG3_ n, VTG4_ n, VTG1_ n +1, VTG2_ n +1, VTG3_ n +1, and VTG4_ n +1 correspond to the TG pulse signal lines 114 in fig. 1. Further, the signal line Vsig in fig. 2 corresponds to the signal line 116 in fig. 1.

The pixel block 202 surrounded by a dotted line in fig. 2 includes four photodiodes PD1_ n, m (hereinafter referred to as "PD 1" or the like), PD2_ n, m +1, PD3_ n, m +1, and PD4_ n, m, where m and n respectively denote a column number and a row number of a pixel block included in the pixel array. It is to be noted that, as described later with reference to fig. 10 and the like, although the present embodiment relates to an example in which nine photodiodes are provided for one filter color to form one pixel block, four photodiodes are included here for simplicity of explanation.

The photodiode serves as a photoelectric conversion element that converts incident light into electric charges corresponding to the amount of light. Cathodes of the PDs 1_ n, m, PD2_ n, m +1, PD3_ n, m +1 and PD4_ n, m are respectively connected with input parts of gates of transmission gates TG1_ n, m (hereinafter abbreviated as TG1), TG2_ n, m +1, TG3_ n, m +1 and TG4_ n, m, and the VTGs 1_ n, VTG2_ n, VTG3_ n and VTG4_ n are respectively connected with input parts of gates of the TGs 1_ n, m, TG2_ n, m +1, TG3_ n, m +1 and TG4_ n, m. When a transfer signal is input from the VTG to its gate, the TG is turned on. The drain of the TG shares a diffusion layer with the source of the reset transistor (hereinafter referred to simply as "RS" or the like) to form a floating diffusion (hereinafter referred to simply as "FD" or the like). When the TG is turned on, charges stored by photoelectric conversion of the PD are transferred onto the FD.

When a reset signal is input from the signal line VRS _ n, the RS is turned on to reset the potential of the FD to the potential of the power supply line.

The FD functions as a charge/voltage converter that converts charges into voltages. The FD includes a capacitance Cfd for storing electric charges generated by one of the PDs 1 to 4 in association with the PD, and is connected to an input portion (hereinafter, simply referred to as "AMP") of a gate of an amplifier transistor. The AMP is connected to the signal line Vsig through a selection transistor (hereinafter, simply referred to as "SL"). When a control signal is input to the gate thereof from the signal line VSL _ n, the SL is turned on. The signal line is connected to a constant current source (not shown) so that the AMP and the constant current source form a source follower circuit when the SL is turned on, the AMP outputting a low-resistance signal corresponding to the potential of the FD to a vertical signal line Vsig. The voltages output from the respective pixels through the vertical signal line Vsig are output to the signal converter 108. The signal converter 108 includes a CDS (correlated double sampling) circuit (hereinafter, abbreviated as "CDS") and an analog-to-digital conversion circuit (hereinafter, abbreviated as "ADC"). The CDS holds the reset voltage and the signal voltage output from the FD by a sample-and-hold circuit (S/H), and obtains the difference of these voltages. The ADC commonly converts analog voltage signals output from the CDS into digital signals.

Fig. 3A is a diagram illustrating the PD sharing one FD shown in fig. 2, which shows the configuration of the signal reading side of the pixel array. Fig. 3A shows two adjacent pixel blocks, wherein each pixel block comprises the PD 1-PD 4 as described above. The PDs 1 to 4 share an FD by the TGs 1 to 4, and the FD can convert the charges of the PDs 1 to PD4 into voltages. According to the present embodiment, with such a single FD, it is possible to suppress an increase in the number of ADC steps that would otherwise increase as the number of Pixels (PDs) increases, by appropriately determining the number and arrangement (connection relationship) of PDs sharing the FD, as described later with reference to fig. 10 and the like.

Referring to fig. 3A, eight PDs share one circuit including AMP, SL, RS, and FD.

Fig. 3B shows a color filter array on the light receiving side of the pixel array of fig. 3A. Each pixel block corresponds to one color, i.e., green (Gr or Gb), red (R) or blue (B). The green pixel is clearly displayed as Gr when the color of the pixel block horizontally adjacent to the green pixel is red, and as Gb when the color of the pixel block horizontally adjacent to the green pixel is blue.

Fig. 4A is a cross-sectional view of the pixel array along arrow IVA in fig. 3A and 3B. In fig. 4A, light is input to the pixel array 200 from the lower side in the figure via the lens portion 302 and the color filter 310 that passes light of a specific color, and charges are read out from the upper side in the figure. The pixel array 200 is implemented on a single semiconductor substrate, and a P-well 306 is disposed between the PDs 1-4. One PD includes the first PD 302_1 and the PD 302_2 having different impurity concentrations, but combined to form a single diffusion layer.

Fig. 4B is a diagram showing the potential of the pixel array shown in fig. 4A. In the figure, the left PD1 and PD4 correspond to pixel blocks of the nth row, and the right PD1 and PD4 correspond to pixel blocks of the (n + 1) th row, where subscripts m and n are omitted. Fig. 4C is a pulse timing diagram of the control signals of the pixel array of fig. 4A. Next, the operation of the pixel array is described with reference to fig. 2 to 4.

First, in the absence of light, electric charges generated in the photodiode by a dark power source or the like are removed. At time t1, the control signals of VTG1_ n to VTG4_ n become high level, turning on the TG1, TG2, TG3, and TG4 of the nth row. Meanwhile, when the control signal of the signal line VRS _ n becomes a high level, the RS is turned on. Accordingly, the charges of the PD1, PD2, PD3, and PD4 of the nth row flow to the RS through the FD. Then, the voltages of the PD1, PD2, PD3, and PD4 are reset.

Next, when the control signals of the VTGs 1_ n to 4_ n become high level, the TGs 1, TG2, TG3 and TG4 of the n +1 th row are turned on. Meanwhile, when the control signal of the signal line VRS _ n becomes a high level, the RS is turned on. Accordingly, the charges of the PD1, PD2, PD3, and PD4 of the n +1 th row flow to the RS through the FD. Then, the voltages of the PD1, PD2, PD3, and PD4 are reset.

Then, at time t2, the RS is turned on in accordance with the control signal of the signal line VRS _ n so that the voltage of the FD is the same as the voltage of the reset transistor.

At a time t3 when a predetermined charge integration period Tint elapses from the time t1, when the control signals of the signal lines VTG1_ n to VTG4_4 become high level, the TG1, TG2, TG3, and TG4 of the nth row are turned on. Accordingly, the charges of the PD1 to PD4 flow into the FD of the nth row. Meanwhile, when the control signal of the signal line VRS _ n becomes a high level, the SL is turned on. Then, the charges stored in the nth row FD are transferred to the signal line Vsig through the AMP and the SL. The signal is provided to the ADC.

Subsequently, at time t4, when the control signals of the VTGs 1_ n +1 to VTG4_ n +1 become high while the SL remains in the on state, the TGs 1, TG2, TG3, and TG4 of the n +1 th row are turned on. Accordingly, the charges of the PD1 to PD4 flow into the FD of the n +1 th row. Meanwhile, when the control signal of the signal line VRS _ n becomes a high level, the SL is turned on. Then, the charges stored in the n +1 th row FD are transferred to the signal line Vsig through the AMP and the SL. The signal is provided to the ADC.

Fig. 5 to 7 are diagrams illustrating a relationship between a color filter array and a resolution.

Fig. 5 shows a bayer array in which Gr and R or B and Gb are alternately arranged in a horizontal direction, in the example shown in fig. 5, a pixel block corresponding to each filter color has one PD. so that a length a1 of one side of the pixel block is the same as a length B1 of one side of one pixel corresponding to the PD, fig. 6 shows an example in which a pixel block corresponding to each filter color has two Pixels (PDs) in a vertical direction and two pixels (2 × 2) in a horizontal direction, and thus, a length a2 of one side of the pixel block is twice as long as a length B2 of one side of one pixel, fig. 7 shows an example in which a pixel block corresponding to each filter color has three Pixels (PDs) in a vertical direction and three pixels (3 × 3) in a horizontal direction, and thus, a length a3 of one side of the pixel block is three times as long as a length B3 of one side of one pixel.

The lengths a1, a2, and a3 of one side of the pixel block correspond to the area of the PD and have a relationship of a1< a2< a3, and thus, the magnitude of the sensitivity in fig. 5 to 7 is fig. 5< fig. 6< fig. 7 for the sum of signals from PDs of 2 × 2 or 3 × 3.

Furthermore, the resolution of the image sensor depends on the size of the pixel for one filter color. The lengths b1, b2, and b3 of one side of one pixel have a relationship of b1> b2> b3, and thus the resolution in fig. 5 to 7 is fig. 5< fig. 6< fig. 7.

Next, referring to fig. 8A to 8C, the operation of the ADC in the comparative example of the present embodiment will be described, the pixel array 200 shown in fig. 8A includes pixel blocks 212 of three filter colors, the pixel block of one filter color includes 2 × 2 or 4 pixels 214, each pixel includes four PDs in one pd.gr pixel block 212 shares one FD. -FD with a capacitance Cfd through the TGs 1 to TG4 and can collectively convert charges supplied from the four PDs sharing the FD into a voltage, the FD of the Gr and the FD of the B pixel block 212 are connected to a source follower circuit SFC including an AMP and to the ADC through a metal signal line Vsig, one read channel for each ADC, and the pixel array 200 can read signals through two read channels ch.1 and ch.2, respectively.

Fig. 8B shows the signal read in the ADC step. The ADC treats the process of all ADC circuits from the start of processing to the end of processing as one step. In fig. 8B, each row corresponds to one ADC step, and the number of ADC steps is 2. Fig. 8C is a pulse timing diagram of the control signal. ADC step 1(AD1) starts with the pulse rise of the reset signal at time t2 and ends with the next pulse fall. During this time period, the charge of Gr is read through the read channel ch.1 and the charge of R is read through the read channel ch.2. Then, the ADC step 2(AD2) starts at the end of the AD1 period and ends when the select signal VSL _ n falls. During this time period, the charge of B is read through the read channel ch.1, and the charge of Gb is read through the read channel ch.2.

Fig. 9A shows an example where the pixel block of one filter color comprises a pixel array of 3 × 3 pixels, see the Gr pixel block in the pixel array 900, the PDs connected to the TG1, TG2, TG4 and TG5 share fd1 and, further, the PDs connected to the TG3 and TG6 share fd3 and, further, the PDs connected to the TG7 and TG8 share fd2 and the PDs connected to the TG9 share fd4 and the PDs connected to the TG of another filter color share the FD2 to fd4 and, further, the FD1 and FD2 are connected to the ADC of the read channel ch.1 through a source follower circuit SFC.

Fig. 9B shows an ADC step in the pixel array shown in fig. 9A and signals read in the ADC step. One read channel can process one color in a single ADC step and only process the output of one source follower circuit SFC. Performing ADC processing on blocks of three colors of pixels in the pixel array 900 requires 6 ADC steps, namely AD 1-AD 6.

Thus, when the number of pixels included in the pixel block is increased from 2 × 2 shown in FIG. 8 to 3 × 3 shown in FIG. 9, the number of ADC steps is increased by three times.

For a pixel block including 2 × 2 pixels shown in fig. 8, the charges provided by the pixel block are added to the charge domain for the ADC, while in the example shown in fig. 9, the charges of the pixel block are distributed to different read channels or different ADC steps, for example, the signal of the Gr pixel block is separated into Gr1 and Gr2, the signal of the B pixel block is separated into B1 to B4, and these signals are added to the digital domain by colors, and thus, the pixel block including 3 × 3 pixels increases the noise by 1.4 to 2 times as compared with the pixel block including 2 × 2 pixels.

Fig. 10A is a diagram showing a configuration of a signal reading side of a pixel array provided by a first embodiment of the present invention, in fig. 10A and the following description, similar or identical reference symbols are provided for similar or identical elements as in fig. 8A and 9A to avoid redundant description, the image sensor includes a pixel array 1000 including pixel blocks of each of filter colors Gr, R, B, and Gb, each having Pixels (PDs) arranged in a3 × 3 matrix form, one PD being provided for each of the pixels.

Referring to the Gr pixel block in the pixel array 1000, three PDs connected to the TG1, TG4, and TG5 share the FD 2. The FD1 is shared by two PDs connected to the TG2 and TG 3. The FD3 is shared by two PDs connected to the TG6 and TG 9. The FD4 is shared by two PDs connected to the TG7 and TG 8. The FD1 to FD4 are connected to the ADC of the read channel ch.1 through a source follower circuit SFC.

As described above, according to the signal reading configuration of the pixel array of the present embodiment, each Pixel (PD) in the pixel block corresponding to one filter color is connected to one ADC through the associated FD shared by each pixel. Accordingly, the AD conversion can be performed in a single step on the signals of all PDs in the pixel block.

Fig. 10B shows the ADC steps in the pixel array shown in fig. 10A and the signals read in the ADC steps, performing ADC processing on three color pixel blocks in the pixel array 1000 requires 2 ADC steps, i.e. AD1 and AD2, and therefore the signals read in the ADC steps are the same as in the case of 2 × 2 pixels.

Fig. 11A is a diagram showing a lens portion 1100 superimposed on the pixel array 1000 in fig. 10, and fig. 11B is a cross-sectional view along a horizontal direction arrow XIB in fig. 11A. In fig. 11B, light enters the lens portion 1100 from the lower side, and enters PDs constituting the pixel array 1000 via the color filter 1110. The lens portion 1100 includes on-chip lenses 1102 formed based on the size of the pixels in the pixel array 1000.

Example 2

In the present invention, a plurality of FDs shared only by pixels in a pixel block of one filter color are provided for the pixel block to realize signal reading in one ADC step. The following embodiments show examples of pixel layouts. Fig. 12 shows a configuration of a signal reading side of a pixel array provided by another embodiment of the present invention. Referring to the Gr pixel block in the pixel array 1200, the six PDs connected to the TGs 1 to TG6 share the FD 1. The three PDs connected to the TG7 to TG9 share the FD 2. The FD1 and FD2 are connected to the ADC of the read channel ch.1 via a source follower circuit SFC.

Example 3

Fig. 13 shows a configuration of a signal reading side of a pixel array provided by another embodiment of the present invention. Referring to the Gr pixel block in the pixel array 1300, the three PDs connected to the TGs 1 to TG3 share the FD 1. The four PDs connected to the TG4, TG5, TG7, and TG8 share the FD 2. The FD3 is shared by two PDs connected to the TG6 and TG 9. The FD1 to FD3 are connected to the ADC of the read channel ch.1 through a source follower circuit SFC.

Example 4

Fig. 14 shows a configuration of a signal reading side of a pixel array provided by another embodiment of the present invention. Referring to the Gr pixel block in the pixel array 1400, the three PDs connected to the TG1, TG2, and TG4 share the FD 1. The three PDs connected to the TG3, TG5, and TG6 share the FD 1. The three PDs connected to the TG7 to TG9 share the FD 3. The FD1 to FD3 are connected to the ADC of the read channel ch.1 through a source follower circuit SFC.

Example 5

Fig. 15 shows a color filter array on the light receiving side of a pixel array according to another embodiment of the present invention. Referring to the Gr pixel block 1502 in the pixel array 1500, the pixel block includes three rows of pixels, i.e., the above-described three pixels, two pixels, and three pixels, for a total of eight pixels 1403 arranged horizontally.

Fig. 16 is a diagram showing a lens portion superimposed on the pixel array in fig. 15. The lens portion 1600 includes a square on-chip lens 1602 and a rectangular on-chip lens 1603 that are formed based on the size of the pixels in the pixel array 1500.

Fig. 17A shows the configuration of the signal reading side of the pixel array provided by the present embodiment the image sensor includes a pixel array 1700 including pixel blocks of each of the filter colors Gr, R, B, and Gb, each having Pixels (PD) arranged in a3 × 3 matrix form, one photodiode being provided for each of the pixels in the pixel blocks 1702.

The photodiodes corresponding to the two

pixels

1706 and 1707 adjacent to the FD share the FD. Further, the photodiode connected to the FD includes photodiodes corresponding to six

pixels

1703, 1704, 1705, 1708, 1709, and 1711 provided separately from the FD.

Fig. 17B is a cross-sectional view taken along a vertical direction arrow XVIIB in fig. 17A, and fig. 17C is a cross-sectional view taken along a horizontal direction arrow XVIIC in fig. 17A. In fig. 17B and 17C, light enters the lens portion 1600 from the lower side in the figure, and enters PDs constituting the pixel array 1700 via the color filter 1710. Referring to the Gr pixel block in the pixel array 1700 shown in fig. 17A, the photodiodes connected to the TGs 1 to TG9 share the FD. The FD is connected to the ADC of the read channel ch.1 via a source follower circuit SFC.

According to the signal reading configuration of the pixel array of the present embodiment, each Pixel (PD) in the pixel block corresponding to one filter color is connected to one ADC through the associated FD shared by each pixel. Further, the PD connected to the FD includes PDs corresponding to pixels arranged separately from the FD. This allows performing AD conversion on the signals of all PDs in the pixel block in a single step.

According to the present embodiment, eight photodiodes share one FD. and therefore, the capacitance of the FD can be small compared to that of the 3 × 3 pixel, and thus, noise generated by signal reading can be made smaller.

Example 6

Fig. 18 shows a color filter array on the light receiving side of a pixel array according to another embodiment of the present invention. In the pixel array 1800 shown in fig. 18, a Gr pixel block 1802 includes four

pentagonal pixels

1804, 1806, 1807, and 1809 adjacent to an FD. Further, the pixel block 1802 includes four

square pixels

1803, 1805, 1808, and 1811 provided separately from the FD.

Fig. 19A is a diagram showing a lens portion superimposed on the pixel array shown in fig. 18. A lens portion 1900 comprising an array of square on-chip lenses 1902 is superimposed on a block 1800 of pixels shown in fig. 19A, wherein the size of the square on-chip lenses 1902 is 1/9 of the block of pixels.

Fig. 19B shows a cross section along the horizontal direction arrow XIXB in fig. 19A. In fig. 19B, light enters the lens portion 1900 from the lower side in the figure and enters PDs constituting the pixel array 1800 via the color filter 1910.

The pixel block 1802 includes four

adjacent pixels

1804, 1806, 1807, and 1809. The pixel block 1802 further includes four

pixels

1803, 1805, 1808, and 1811 which are separately provided.

Example 7

FIG. 20 illustrates a color filter array provided by an embodiment. In the pixel array 2000, the Gr pixel block 2002 includes eight rectangular pixels 1903 whose longitudinal direction is the vertical direction.

Fig. 21A is a diagram showing a lens portion superimposed on the pixel array shown in fig. 20. A lens portion 2100 comprising an array of square on-chip lenses 2102 is superimposed over the pixel array 2002, wherein the size of the square on-chip lenses 2102 is 1/8 of the pixel block. Note that the lens portion 2100 is disposed at an inclination angle θ with respect to the pixel array 2000.

Fig. 21B is a sectional view along a horizontal direction arrow XXIB in fig. 21A, and fig. 21C is a sectional view along a vertical direction arrow XXIC in fig. 21A. In fig. 21B, light enters the lens portion 2100 from the lower side and enters PDs constituting the pixel array 2000 via the color filter 1110. That is, light entering the on-chip lenses 2102_1 to 2102_8 enters the PDs 2003_1 to 2003_8, respectively.

In the pixel array 2000, the longitudinal direction of the pixels 2003 is the vertical direction, so that the resolution in the vertical direction is lower than the resolution in the horizontal direction. However, since the lens portion 2100 including the square on-chip lens 2102 is disposed at an inclination angle θ with respect to the pixel array 2000, light can be uniformly sampled by dividing a light area into square areas. From the viewpoint of uniform sampling, the angle θ is preferably set to 45 degrees. Therefore, the influence of the difference between the resolution in the horizontal direction and the resolution in the vertical direction of the output image can be reduced.

Fig. 22 shows the configuration of the signal reading side of the pixel array provided by the present embodiment. Referring to the Gr pixel block in the pixel array 2000, the PDs connected to the TG1, TG2, TG5, and TG6 share the FD 1. PDs connected to the TG3, TG4, TG7, and TG8 share the FD 2. The FD1 and FD2 are connected to the ADC of the read channel ch.1 via a source follower circuit SFC.

Example 8

The following embodiments describe aspects of the lens portions superimposed on the pixel array.

Fig. 23A shows a lens portion superimposed on the pixel array shown in fig. 10 to 14, and fig. 23B shows a cross section along a vertical direction arrow XXIIIB in fig. 23A. As shown in fig. 23A and 23B, light enters the lens portion 2300 and enters PDs constituting the pixel array 1000 via the color filter 2310.

In the lens section 2300, the lens section 2300 provided for the Gr pixel block is composed of a combination of rectangular on-chip lenses 2304 superimposed on horizontally adjacent two pixels, square on-chip lenses 2305 having the same size as the pixels, and on-chip lenses 2306 superimposed on vertically adjacent two pixels.

The pixel overlapping the on-chip lens 2304 is composed of two PDs, and can be used for imaging and phase difference Autofocus (AF). Fig. 24A and 24B are diagrams illustrating an operation of the phase difference AF. When horizontally adjacent PDs operate as phase difference AF sensors, light fluxes entering from the imaging lens are received by the two PDs shown in fig. 24A and 24B, respectively. For example, the AF controller 118 in fig. 1 detects signals from the two PDs and measures a deviation of the focus based on the interval between two images formed on the image sensor. Then, the optical system is controlled to be focused according to the measured deviation. On the other hand, at the time of imaging, adjacent PDs are combined with other PDs in the pixel block to form a pixel of one color.

In the example shown in fig. 23A, the on-chip lenses 2304 may be used to detect a phase difference in the horizontal direction, and the on-chip lenses 2306 may be used to detect a phase difference in the vertical direction.

Example 9

Fig. 25 shows a lens portion superimposed on the pixel array shown in fig. 10 to 14.

In the lens portion 2500, a portion corresponding to a GR pixel block is constituted by a combination of a rectangular on-chip lens 2502 superimposed on 2 × 2 or 4 pixels and a square on-chip lens 2503 having the same size as the pixels.

The pixel on which the on-chip lens 2502 is superimposed is composed of four PDs, and can be used for imaging and phase difference Autofocus (AF). When horizontally adjacent PDs operate as phase difference AF sensors, light fluxes entering from the imaging lens are received by the two PDs shown in fig. 24A and 24B, respectively. For example, the AF controller 118 in fig. 1 detects signals from the two PDs and measures a deviation of the focus based on the interval between two images formed on the image sensor. Then, the optical system is controlled to be focused according to the measured deviation. Two PDs vertically adjacent are also used for phase difference AF control. On the other hand, at the time of imaging, adjacent PDs are combined with other PDs in the pixel block to form a pixel of one color.

Example 10

Fig. 26A is a diagram showing a lens portion superimposed on the pixel array 2000 shown in fig. 20. A lens portion 2600 containing an array of four on-chip lenses 2603 is superimposed over a block of pixels 2602, wherein the size of the on-chip lenses 2603 is 1/4 of the block of pixels.

Fig. 26B shows a cross section along the horizontal direction arrow XXVIB in fig. 26A. As shown in fig. 26A and 26B, light enters the lens portion 2600, and enters PDs constituting the pixel array 2000 via a color filter 2610.

In the pixel array 2000, the longitudinal direction of the pixels 2003 is the vertical direction, so that the resolution in the vertical direction is lower than the resolution in the horizontal direction. However, superimposing one on-chip lens 2603 on two PDs has an advantage such that these PDs can be used as the phase difference AF sensor as described above. In the example shown in fig. 26A, the combination of the on-chip lens 2603 and two PDs enables detection of a phase difference in the horizontal direction.

Example 11

Fig. 27 is a diagram showing a lens portion superimposed on the pixel array 2000 in fig. 20.

In the lens section 2700, two on-chip lenses 2703 provided for the Gr pixel blocks 2702 are superimposed on 2 × 2 or four pixels the pixels on which the on-chip lenses 2703 are superimposed are composed of four PDs and can be used for imaging and phase difference Autofocus (AF).

In the pixel array 2000, the longitudinal direction of the pixels 2003 is the vertical direction, so that the resolution in the vertical direction is lower than the resolution in the horizontal direction. However, superimposing one on-chip lens 2703 on four PDs has an advantage such that these PDs can be used as the phase difference AF sensor as described above.

Example 12

Fig. 28 shows a color filter array on the light receiving side of a pixel array according to another embodiment of the present invention. In the pixel array 2800, a Gr pixel block 2802 includes eight rectangular pixels 2803 whose longitudinal directions are horizontal directions.

Fig. 29 shows a lens portion 2900 superimposed on the pixel array 2800 shown in fig. 28, and fig. 30 shows an example of a combination of the lens portions 2900 in the pixel array 2800. The lens portion 2900 is formed such that the pixel block 2802 includes four square on-chip lenses 2902.

In the pixel array 2800, the longitudinal direction of the pixels 2803 is the horizontal direction, so that the resolution in the horizontal direction is lower than the resolution in the vertical direction. However, superimposing one on-chip lens 2902 on two PDs has an advantage such that these PDs can be used as the phase difference AF sensor as described above. In the example shown in fig. 30, the combination of the on-chip lens 2902 and two PDs enables detection of a phase difference in the vertical direction.

Example 13

Fig. 31 shows a color filter array on the light receiving side of a pixel array provided by another embodiment of the present invention. In the pixel array 3000, the Gr pixel block 3002 includes four rectangular pixels 3003 whose longitudinal direction is the horizontal direction and four rectangular pixels 3004 whose longitudinal direction is the vertical direction.

Fig. 32 shows an example of a combination of the lens portions 2900 shown in fig. 29 in the color filter array shown in fig. 30. The lens portion 2900 is formed such that the pixel block 3002 includes four square on-chip lenses 2902.

In the pixel array 3000, the on-chip lens 2902 is superimposed on two pixels 3003 whose longitudinal direction is the horizontal direction, and the on-chip lens 2904 is superimposed on two pixels 3004 whose longitudinal direction is the vertical direction. This has the advantage of allowing the on-chip lens 2902 to function as a phase difference AF sensor as described above. In the example shown in fig. 32, the combination of the on-chip lens 2902 and two PDs enables detection of a phase difference in the vertical direction. In addition, the combination of the on-chip lens 2904 and the two PDs enables detection of a phase difference in the horizontal direction.

Example 14

Fig. 33 shows a combination of a color filter array and a lens portion on the light receiving side of a pixel array provided by another embodiment of the present invention. The lens portion 3300 constitutes the pixel-and-lens portion combination 2600 shown in fig. 26A and the pixel-and-lens portion combination 2900 shown in fig. 30.

Fig. 34A shows a configuration of the signal reading side of the pixel array shown in fig. 33. In the upper left region 3402 of the pixel array 3400, in the Gr pixel block 3406, PDs connected to four TGs share one FD. The two FDs included in the Gr pixel block and the two FDs included in the B pixel block are connected to one ADC of the read channel ch.1 through one source follower circuit SFC. The region 3404 is a configuration example of the signal reading side of the pixel array having the color filter array shown in fig. 28.

Fig. 34B shows a layout example of transistors in the pixel array in fig. 34A. In fig. 34, two FDs included in the Gr pixel block and two FDs included in the B pixel block are connected to the source follower circuit SFC including AMP, SL, and RS provided between the two pixel blocks.

Next, referring to fig. 35, a description is given of a procedure of a signal reading method performed by the image sensor provided in each of the above embodiments. The variable i is initialized to 0 (S3501). Then, the signal charges are read out from the FD of the ith row through each read channel (S3503). In this process, all the FD-stored signal charges contained in the pixel block of one filter color are supplied to the vertical signal line through the SFC circuit. Then, ADC is performed on the read signal (S3504). Next, i +1 is set to i (S3505). The processing of steps S3503 to S3505 is repeatedly performed by the number of lines N of the pixel block (S3502 to S3506).

Although the signals of the same row of pixels are read through all the read channels in the foregoing process, the rows from which the pixel signals are read may be different for different read channels. For example, the signals of the pixels can be read in the following manner: the read channel ch.1 reads signals from the pixels of row n, the read channel ch.2 reads signals from the pixels of row n +1, and so on.

Other embodiments

Although the above embodiment has been described taking an RGB layout as an example, the present invention can be applied to other color layouts, such as black and white.

In addition, the pixel array according to an embodiment may be combined with an on-chip lens according to another embodiment. For example, a lens portion 2100 comprising an array of square on-chip lenses 2102 may be superimposed on the pixel array shown in any of embodiments 8 to 13, wherein the size of the square lens portion 2100 is 1/8 of the pixel block in fig. 21A. At this time, the lens portion 2100 may be disposed at a tilt angle θ with respect to the pixel array 2000.

The above description is only a specific embodiment of the present invention and is not intended to limit the scope of the present invention. Any modifications or substitutions that can be easily found by those skilled in the art within the technical scope of the present invention should fall within the protective scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An image sensor, comprising:

a plurality of pixel blocks each corresponding to one of the filter colors and including a plurality of photoelectric conversion elements corresponding to pixels constituting the pixel block, respectively;

a plurality of charge/voltage converters, any one of which is configured to convert charges output by a plurality of photoelectric conversion elements included in each of two adjacent pixel blocks of the plurality of pixel blocks into voltages at different times, the two adjacent pixel blocks being connected to different pulse signal lines and connected to a same data line, and before the two adjacent pixel blocks output the charges, a reset time is provided to the charge/voltage converters respectively corresponding to the two adjacent pixel blocks at different times;

2. The image sensor of claim 1,

the plurality of pixel blocks are arranged in a matrix form.

3. The image sensor according to claim 1 or 2,

the charge/voltage converter converts only the charge output from the photoelectric conversion element in one pixel block into a voltage.

4. The image sensor of claim 3,

the pixel block includes pixels arranged in a3 × 3 matrix form.

5. The image sensor of claim 4,

the plurality of charge/voltage converters include at least a first charge/voltage converter shared by two of the photoelectric conversion elements and a second charge/voltage converter shared by three of the photoelectric conversion elements.

6. The image sensor of claim 4,

the plurality of charge/voltage converters include a first charge/voltage converter shared by three of the photoelectric conversion elements and a second charge/voltage converter shared by six of the photoelectric conversion elements.

7. The image sensor of claim 4,

the plurality of charge/voltage converters include a first charge/voltage converter shared by two of the photoelectric conversion elements, a second charge/voltage converter shared by three of the photoelectric conversion elements, and a third charge/voltage converter shared by four of the photoelectric conversion elements.

8. The image sensor of claim 4,

the plurality of charge/voltage converters includes three charge/voltage converters, wherein each charge/voltage converter is shared by three of the photoelectric conversion elements.

9. The image sensor of claim 3,

the pixel block includes pixels arranged in a matrix of 2 × 4.

10. The image sensor of claim 9,

the plurality of charge/voltage converters includes two charge/voltage converters shared by four of the photoelectric conversion elements.

11. The image sensor of claim 9,

the pixel block includes eight pixels, and the longitudinal direction thereof is a horizontal direction or a vertical direction.

12. The image sensor of claim 9,

an array of lenses sized 1/8 pixel blocks is superimposed over the pixel blocks, wherein the lenses are disposed at a predetermined angle θ to the pixels.

13. The image sensor of claim 12,

the predetermined angle θ is 45 degrees.

14. The image sensor of claim 4,

a lens is superimposed on two or four adjacent pixels comprised by said block of pixels.

15. An image sensor, comprising:

at least one charge-to-voltage converter, any one of the charge-to-voltage converters being configured to convert charges output by a plurality of photoelectric conversion elements included in each of two adjacent pixel blocks of the plurality of pixel blocks into voltages at different times, the two adjacent pixel blocks being connected to different pulse signal lines and connected to a same data line, and before the two adjacent pixel blocks output the charges, providing a reset time to the charge-to-voltage converter respectively corresponding to the two adjacent pixel blocks at different times;

16. The image sensor of claim 15,

the plurality of pixel blocks are arranged in a matrix form.

17. The image sensor of claim 15 or 16,

the at least one charge/voltage converter converts only the charge output from the photoelectric conversion element included in one pixel block into a voltage.

18. The image sensor of claim 17,

the at least one charge/voltage converter is shared by only the photoelectric conversion elements included in one pixel block.

19. The image sensor of claim 18,

the pixel block comprises an array of eight pixels.

20. The image sensor of claim 19,

each row of the pixel block comprises three pixels, two pixels and three pixels.

21. The image sensor of claim 19,

the pixel block includes four pixels adjacent to each other and four pixels arranged separately.

22. The image sensor of claim 15,

an array of lenses of size 1/9 pixel blocks is superimposed on the pixel blocks.

23. An image sensor, comprising:

a plurality of pixel blocks each corresponding to one of the filter colors and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, the pixel block includes eight pixels, and a longitudinal direction thereof is a horizontal direction or a vertical direction;

and any one of the charge-to-voltage converters is configured to convert charges output by the plurality of photoelectric conversion elements included in each of two adjacent pixel blocks of the plurality of pixel blocks into voltages at different times, the two adjacent pixel blocks are connected to different pulse signal lines and connected to the same data line, and before the two adjacent pixel blocks output the charges, a reset time is provided to the charge-to-voltage converters respectively corresponding to the two adjacent pixel blocks at different times.

24. The image sensor of claim 23,

the pixel block includes pixels arranged in a matrix of 2 × 4.

25. The image sensor of claim 24, wherein the image sensor comprises a plurality of pixel blocks, wherein one of the pixel blocks comprises eight pixels with a vertical direction being a horizontal direction, and another of the pixel blocks comprises eight pixels with a vertical direction being a vertical direction.

26. The image sensor of any one of claims 23 to 25,

27. The image sensor of claim 26,

the predetermined angle θ is 45 degrees.

28. The image sensor of any one of claims 23 to 25,

29. An image sensor, comprising:

the pixel module comprises a plurality of pixel blocks, a color filter;

30. An image sensor, comprising:

a plurality of pixel blocks each corresponding to one of the filter colors and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, and the pixel block includes four adjacent pixels and four pixels arranged separately;

31. An image sensor, comprising:

the pixel structure comprises a plurality of pixel blocks, a plurality of charge/voltage converters, a plurality of reset time control units and a plurality of charge/voltage converters, wherein each pixel block corresponds to a filtering color and comprises a plurality of photoelectric conversion elements, the plurality of photoelectric conversion elements respectively correspond to pixels forming the pixel block, the pixel block comprises pixels arranged in a3 × 3 matrix form, any one charge/voltage converter is used for converting charges output by the plurality of photoelectric conversion elements contained in each two adjacent pixel blocks in the plurality of pixel blocks into voltages at different times, the two adjacent pixel blocks are connected to different pulse signal lines and are connected to the same data line, and before the charges are output by the two adjacent pixel blocks, a reset time is respectively provided to the charge/voltage converters corresponding to the two adjacent pixel blocks at the same time.

32. The image sensor of claim 31,

33. A signal reading method of an image sensor, the image sensor comprising:

a signal converter connected to the plurality of charge/voltage converters to convert voltage signals output from the plurality of charge/voltage converters included in each pixel block;

wherein each pixel in the block of pixels corresponding to the one filter color is connected to the signal converter via an associated one of the plurality of charge-to-voltage converters,

wherein the associated charge-to-voltage converter is shared by each pixel; the method comprises the following steps:

34. A signal reading method of an image sensor, the image sensor comprising:

a plurality of pixel blocks each corresponding to one of the filter colors and including a plurality of photoelectric conversion elements corresponding to pixels constituting the pixel block;

the signal converter is connected with the at least one charge/voltage converter to convert the voltage signal output by the at least one charge/voltage converter contained in each pixel block; wherein each pixel in the pixel block corresponding to the one filter color is connected to the signal converter via the at least one charge-to-voltage converter, wherein the at least one charge-to-voltage converter is shared by each pixel, and the photoelectric conversion element connected to the at least one charge-to-voltage converter includes a photoelectric conversion element corresponding to a pixel arranged separately from the at least one charge-to-voltage converter; the method comprises the following steps:

providing voltage signals output by at least one charge/voltage converter contained in the first pixel block to the signal converter in common; and providing the voltage signals output by at least one charge/voltage converter contained in the second pixel block to the signal converter in a common mode.

35. A signal reading method of an image sensor, the image sensor comprising:

the method comprises the following steps:

36. A signal reading method of an image sensor, the image sensor comprising: the pixel module comprises a plurality of pixel blocks, a color filter; a plurality of charge/voltage converters, any one of which is configured to convert charges output by a plurality of photoelectric conversion elements included in each of two adjacent pixel blocks of the plurality of pixel blocks into voltages at different times, the two adjacent pixel blocks being connected to different pulse signal lines and connected to a same data line, and before the two adjacent pixel blocks output the charges, a reset time is provided to the charge/voltage converters respectively corresponding to the two adjacent pixel blocks at different times;

the method comprises the following steps:

37. A signal reading method of an image sensor, the image sensor comprising: a plurality of pixel blocks each corresponding to one of the filter colors and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel block, and the pixel block includes four adjacent pixels and four pixels arranged separately;

the method comprises the following steps:

38. A signal reading method of an image sensor is characterized in that the image sensor includes a plurality of pixel blocks each corresponding to a filter color and including a plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements respectively correspond to pixels constituting the pixel blocks, and the pixel blocks include pixels arranged in a3 × 3 matrix form;

the method comprises the following steps: