JP2017076872A - Imaging element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging element whose area can be reduced.SOLUTION: An imaging element is configured by laminating at least a first semiconductor substrate 100, a second semiconductor substrate 101, and a third semiconductor substrate 102. The second semiconductor substrate 101 is provided between the first semiconductor substrate 100 and the third semiconductor substrate 102. The first semiconductor substrate 100 has a plurality of pixels 200 each outputting a pixel signal by photoelectric conversion. The plurality of pixels have pixels of a first pixel group and pixels of a second pixel group. The second semiconductor substrate has a first signal processing circuit 303 for processing signals from the pixels of the first pixel group. The third semiconductor substrate 102 has a second signal processing circuit 306 for processing signals from the pixels of the second pixel group.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an image sensor.

  Many digital cameras, digital video cameras, and mobile phones with camera functions that use CMOS image sensors as image sensors have been developed. In general, a mobile phone with a camera function has a small size of an image pickup element used for a digital camera and a digital video camera. For example, an image sensor mounted on a mobile phone with a camera function is a 1/3 type (4.8 mm × 3.6 mm), and an image sensor mounted on a digital camera is a full size (36 mm × 24 mm). . In that case, when comparing the areas of the image sensors, the 1/3 type is about 2% of the full size.

  Comparing the number of pixels of a mobile phone with a camera function and a digital camera that have become widespread in recent years, the mobile phone with a camera function is about 10 million pixels, and the digital camera is about 25 million pixels. This is smaller than the difference in the area of the image sensor. In terms of the area per pixel, the area per pixel of the 1/3 type imaging device is about 1/20 compared to the full size.

  On the other hand, from the viewpoint of speeding up, proposals have been made to configure the number of signal processing circuits corresponding to the number of pixels with respect to the image sensor in which the number of signal processing circuits corresponding to the pixel array is configured. In addition, as a configuration of an imaging element using a CMOS in recent years, a stacked imaging element in which an analog part and a logic part are stacked for each layer is realized.

  For example, Patent Document 1 discloses a technique in which a light receiving layer including a plurality of pixels including a photodiode and a signal processing layer including a signal processing circuit that processes a pixel signal are stacked. . High functionality by reducing the chip area and relieving the restrictions on the layout of the logic part by configuring the light receiving part and the signal processing circuit, which were conventionally configured in one layer, in separate layers. There is merit such as. In particular, it is useful for a small-sized image pickup element employed in a mobile phone with a camera function.

JP 2014-179678 A

  However, in the case of a configuration in which a signal processing circuit corresponding to the number of pixels is provided in the stacked structure disclosed in Patent Document 1 described above, the following concerns are raised. In the laminated structure disclosed in Patent Document 1 described above, a signal output from the light receiving layer is input to one signal processing layer and subjected to signal processing. That is, it is necessary to configure the number of signal processing circuits corresponding to the number of pixels in one layer. If this configuration is to be realized with a small image sensor, the area per signal pixel is small and the area of the signal processing circuit is larger than the pixel area. Therefore, there is a concern that the area of the entire image sensor increases. On the other hand, since an apparatus on which a small image sensor represented by a mobile phone is mounted is desired to be downsized, it is not preferable to increase the area of the image sensor.

  An object of the present invention is to provide an imaging device capable of reducing the area.

  The imaging device of the present invention is an imaging device in which at least a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are stacked, and the second semiconductor substrate includes the first semiconductor substrate and the first semiconductor substrate. The first semiconductor substrate includes a plurality of pixels that output a pixel signal by photoelectric conversion, and the plurality of pixels includes a pixel of the first pixel group and the third semiconductor substrate. The second semiconductor substrate includes pixels of a second pixel group, the second semiconductor substrate includes a first signal processing circuit that processes signals of the pixels of the first pixel group, and the third semiconductor substrate includes: It has a 2nd signal processing circuit which processes a signal of a pixel of the 2nd pixel group.

  According to the present invention, the area can be reduced.

It is sectional drawing which shows the structural example of the image pick-up element by 1st Embodiment. It is a circuit diagram showing an example of composition of an image sensor by a 1st embodiment. It is a figure which shows the structural example of the image pick-up element by 1st Embodiment. It is a figure which shows the structural example of the image pick-up element by 1st Embodiment. It is a figure which shows the other structural example of the image pick-up element by 1st Embodiment. It is a graph for demonstrating the influence of the transmission path length by 2nd Embodiment. It is a figure which shows the example of a current setting of the constant current source by 2nd Embodiment. It is explanatory drawing of the pupil division type image pick-up element by 3rd Embodiment. It is a circuit diagram which shows the structural example of the image pick-up element by 3rd Embodiment. It is a figure which shows the structural example of the image pick-up element by 3rd Embodiment. It is a figure which shows the structural example of the image pick-up element by 4th Embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a cross-sectional structure of a backside illumination type imaging device according to the first embodiment of the present invention. The imaging element has a structure in which a light receiving layer 100, a first signal processing layer 101, a second signal processing layer 102, a third signal processing layer 103, and a fourth signal processing layer 104 are stacked in order from above. It is. The light receiving layer 100 is a first semiconductor substrate, the first signal processing layer 101 is a second semiconductor substrate, the second signal processing layer 102 is a third semiconductor substrate, and a third signal processing layer. Reference numeral 103 denotes a fourth semiconductor substrate, and the fourth signal processing layer 104 is a fifth semiconductor substrate. The light receiving layer 100 has a plurality of pixels arranged in a matrix in the row direction and the column direction, and FIG. 2 shows two pixels. The light receiving layer 100 includes, in order from the top, a microlens 121, a color filter 120, a semiconductor substrate 110, a first conductivity type region 111, and an interlayer film 119 between the multilayer wiring layers 118. As shown in FIG. 3, the color filter 120 of each pixel is configured by a Bayer array of R (red), G (green), and B (blue). Here, a pixel having the R color filter 120 is referred to as an R pixel, a pixel having the G color filter 120 is referred to as a G pixel, and a pixel having the B color filter 120 is referred to as a B pixel. Further, the G pixel adjacent to the R pixel in the horizontal direction is referred to as G1 pixel, and the G pixel adjacent to the B pixel in the horizontal direction is referred to as G2 pixel. The G1 pixel group is a first pixel group, the G2 pixel group is a second pixel group, the R pixel group is a third pixel group, and the B pixel group is a fourth pixel group.

  In addition to the first conductivity type region 111, the light receiving layer 100 includes a photodiode 112 and a first conductivity type region 113 for suppressing dark current of the photodiode 112. The light receiving layer 100 includes a floating diffusion (FD) 114, a transfer MOS transistor 115, and an amplification MOS transistor 116. In addition, the light receiving layer 100 includes the reset MOS transistor 201 and the selection MOS transistor 202 shown in FIG. The configuration and driving method of this pixel will be described later. Further, the light receiving layer 100 includes an element isolation region 117, a wiring layer 118 formed in a multilayer, and an interlayer film 119 between the multilayer wiring layers 118.

  The light receiving layer 100 and the first to fourth signal processing layers 101 to 104 are electrically connected by a signal transmission line 122, a micro bump 123, and the like. This connection point is connected at a point for transmitting a pixel signal provided in the light receiving layer 100. In addition, wirings for supplying power and the like are connected by micro bumps or the like.

  The G1 pixel in the light receiving layer 100 is directly connected to the first signal processing layer 101. On the other hand, the R pixel in the light receiving layer 100 is connected to the third signal processing layer 103 via the first signal processing layer 101 and the second signal processing layer 102. At this time, the R pixel is connected to the first signal processing layer 101 and the second signal processing layer 102 as a signal transmission path through the first signal processing layer 101 and the second signal processing layer 102. Only. R pixel signal processing is performed in the third signal processing layer 103. The G2 pixel in the light receiving layer 100 is connected to the second signal processing layer 102 via the first signal processing layer 101 as shown in FIG. The B pixel in the light receiving layer 100 is connected to the fourth signal processing layer 104 via the first to third signal processing layers 101 to 103.

  In the present embodiment, the back-illuminated type light-receiving layer 100 is illustrated, but the back-illuminated type may be used instead of the back-illuminated type.

  FIG. 2 is a diagram illustrating a configuration example of the image sensor according to the present embodiment, and the same components as those illustrated in FIG. 1 are denoted by the same reference numerals. The pixel 200 includes a photodiode 112, an FD 114, a transfer MOS transistor 115, an amplification MOS transistor 116, a reset MOS transistor 201, a selection MOS transistor 202, and a constant current source 203, and outputs a pixel signal by photoelectric conversion. The transfer MOS transistor 115, the reset MOS transistor 201, and the selection MOS transistor 202 function as switches and are driven by control pulses PTX, PRES, and PSEL supplied from a pixel control circuit 302 (FIG. 3), which will be described later.

  The photodiode 112 is a photoelectric conversion unit that converts incident light into electric charges. The photodiode 112 has an anode connected to the ground line and a cathode connected to the source of the transfer MOS transistor 115. The transfer MOS transistor 115 is driven by a control pulse PTX input to its gate, and transfers the charge converted by the photodiode 112 to the FD 114. The FD 114 is a charge-voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into a voltage.

  The amplification MOS transistor 116 functions as a source follower, and a voltage that has been subjected to charge-voltage conversion by the FD 114 is input to its gate. The amplification MOS transistor 116 has a drain connected to the power supply line VDD that supplies a constant potential, and a source connected to the selection MOS transistor 202. The selection MOS transistor 202 is driven by a selection pulse PSEL input to its gate, its drain is connected to the amplification MOS transistor 116, and its source is connected to the constant current source 203. When the selection pulse PSEL becomes active level (high level), the selection MOS transistor 202 becomes conductive, the amplification MOS transistor 116 operates as a source follower amplifier, and the output of the amplification MOS transistor 116 is connected to the AD conversion circuit 205. . The amplification MOS transistor 116 outputs a pixel signal having a voltage corresponding to the voltage of the FD 114 to the AD conversion circuit 205.

  The reset MOS transistor 201 has a drain connected to the power supply line VDD and a source connected to the FD 114. The reset MOS transistor 201 is driven by a reset pulse PRES input to its gate, and resets (removes) charges accumulated in the FD 114.

  The pixel 200 resets the FD 114 and outputs a signal when the reset is canceled as an N signal. Thereafter, the transfer MOS transistor 115 is in a non-conductive state, and the photodiode 112 converts light into electric charge and accumulates the electric charge during the electric charge accumulation period. After the end of the charge accumulation period, the transfer MOS transistor 115 becomes conductive, and the pixel 200 outputs a signal based on photoelectric conversion as an S signal.

  The plurality of circuit groups 204 are connected to the plurality of pixels 200, respectively, and process N signals and S signals output from the plurality of pixels 200. Each of the plurality of circuit groups 204 includes an AD (analog / digital) conversion circuit 205, an S-N circuit 206, a memory circuit 207, and an output circuit 208. The AD conversion circuit 205 includes a comparator and a counter, and converts the output signal of the pixel 200 from analog to digital. Specifically, the AD conversion circuit 205 converts the N signal output from the pixel 200 from analog to digital, and then converts the S signal output from the pixel 200 from analog to digital. The SN circuit 206 calculates a difference between the S signal and the N signal output from the AD conversion circuit 205, and outputs a signal obtained by removing the N signal from the S signal. The memory circuit 207 holds a signal output from the SN circuit 206. The output circuit 208 outputs a signal held by the memory circuit 207 to the outside. Here, the AD conversion circuit 205, the SN circuit 206, and the memory circuit 207 are signal processing circuits.

  FIG. 3 is a diagram illustrating a configuration example of the image sensor according to the present embodiment. FIG. 4 is a diagram illustrating a stacked structure of the image sensor according to the present embodiment. The same components as those illustrated in FIG. Is attached. The imaging element includes a light receiving layer 100, a first signal processing layer 101, a second signal processing layer 102, a third signal processing layer 103, and a fourth signal processing layer 104. The first signal processing layer 101 performs signal processing of the first pixel group (G1 pixel group). The second signal processing layer 102 performs signal processing of the second pixel group (G2 pixel group). The third signal processing layer 103 performs signal processing of the third pixel group (R pixel group). The fourth signal processing layer 104 performs signal processing of the fourth pixel group (B pixel group). As described in FIG. 1, the light receiving layer 100, the first signal processing layer 101, the second signal processing layer 102, the third signal processing layer 103, and the fourth signal processing layer 104 overlap in order from the top. Are stacked.

  The light receiving layer 100 includes a pixel portion 301 and a pixel control circuit 302. The pixel unit 301 includes a plurality of pixels 200 arranged in a matrix. The plurality of pixels 200 include a pixel of the first pixel group (G1 pixel group), a pixel of the second pixel group (G2 pixel group), a pixel of the third pixel group (R pixel group), and a fourth pixel group. It has (B pixel group) pixels. The plurality of pixels 200 are provided with color filters 120 having a Bayer array of red, green, and blue. The pixels of the first pixel group (G1 pixel group) are pixels provided with the color filter 120 of the first color (green). The pixels of the second pixel group (G2 pixel group) are pixels provided with the first color (green) color filter 120. The pixels of the third pixel group (R pixel group) are pixels provided with a color filter 120 of a second color (red) different from the first color. The pixels of the fourth pixel group (B pixel group) are pixels provided with a color filter 120 of a third color (blue) different from the first and second colors. The pixel unit 301 is controlled by control pulses PTX, PRES, and PSEL supplied from the pixel control circuit 302, and outputs the N signal and the S number to any one of the first to fourth signal processing layers 101 to 104 for each pixel 200. Output.

  The first signal processing layer 101 includes a first signal processing circuit 303, a first signal processing control circuit 304, and a first output circuit 305. The first signal processing circuit 303 includes a set of the AD conversion circuit 205, the SN circuit 206, and the memory circuit 207 of FIG. 2 for the number of G1 pixels, and the first pixel group (G1 pixel group) of the light receiving layer 100. ) To process signals of the pixels of the first pixel group (G1 pixel group). The first output circuit 305 includes the output circuit 208 in FIG. 2 as many as the number of G1 pixels, and outputs a signal held in the memory circuit 207 in the first signal processing circuit 303 to the outside. The first signal processing control circuit 304 controls the first signal processing circuit 303 and the first output circuit 305.

  The second signal processing layer 102 includes a second signal processing circuit 306, a second signal processing control circuit 307, and a second output circuit 308. The second signal processing circuit 306 has a combination of the AD conversion circuit 205, the SN circuit 206, and the memory circuit 207 of FIG. 2 by the number of G2 pixels, and the second pixel group (G2 pixel group) of the light receiving layer 100. ) To process signals of the pixels of the second pixel group (G2 pixel group). The second output circuit 308 includes the output circuit 208 in FIG. 2 as many as the number of G2 pixels, and outputs a signal held in the memory circuit 207 in the second signal processing circuit 306 to the outside. The second signal processing control circuit 307 controls the second signal processing circuit 306 and the second output circuit 308.

  The third signal processing layer 103 includes a third signal processing circuit 309, a third signal processing control circuit 310, and a third output circuit 311. The third signal processing circuit 309 includes a combination of the AD conversion circuit 205, the S-N circuit 206, and the memory circuit 207 of FIG. 2 by the number of R pixels, and the third pixel group (R pixel group) of the light receiving layer 100. ) To process signals of pixels of the third pixel group (R pixel group). The third output circuit 311 has the output circuit 208 of FIG. 2 for the number of R pixels, and outputs a signal held in the memory circuit 207 in the third signal processing circuit 309 to the outside. The third signal processing control circuit 310 controls the third signal processing circuit 309 and the third output circuit 311.

  The fourth signal processing layer 104 includes a fourth signal processing circuit 312, a fourth signal processing control circuit 313, and a fourth output circuit 314. The fourth signal processing circuit 312 has a combination of the AD conversion circuit 205, the SN circuit 206, and the memory circuit 207 of FIG. 2 by the number of B pixels, and the fourth pixel group (B pixel group) of the light receiving layer 100. ) To process the signals of the pixels of the fourth pixel group (B pixel group). The fourth output circuit 314 includes the output circuit 208 of FIG. 2 for the number of B pixels, and outputs a signal held in the memory circuit 207 in the fourth signal processing circuit 312 to the outside. The fourth signal processing control circuit 313 controls the fourth signal processing circuit 312 and the fourth output circuit 314.

  The first to fourth output circuits 305, 308, 311 and 314 are not configured in the first to fourth signal processing layers 101 to 104, respectively, and a fifth signal processing layer is provided separately. The first to fourth output circuits 305, 308, 311, and 314 may be configured in the fifth signal processing layer. In that case, the first to fourth signal processing circuits 303, 306, 309, and 312 in the first to fourth signal processing layers 101 to 104 respectively perform the signal processing on the fifth signal processing. The data is output to the first to fifth output circuits 305, 308, 311 and 314 in the layer.

  As described above, the light receiving layer 100 and the first to fourth signal processing layers 101 to 104 are stacked. The signals of the first to fourth pixel groups in the light receiving layer 100 are sent to the first to fourth signal processing circuits 303, 306, 309, and 312 in the first to fourth signal processing layers 101 to 104, respectively. Is output. Here, when attention is paid to the transmission path length when the N signal and the S signal are transmitted from the pixel 200 to the first to fourth signal processing circuits 303, 306, 309, and 312, the imaging element has a laminated structure. The transmission path length differs for each of the first to fourth signal processing layers 101 to 104. Generally, noise varies depending on the length of the transmission path.

  In this embodiment, in consideration of the point that noise is less likely to be mixed as the signal transmission path is shorter, and human visibility, a pixel having a high visibility in a signal processing layer with a short transmission path, that is, with less signal degradation. An example of connecting groups will be described. Green is a color with higher human visibility than red. Red is a color with higher human visibility than blue. The G1 pixel group and the G2 pixel group having the highest visibility are connected to the first and second signal processing layers 101 and 102 having the shortest transmission path, respectively. The R pixel having the next highest visibility is connected to the third signal processing layer 103 having the next shortest transmission path. The B pixel group having the lowest visibility is connected to the fourth signal processing layer 104 having the longest transmission path. As described above, in the first to fourth pixel groups, a pixel group having a high visibility is connected to a signal processing layer having a short transmission path, and a pixel group having a low visibility is connected to a signal group having a long transmission path. Connect to the layer. As a result, noise generated on the transmission path in the signals of the G1 pixel group and G2 pixel group having high visibility can be reduced, and a high-quality image can be acquired. According to the present embodiment, the signal processing layers 101 to 104 to be connected differ depending on the color of the color filter 120 arranged in the pixel 200, and the number of pixels 200 connected to each signal processing layer 101 to 104 is different. The number of signal processing circuits corresponding to the number is configured.

  In the comparative example, since the signal processing circuits for all the pixels are formed in one signal processing layer, the area of one signal processing layer is larger than that of the light receiving layer, and the entire area of the image sensor is increased. On the other hand, in this embodiment, the signal processing circuits 303, 306, 309, and 312 are configured in different signal processing layers 101 to 104 for each of the first to fourth pixel groups. For this reason, the circuit area of each of the signal processing layers 101 to 104 of the present embodiment can be reduced to about ¼ of the circuit area of the signal processing layer of the comparative example, so that the area of the entire image sensor is reduced. Can do.

  The first to fourth signal processing layers 101 to 104 have different connection points with respect to the pixel 200, but the first to fourth signal processing circuits 303, 306, 309, and 312 themselves may be the same. . Therefore, another advantage of this embodiment is that the design load does not increase in proportion to the number of signal processing layers 101 to 104 to be stacked.

  In the present embodiment, the first to fourth signal processing circuits 303, 306, 309, and 312 are configured in the first to fourth signal processing layers 101 to 104, respectively. However, the present invention is not limited to this. . In order to perform the signal processing of the first to fourth signal processing layers 101 to 104 in parallel, at least a part of the signal control circuits 303, 306, 309, and 312 is used for the first to fourth signal processing layers 101 to 101. The configuration may be shared by 104. In this case, power consumption can be suppressed as compared with a case where a part of the signal control circuits 303, 306, 309, and 312 is not shared.

  In this embodiment, an example in which the constant current source 203 is provided for each pixel 200 has been described. However, the present invention is not limited to this, and a plurality of pixels are shared among pixel groups having the same signal processing layer for transmitting signals. A plurality of constant current sources 203 may be provided.

  In this embodiment, an example in which a signal processing circuit corresponding to each pixel 200 is provided has been described, but the present invention is not limited to this. A configuration may be adopted in which a plurality of signal processing circuits shared by a plurality of pixels are provided in a pixel group having the same signal processing layer for transmitting a signal, and signal processing is sequentially performed on the plurality of pixels sharing the signal processing circuit.

  Moreover, in this embodiment, the example which assumes that signal degradation is so small that the path | route which transmits a signal from the light reception layer 100 to the 1st-4th signal processing layers 101-104 is short was shown. In this case, an example in which the G1 pixel group and the G2 pixel group are connected to the first and second signal processing layers 101 and 102 having a short transmission path in accordance with human visibility is shown, but the present invention is not limited thereto. For example, the spectral characteristics of the color filter 120 provided in the image sensor are often designed so that the sensitivity of G is higher than the sensitivity of R and B in accordance with human visibility. That is, in many scenes, the G pixel signal is larger than the R pixel and B pixel signals. When the signal value is large, the time required for analog-digital conversion becomes long, and therefore it is expected that the amount of heat generated in the AD conversion circuit 205 is large. If there is a concern about the influence of heat generation on the light receiving layer 100, a pixel group with a larger amount of heat generation may be connected to a signal processing layer farther from the light receiving layer 100. For example, a signal processing circuit that processes the signals of the pixels of the G1 pixel group and the G2 pixel group generates more heat than the signal processing circuit that processes the signals of the pixels of the R pixel group and the B pixel group. In that case, the first signal processing circuit 303 processes the signals of the pixels of the B pixel group, the second signal processing circuit 306 processes the signals of the pixels of the R pixel group, and the third signal processing circuit 309 performs the G2 processing. The pixel signal of the pixel group is processed, and the fourth signal processing circuit 312 processes the pixel signal of the G1 pixel group. Further, it is not always necessary to change the signal processing layers 101 to 104 connected to the pixel 200 according to the pixel group of the Bayer array.

  FIG. 5 is a diagram illustrating another configuration example of the image sensor according to the present embodiment, and the same components as those illustrated in FIG. 3 are denoted by the same reference numerals. In the pixel unit 301, four pixels in two rows and two columns including G1, G2, R, and B pixels are defined as one block, and the upper left block is defined as a block in the first row and first column. In that case, the pixel 200 in the pixel unit 301 is divided into an odd-row odd-column block I, an odd-row even-column block J, an even-row odd-column block K, and an even-row even-column block L. .

  The first pixel group of the block I in the odd-numbered and odd-numbered columns is connected to the first signal processing layer 101, and the first signal processing layer 101 is a signal of the first pixel group in the block I in the odd-numbered and odd-numbered columns. Process. The second pixel group of the block J in the odd-numbered even column is connected to the second signal processing layer 102, and the second signal processing layer 102 is a signal of the second pixel group in the block J in the odd-numbered even column. Process. The third pixel group of the even-numbered and odd-numbered block K is connected to the third signal processing layer 103, and the third signal processing layer 103 is a signal of the third pixel group of the even-numbered odd column block K. Process. The fourth pixel group of the even-numbered-even-column block L is connected to the fourth signal processing layer 104, and the fourth signal-processing layer 104 is a signal of the fourth pixel group of the even-numbered even column block L. Process. Also in this case, the area of the image sensor can be reduced.

  As described above, the image pickup device of the present embodiment can configure the number of circuit groups 204 corresponding to the number of pixels while suppressing an increase in area.

(Second Embodiment)
In the first embodiment, signals of the first to fourth pixel groups of the light receiving layer 100 are input to the first to fourth signal processing layers 101 to 104, respectively, and the first to fourth signal processing layers 101 to 101 are input. An example in which signal processing is performed every 104 is shown. Here, paying attention to the transmission path length, as shown in FIG. 1, the first signal processing layer 101, the second signal processing layer 102, the third signal processing layer 103, and the fourth signal processing layer 104 The transmission path from the light receiving layer 100 to the signal processing layers 101 to 104 becomes longer in order. Since the parasitic resistance and parasitic capacitance of the wiring increase in proportion to the transmission path length, the potential stabilization time becomes longer as the signal processing layers 101 to 104 have a longer transmission path length. Hereinafter, the influence of the difference in the transmission path length will be described with reference to FIG. Hereinafter, the points of the second embodiment of the present invention different from the first embodiment will be described.

  FIG. 6 is a diagram illustrating time transition of the input potential V of the first to fourth signal processing layers 101 to 104 when the S signal is read after reading the N signal from the pixel 200. Since the photodiode 112 converts light into electrons (negative charge), the potential of the S signal gradually decreases from the reset level when output starts. The S signal means that the lower the potential, the larger the pixel value.

  The potential transition A indicates the time transition of the input potential of the first signal processing layer 101 when the S signal is output from the light receiving layer 100 to the first signal processing layer 101, and the potential stabilization time is the shortest. The potential transition B indicates the time transition of the input potential of the second signal processing layer 102 when the S signal is output from the light receiving layer 100 to the second signal processing layer 102, and the potential stabilization time is the second shortest. The potential transition C indicates the time transition of the input potential of the third signal processing layer 103 when the S signal is output from the light receiving layer 100 to the third signal processing layer 103, and the potential stabilization time is the third shortest. The potential transition D indicates the time transition of the input potential of the fourth signal processing layer 104 when the S signal is output from the light receiving layer 100 to the fourth signal processing layer 104, and the potential stabilization time is the longest. As the signal processing layers 101 to 104 have longer transmission path lengths, the potential stabilization time becomes longer.

  When the pixel 200 is driven under the same conditions, the fourth signal processing layer 104 is longer than the first signal processing layer 101 due to the difference in transmission path length described above until the potential of the S signal is stabilized. Then, it becomes longer by time Δt. If the first signal processing layer 101 waits for the start of processing until the potential of the S signal of the fourth signal processing layer 104 is settled, there arises a disadvantage that the reading time of the S signal becomes long.

  On the other hand, when the value of the current flowing through the wiring is increased, the potential stabilization time of the S signal is shortened. That is, when the current value of the constant current source 203 in FIG. 2 is increased, the potential stabilization time of the S signal is shortened. However, if the current value is increased for all the pixels, the power consumption increases. In the second embodiment of the present invention, an example of driving when driving the image sensor of FIGS. 1 to 4 described in the first embodiment will be described from the viewpoint of potential stabilization time and power consumption.

  FIG. 7 is a diagram showing a setting example of the drive current of the constant current source 203 (FIG. 2) according to the second embodiment of the present invention. The current Ia is a current of the constant current source 203 provided in the pixel 200 connected to the first signal processing layer 101. The current Ib is a current of the constant current source 203 provided in the pixel 200 connected to the second signal processing layer 102. The current Ic is a current of the constant current source 203 provided in the pixel 200 connected to the third signal processing layer 103. The current Id is a current of the constant current source 203 provided in the pixel 200 connected to the fourth signal processing layer 104. The currents Ia to Id can be changed by changing the sizes of the MOS transistors constituting the constant current source 203 of each pixel 200.

  In the present embodiment, the current value of the constant current source 203 is set so that Ia <Ib <Ic <Id. The current of the constant current source 203 in the pixel 200 of the fourth pixel group (B pixel group) is larger than the current of the constant current source 203 in the pixel 200 of the third pixel group (R pixel group). The current of the constant current source 203 in the pixel 200 of the third pixel group (R pixel group) is larger than the current of the constant current source 203 in the pixel 200 of the second pixel group (G2 pixel group). The current of the constant current source 203 in the pixel 200 of the second pixel group (G2 pixel group) is larger than the current of the constant current source 203 in the pixel 200 of the first pixel group (G1 pixel group). Since the first signal processing layer 101 has a short potential settling time, the current Ia of the constant current source 203 is reduced to reduce power consumption. In contrast, since the fourth signal processing layer 104 has a long potential stabilization time, the current Id of the constant current source 203 is increased and the potential stabilization time is shortened. In this manner, by making the current of the constant current source 203 of the pixel 200 different for each of the first to fourth signal processing layers 101 to 104, the reading of the S signal is speeded up while reducing the increase in power consumption. Can be made.

(Third embodiment)
FIG. 8 is a diagram illustrating a configuration example of a part of the pupil-division imaging device according to the third embodiment of the present invention, in which the light beam emitted from the exit pupil 812 of the photographing lens is incident on the unit pixel 800. is there. The pupil-division imaging element can detect a focus and has a plurality of unit pixels 800 arranged in a matrix. One unit pixel 800 includes two pixels 801a and 801b. The two pixels 801 a and 801 b receive light that has passed through different regions 814 and 815 of the exit pupil 812 of the photographing lens by one microlens 811. By comparing the output signals of the two pixels 801a and 801b, it is possible to detect the focus with the photographing lens. Further, a signal of a captured image can be obtained from the addition signal of the output signals of the two pixels 801a and 801b.

  The exit pupil 812 of the photographic lens has different regions 814 and 815. The color filter 810 is provided between the microlens 811 and the unit pixel 800. The unit pixel 800 includes a first pixel 801a and a second pixel 801b. The optical axis 813 is the central axis of the light beam emitted from the exit pupil 812 of the photographing lens to the unit pixel 800.

  The light that has passed through the exit pupil 812 of the photographic lens enters the unit pixel 800 around the optical axis 813 via the microlens 811 and the color filter 810. The light beam passing through the region 814 is received by the first pixel 801 a through the microlens 811 and the color filter 810. The light beam passing through the region 815 is received by the second pixel 801 b through the microlens 811 and the color filter 810. Therefore, the first pixel 801a and the first pixel 801b respectively receive light in different areas 814 and 815 of the exit pupil 812 of the photographing lens. Therefore, by comparing the output signals of the first pixel 801a and the second pixel 801b, the phase difference of the subject can be detected, and the focus of the photographing lens can be detected.

  Here, in the plurality of unit pixels 800, signals obtained from the plurality of first pixels 801a are A image signals, and signals obtained from the plurality of second pixels 801b are B image signals. A signal obtained by adding the A image signal and the B image signal is defined as an A + B image signal. This A + B image signal is an imaging signal and can be used for a captured image.

  Consider a case where a pupil-divided imaging element has a laminated structure and performs focus detection and captured image generation at high speed. In that case, for one unit pixel 800, a signal processing circuit that processes three signals of an A image signal, a B image signal, and an A + B image signal in parallel is required. When this signal processing circuit is provided in one signal processing layer, there is a concern that the area of the image sensor increases.

  In the present embodiment, an example will be described in which a pupil-division imaging device is applied to the imaging device of the first embodiment. In the first embodiment, an example in which signal processing is performed using different signal processing layers 101 to 104 for each of the first to fourth pixel groups and output from each of the signal processing layers 101 to 104 has been described. In the present embodiment, an example will be described in which A image signal, B image signal, and A + B image signal are output to different signal processing layers and signal processing is performed.

  FIG. 9 is a diagram illustrating a configuration example of the pupil-division imaging device according to the present embodiment, and the same components as those illustrated in FIGS. 2 and 8 are denoted by the same reference numerals. Hereinafter, the points of the present embodiment different from the first embodiment will be described. In the present embodiment, control is performed so that the A image signal, the B image signal, and the A + B image signal are read out from the unit pixel 800 in parallel. As in FIG. 1, the imaging element includes a light receiving layer 900, a first signal processing layer 910, a second signal processing layer 920, and a third signal processing layer 930 that are stacked. The light receiving layer 900 is a first semiconductor substrate, the first signal processing layer 910 is a second semiconductor substrate, the second signal processing layer 920 is a third semiconductor substrate, and a third signal processing layer. Reference numeral 930 denotes a fourth semiconductor substrate.

  Similar to the light receiving layer 100 of FIG. 1, the light receiving layer 900 includes a plurality of microlenses 811, a plurality of color filters 810, and a plurality of unit pixels 800 respectively corresponding to the plurality of microlenses 811. The plurality of unit pixels 800 are arranged in a matrix. Each of the plurality of unit pixels 800 includes a first pixel 801a and a second pixel 801b that each output a pixel signal by photoelectric conversion. Each of the first pixel 801a and the second pixel 801b has the same configuration as the pixel 200 in FIG. The same control pulse PTX is supplied to the gates of the transfer MOS transistors 115 of the first pixel 801a and the second pixel 801b. The same control pulse PRES is supplied to the gates of the reset MOS transistors 201 of the first pixel 801a and the second pixel 801b. The same control pulse PSEL is supplied to the gates of the selection MOS transistors 202 of the first pixel 801a and the second pixel 801b.

  The first signal processing layer 910 includes a first analog signal addition averaging circuit 911 and a first circuit group 912 having the same configuration as the circuit group 204 of FIG. The first analog signal addition averaging circuit 911 and the first circuit group 912 are first signal processing circuits that process the signals of the plurality of unit pixels 800. Specifically, the first analog signal addition averaging circuit 911 and the first circuit group 912 are the first signal processing circuits. The signals of the first pixel 801a and the second pixel 801b are processed.

  The second signal processing layer 920 includes a second analog signal addition averaging circuit 921 and a second circuit group 922 having the same configuration as the circuit group 204 of FIG. The second analog signal addition averaging circuit 921 and the second circuit group 922 are second signal processing circuits that process the signals of the plurality of unit pixels 800. Specifically, the second analog signal addition averaging circuit 921 and the second circuit group 922 are the second signal processing circuits. The signal of one pixel 801a is processed.

  The third signal processing layer 930 includes a third analog signal addition averaging circuit 931 and a third circuit group 932 having the same configuration as the circuit group 204 of FIG. The third analog signal addition averaging circuit 931 and the third circuit group 932 are third signal processing circuits that process the signals of the plurality of unit pixels 800. Specifically, the third analog signal addition averaging circuit 931 and the third circuit group 932 are The signal of the second pixel 801b is processed.

  The first to third analog signal addition averaging circuits 911, 921, and 931 each receive two analog signals and output an analog signal obtained by averaging the two input analog signals. The first analog signal addition averaging circuit 911 receives the A image signal output from the first pixel 801a and the B image signal output from the second pixel 801b, and adds and averages the A image signal and the B image signal. The A + B image signal is output to the first circuit group 912. The second analog signal addition averaging circuit 921 inputs the A image signal output from the first pixel 801a to the two input terminals, adds and averages the two A image signals, and outputs the A image signal to the second image signal. Output to the circuit group 922. The third analog signal addition averaging circuit 931 inputs the B image signal output from the second pixel 801b to the two input terminals, adds and averages the two B image signals, and outputs the B image signal to the third image signal. Output to the circuit group 932.

  The first to third signal processing layers 910, 920, and 930 have the same configuration and can reduce the circuit design load. The second analog signal addition averaging circuit 921 inputs an A image signal and outputs an A image signal, and the third analog signal addition averaging circuit 931 inputs a B image signal and outputs a B image signal. To do. Therefore, the circuit scale of the second and third signal processing layers 920 and 930 may be reduced by deleting the second and third analog signal addition averaging circuits 921 and 931.

  FIG. 10 is a diagram illustrating a configuration example of the imaging element according to the present embodiment, and the same components as those illustrated in FIG. 9 are denoted by the same reference numerals. The imaging element includes a light receiving layer 900, a first signal processing layer 910, a second signal processing layer 920, and a third signal processing layer 930. The light receiving layer 900, the first signal processing layer 910, the second signal processing layer 920, and the third signal processing layer 930 are stacked so as to overlap in order from the top. The first signal processing layer 910 performs signal processing of the A + B image signal. The second signal processing layer 920 performs signal processing of the A image signal. The third signal processing layer 930 performs signal processing of the B image signal.

  The light receiving layer 900 includes a pixel portion 1001 and a pixel control circuit 1002. The pixel unit 1001 includes a plurality of unit pixels 800 arranged in a matrix. Each of the plurality of unit pixels 800 includes a first pixel 801a and a second pixel 801b. The pixel control circuit 1002 controls the pixel portion 1002. The light receiving layer 900 outputs an A image signal from the first pixels 801a of the plurality of unit pixels 800, and outputs a B image signal from the second pixels 801b of the plurality of unit pixels 800.

  The first signal processing layer 910 includes a first signal processing circuit 1011, a first signal processing control circuit 1012, and a first output circuit 1013, and inputs an A image signal and a B image signal from the light receiving layer 900. . The first signal processing circuit 1011 has a first circuit group 912 excluding the first analog signal addition averaging circuit 911 and the output circuit 208 of FIG. The first output circuit 1013 corresponds to the output circuit 208 in the first circuit group 912 in FIG.

  The second signal processing layer 920 includes a second signal processing circuit 1021, a second signal processing control circuit 1022, and a second output circuit 1023, and inputs an A image signal from the light receiving layer 900. The second signal processing circuit 1021 includes a second circuit group 922 excluding the second analog signal addition averaging circuit 921 and the output circuit 208 of FIG. The second output circuit 1023 corresponds to the output circuit 208 in the second circuit group 922 in FIG.

  The third signal processing layer 930 includes a third signal processing circuit 1031, a third signal processing control circuit 1032, and a third output circuit 1033, and inputs the B image signal from the light receiving layer 900. The third signal processing circuit 1031 has a third circuit group 932 excluding the third analog signal addition averaging circuit 931 and the output circuit 208 of FIG. The third output circuit 1033 corresponds to the output circuit 208 in the third circuit group 932 in FIG.

  According to the present embodiment, even if the number of signals read out per unit pixel 800 increases, the light receiving layer 900 outputs a signal divided into a plurality of signal processing layers 910, 920, 930, and another signal processing layer 910, 920. , 930 perform signal processing. Thereby, the enlargement of the area of an image pick-up element can be suppressed.

  In this embodiment, the A + B image signal is generated in the image sensor, but the A + B image signal may be generated by a signal processing unit outside the image sensor. In the present embodiment, it is assumed that the shorter the path for transmitting a signal from the light receiving layer 900 to the first to third signal processing layers 910, 920, and 930, the smaller the signal deterioration, and the A + B image used for imaging. The signal is output to the first signal processing layer 910, but is not limited thereto.

(Fourth embodiment)
In the first embodiment, an example in which signal processing is performed using different signal processing layers 101 to 104 for each of the first to fourth pixel groups and output from each of the signal processing layers 101 to 104 has been described. The fourth embodiment of the present invention is a fifth signal processing layer that calculates the luminance signal Y using the signals of the R pixel, the G1 pixel, the G2 pixel, and the B pixel with respect to the image sensor of the first embodiment. Are further laminated. A luminance signal Y is calculated based on the signals of the R pixel, G pixel, and B pixel, and AF (automatic focus adjustment) calculation and AE (automatic exposure adjustment) calculation can be performed using the luminance signal Y. In that case, when the imaging device calculates and outputs the luminance signal Y, AF calculation and AE calculation can be performed without calculating the luminance signal Y outside, thereby reducing the external calculation processing load. it can. In the present embodiment, an example in which the imaging device further includes a fifth signal processing layer for calculating the luminance signal Y will be described.

  FIG. 11 is a diagram illustrating a configuration example of an imaging element according to the fourth embodiment of the present invention, and the same components as those illustrated in FIG. 3 are denoted by the same reference numerals. The image sensor in FIG. 11 is obtained by adding a fifth signal processing layer 1150 to the image sensor in FIG. Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  The image sensor includes a light receiving layer 100, a first signal processing layer 101, a second signal processing layer 102, a third signal processing layer 103, a fourth signal processing layer 104, and a fifth signal processing. A layer 1150 is stacked in order from the top. The light receiving layer 100 is a first semiconductor substrate, the first signal processing layer 101 is a second semiconductor substrate, the second signal processing layer 102 is a third semiconductor substrate, and a third signal processing layer. Reference numeral 103 denotes a fourth semiconductor substrate, and the fourth signal processing layer 104 is a fifth semiconductor substrate. The fifth signal processing layer 1150 is a sixth semiconductor substrate. The fifth signal processing layer 1150 includes a first pixel group (G1 pixel group), a second pixel group (G2 pixel group), a third pixel group (R pixel group), and a fourth pixel of the light receiving layer 100. Connected to a group (B pixel group).

  The fifth signal processing layer 1150 includes a luminance conversion circuit 1151, a luminance conversion control circuit 1152, and a fifth output circuit 1153, and inputs signals from the G1 pixel group, the G2 pixel group, the R pixel group, and the B pixel group. To do. The luminance conversion control circuit 1152 controls the luminance conversion circuit 1151. The luminance conversion circuit 1151 is a fifth signal processing circuit, which adds a plurality of pixels by multiplying the signals of the pixels of the R pixel group, the G1 pixel group, the G2 pixel group, and the B pixel group by a predetermined coefficient. Luminance signal Y is generated. The fifth signal processing layer 1150 inputs analog signals of R pixel, G1 pixel, G2 pixel, and B pixel from the light receiving layer 100 via the first to fourth signal processing layers 101 to 104. Note that the fifth signal processing layer 1150 may input digital signals of R, G1, G2, and B pixels output from the first to fourth signal processing layers 101 to 104. The fifth output circuit 1153 outputs the luminance signal Y generated by the luminance conversion circuit 1151 to the outside.

  According to this embodiment, the luminance conversion processing of the luminance conversion circuit 1151 can be performed inside the image sensor. Here, when considering the resolution of the luminance signal Y required for the AF calculation and the AE calculation, the AF calculation generally requires the high-resolution luminance signal Y in order to perform highly accurate distance measurement. In many cases, the AE calculation uses a luminance signal Y integrated for each predetermined area. That is, when performing the AE calculation, it is necessary to perform an integration process of the luminance signal Y. Correspondingly, a sixth signal processing layer for performing processing of adding pixel signals to the luminance signal Y in the horizontal and vertical directions can be further added. The sixth signal processing layer is laminated below the fifth signal processing layer 1150, and outputs a luminance signal Y having a resolution suitable for subsequent processing.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

100 light-receiving layer, 101 first signal processing layer, 102 second signal processing layer, 103 third signal processing layer, 104 fourth signal processing layer, 200 pixels, 303 first signal processing circuit, 306 second Signal processing circuit, 309 third signal processing circuit, 312 fourth signal processing circuit

Claims (18)

An imaging device in which at least a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are stacked,
The second semiconductor substrate is provided between the first semiconductor substrate and the third semiconductor substrate;
The first semiconductor substrate has a plurality of pixels that output pixel signals by photoelectric conversion;
The plurality of pixels include pixels of a first pixel group and pixels of a second pixel group,
The second semiconductor substrate has a first signal processing circuit for processing a signal of a pixel of the first pixel group,
The image pickup device, wherein the third semiconductor substrate includes a second signal processing circuit that processes a signal of a pixel of the second pixel group. The pixels of the first pixel group are pixels provided with a color filter of a first color,
2. The image sensor according to claim 1, wherein the pixels of the second pixel group are pixels provided with a color filter of a second color different from the first color.   The image sensor according to claim 2, wherein the first color has a higher human visibility than the second color.   The image sensor according to claim 2 or 3, wherein the first color is green and the second color is red or blue.   The imaging device according to claim 1, wherein the second signal processing circuit generates more heat than the first signal processing circuit. The pixels of the first pixel group are pixels provided with a red or blue color filter,
6. The image sensor according to claim 1, wherein the pixels of the second pixel group are pixels provided with a green color filter. The imaging element includes at least the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate, and the fourth semiconductor substrate,
The third semiconductor substrate is provided between the second semiconductor substrate and the fourth semiconductor substrate;
The plurality of pixels include pixels of the first pixel group, pixels of the second pixel group, and pixels of a third pixel group,
2. The image sensor according to claim 1, wherein the fourth semiconductor substrate includes a third signal processing circuit that processes a signal of a pixel of the third pixel group. The pixels of the first pixel group are pixels provided with a color filter of a first color,
The pixels of the second pixel group are pixels provided with a color filter of a second color different from the first color,
The image sensor according to claim 7, wherein the pixels of the third pixel group are pixels provided with a color filter of a third color different from the first and second colors.   The image sensor according to claim 8, wherein the first color is green, the second color is red, and the third color is blue. The image pickup device includes at least the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate, the fourth semiconductor substrate, and the fifth semiconductor substrate,
The third semiconductor substrate is provided between the second semiconductor substrate and the fourth semiconductor substrate;
The fourth semiconductor substrate is provided between the third semiconductor substrate and the fifth semiconductor substrate;
The plurality of pixels include a pixel of the first pixel group, a pixel of the second pixel group, a pixel of a third pixel group, and a pixel of a fourth pixel group,
The fourth semiconductor substrate has a third signal processing circuit for processing a signal of a pixel of the third pixel group,
The imaging device according to claim 1, wherein the fifth semiconductor substrate includes a fourth signal processing circuit that processes a signal of a pixel of the fourth pixel group. The plurality of pixels are provided with red, green, and blue Bayer array color filters,
The pixels of the first pixel group are pixels provided with a green color filter,
The pixels of the second pixel group are pixels provided with a green color filter,
The pixels of the third pixel group are pixels provided with a red color filter,
The image sensor according to claim 10, wherein the pixels of the fourth pixel group are pixels provided with a blue color filter. The image pickup device includes at least the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate, the fourth semiconductor substrate, and the fifth semiconductor substrate,
The third semiconductor substrate is provided between the second semiconductor substrate and the fourth semiconductor substrate;
The fourth semiconductor substrate is provided between the third semiconductor substrate and the fifth semiconductor substrate;
The plurality of pixels include pixels of the first pixel group, pixels of the second pixel group, and pixels of a third pixel group,
The pixels of the first pixel group are pixels provided with a color filter of a first color,
The pixels of the second pixel group are pixels provided with a color filter of a second color different from the first color,
The pixels of the third pixel group are pixels provided with a color filter of a third color different from the first and second colors,
The fourth semiconductor substrate has a third signal processing circuit for processing a signal of a pixel of the third pixel group,
2. The image sensor according to claim 1, wherein the fifth semiconductor substrate includes a fourth signal processing circuit that generates a luminance signal based on signals of pixels of the first to third pixel groups. The plurality of pixels are provided with red, green, and blue Bayer array color filters,
The image pickup device includes at least the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate, the fourth semiconductor substrate, the fifth semiconductor substrate, and the sixth semiconductor substrate,
The third semiconductor substrate is provided between the second semiconductor substrate and the fourth semiconductor substrate;
The fourth semiconductor substrate is provided between the third semiconductor substrate and the fifth semiconductor substrate;
The fifth semiconductor substrate is provided between the fourth semiconductor substrate and the sixth semiconductor substrate;
The plurality of pixels include a pixel of the first pixel group, a pixel of the second pixel group, a pixel of a third pixel group, and a pixel of a fourth pixel group,
The pixels of the first pixel group are pixels provided with a green color filter,
The pixels of the second pixel group are pixels provided with a green color filter,
The pixels of the third pixel group are pixels provided with a red color filter,
The pixels of the fourth pixel group are pixels provided with a blue color filter,
The fourth semiconductor substrate has a third signal processing circuit for processing a signal of a pixel of the third pixel group,
The fifth semiconductor substrate has a fourth signal processing circuit for processing a signal of a pixel of the fourth pixel group,
The imaging device according to claim 1, wherein the sixth semiconductor substrate has a fifth signal processing circuit that generates a luminance signal based on signals of pixels of the first to fourth pixel groups. Each of the plurality of pixels has a constant current source;
The current of the constant current source in the pixels of the second pixel group is larger than the current of the constant current source in the pixels of the first pixel group. The imaging device according to item. An imaging device in which at least a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are stacked,
The second semiconductor substrate is provided between the first semiconductor substrate and the third semiconductor substrate;
The first semiconductor substrate has a plurality of unit pixels respectively corresponding to a plurality of microlenses,
Each of the plurality of unit pixels includes first and second pixels that each output a pixel signal by photoelectric conversion;
The second semiconductor substrate has a first signal processing circuit that processes signals of the plurality of unit pixels,
The image pickup device, wherein the third semiconductor substrate includes a second signal processing circuit that processes signals of the plurality of unit pixels. The first signal processing circuit processes a signal of the first pixel in the plurality of unit pixels,
16. The image sensor according to claim 15, wherein the second signal processing circuit processes a signal of the second pixel in the plurality of unit pixels. The imaging element includes at least the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate, and the fourth semiconductor substrate,
The third semiconductor substrate is provided between the second semiconductor substrate and the fourth semiconductor substrate;
16. The image sensor according to claim 15, wherein the fourth semiconductor substrate has a third signal processing circuit that processes signals of the plurality of unit pixels. The first signal processing circuit processes signals of the first and second pixels in the plurality of unit pixels,
The second signal processing circuit processes a signal of the first pixel in the plurality of unit pixels,
18. The image sensor according to claim 17, wherein the third signal processing circuit processes a signal of the second pixel in the plurality of unit pixels.

Images