JP6355401B2 - Solid-state imaging device and camera - Google Patents

Description

  The present invention relates to a solid-state imaging device and a camera.

  The solid-state imaging device includes a pixel array in which a plurality of pixels are arranged on a semiconductor substrate. Each pixel includes, for example, a photoelectric conversion unit, a floating diffusion, a transfer transistor, and an amplification transistor. The photoelectric conversion unit photoelectrically converts light incident on the pixel, and the photoelectric conversion unit generates an amount of charge corresponding to the amount of incident light. The floating diffusion is an impurity region formed in the semiconductor substrate so that its potential is in a floating state. The transfer transistor transfers charges from the photoelectric conversion unit to the floating diffusion. The amplification transistor performs a source follower operation and outputs a signal corresponding to the potential of the floating diffusion.

  Some solid-state imaging devices include a pixel array in which focus detection pixels are arranged in addition to imaging pixels. For example, focus detection based on a phase difference detection method can be performed using signals from the focus detection pixels. it can.

JP 2011-60815 A

  One type of noise that can occur in a transistor is flicker noise (also referred to as “1 / f noise”) due to an interface trap at the interface between the channel region and the gate insulating film.

  In each focus detection pixel, pupil division is performed in order to perform focus detection based on the phase difference detection method. Therefore, the amount of light detected by the focus detection pixel is smaller than the amount of light detected by the imaging pixel. Thus, in a pixel with a small amount of incident light, the influence of the flicker noise that can occur in the amplification transistor on the signal component is large.

  An object of the present invention is to provide a technique advantageous for improving the focus detection accuracy of a solid-state imaging device including an imaging pixel and a focus detection pixel.

One aspect of the present invention relates to a solid-state imaging device, and the previous solid-state imaging device is a solid-state imaging device including a plurality of pixels arranged on a semiconductor substrate, and each pixel is a photoelectric conversion formed on the semiconductor substrate. And an amplification transistor that outputs a signal corresponding to the charge generated in the photoelectric conversion unit, and another transistor that is different from the amplification transistor, and the plurality of pixels include an imaging pixel and a focus detection pixel And the area of the photoelectric conversion unit of the focus detection pixel is smaller than the area of the photoelectric conversion unit of the imaging pixel in a plan view with respect to the upper surface of the semiconductor substrate, and the focus detection pixel of the focus detection pixel area of the gate of the amplifying transistor, the much larger than the area of the gate of the amplifying transistor of the imaging pixel, in the image pickup pixel, the amplification tigers and the other transistor The register, the are formed in one active region in the semiconductor substrate, wherein the focus detection pixel, the other transistor and the amplifier transistor are formed separately on different active region in said semiconductor substrate It is characterized by that.

  According to the present invention, it is advantageous to improve the focus detection accuracy of a solid-state imaging device including an imaging pixel and a focus detection pixel.

2A and 2B are diagrams for explaining an example of the entire configuration of a solid-state imaging device and a configuration example of a pixel. The figure for demonstrating the example of the upper surface layout of a pixel array. The figure for demonstrating the example of the cross-section of an imaging pixel and a focus detection pixel. The figure for demonstrating the example of the upper surface layout of a pixel array. The figure for demonstrating the example of the upper surface layout of a pixel array. The figure for demonstrating the example of the upper surface layout of a pixel array. The figure for demonstrating the example of the upper surface layout of a pixel array. The figure for demonstrating the example of the upper surface layout of a pixel array.

(First embodiment)
The solid-state imaging device IA (hereinafter referred to as “device IA”) of the first embodiment will be described with reference to FIGS.

FIG. 1A is a block diagram for explaining an example of the overall configuration of the device IA. The device IA includes a pixel array A _PX , a driving unit UD, a reading unit UR, and a timing generator TG. The pixel array A _PX is configured, for example, by arranging a plurality of pixels PX on a semiconductor substrate (hereinafter simply referred to as “substrate”) such as a silicon substrate. The drive unit UD drives each pixel PX of the pixel array _APX . For example, the drive unit UD has a vertical scanning circuit, and supplies a drive signal or a control signal to each pixel PX to drive each pixel PX in units of rows.

The reading unit UR reads a signal (pixel signal) of each pixel PX driven by the driving unit UD. For example, the reading unit UR has a signal amplification circuit, a horizontal scanning circuit, a multiplexer, and the like, and reads signals from the pixels PX in each column of the pixel array A _PX by controlling them. The readout unit UR may further include an AD conversion unit, and the signal of each pixel PX is output to the outside as digital data ds, for example. Image data is formed based on the signal of each pixel PX.

  The timing generator TG supplies a control signal for reading a signal from each pixel PX to the driving unit UD and the reading unit UR based on a clock signal from the outside.

FIG. 1B shows a circuit configuration example of the pixel PX. The pixel PX functions as one sensor. The pixel PX includes, for example, a photoelectric conversion unit PD such as a photodiode, a floating diffusion FD, a transfer transistor T _TX , an amplification transistor T _SF , a selection transistor T _SEL , and a reset transistor T _RES .

  The floating diffusion FD is a node configured so that its potential is floating (floating state). The floating diffusion FD includes a floating diffusion region. The floating diffusion region is a semiconductor region formed on the substrate so that its potential is floating. For example, when electrons are used as signal charges, the floating diffusion region is formed by injecting an N-type impurity (donor). The floating diffusion FD has a junction capacitance by a PN junction formed between the floating diffusion region and the substrate.

The transfer transistor _TTX receives the control signal TX at the gate terminal. When the transfer transistor T _TX is turned on based on the control signal TX, generated in the photoelectric conversion unit PD accumulated charge is transferred to the floating diffusion FD via the transfer transistor T _TX.

Amplifying transistor T _SF outputs a signal based on charges generated by the photoelectric conversion unit PD. For example, the amplification transistor _{T SF} performs a source follower operation. The gate terminal of the amplifying transistor T _SF is electrically connected to the floating diffusion FD. Then, in response to a charge in the floating diffusion FD is transferred, the source potential of the amplifying transistor T _SF is varied.

The selection transistor _TSEL receives the control signal SEL at the gate terminal. When the selection transistor T _SEL based on the control signal SEL is turned on, a pixel signal corresponding to the source potential of the amplifying transistor T _SF is output to the column signal line L _C.

The reset transistor T _RES receives the control signal RES at the gate terminal. When the reset transistor _TRES becomes conductive based on the control signal RES, the floating diffusion FD is connected to the power supply potential V1 via the reset transistor _TRES, and the potential of the floating diffusion FD is reset.

FIG. 2 is a schematic diagram showing a top layout of the pixel array _APX . Here, for ease of explanation, a configuration in which the pixels PX are arranged so as to form 6 rows × 4 columns is shown. In the drawing, the m-th row is indicated as “Rm” and the n-th column is indicated as “Cn” (m = 1 to 6, n = 1 to 4). In the drawing, the gate patterns of the transistors T _TX , T _SF , T _SEL , and T _RES are indicated as “G _TX ”, “G _SF ”, “G _SEL ”, and “G _RES ”, respectively.

Moreover, for clarity of illustration, while indicating active region and a gate pattern of each element formed on the substrate, the third to fourth column, the power line of the column signal line L _C, and the power supply potential V1 not It is illustrated. For the same reason, a signal line for supplying a control signal to each pixel PX is not shown.

The plurality of pixels PX include pixels for acquiring image data (hereinafter referred to as “imaging pixels”) and pixels for performing focus detection (hereinafter referred to as “focus detection pixels”). That is, focus detection pixels are arranged in the pixel array _APX together with the imaging pixels. The focus detection pixels can be arranged, for example, in part of the central area or part of the peripheral area of the pixel array _APX .

Hereinafter, in order to distinguish between the imaging pixel and the focus detection pixel, in this specification, the focus detection pixel is referred to as “focus detection pixel PX _AF ”.

The signal of the focus detection pixel PX _AF is used for focus detection according to a phase difference detection method, for example. According to the phase difference detection method, a plurality of pairs of focus detection pixels PX _AF are used, and pupil division is performed at each focus detection pixel PX _AF . Specifically, one of the pair of focus detection pixels PX _AF detects half of the incident light flux on one side, and the other of the pair of focus detection pixels PX _AF detects the incident light flux. One half of the luminous flux is detected. Then, focus detection according to the phase difference detection method is performed using pixel signals obtained from each of the plurality of pairs of focus detection pixels PX _AF .

In FIG. 2, the imaging pixels PX are arranged in the first, third to fourth, and sixth rows, and the focus detection pixels PX _AF are arranged in the second and fifth rows. For example, a focus detection pixel _{PX AF} in the second row and the first column, and the focus detection pixels _{PX AF} in the second row and the second column, form a pair of focus detection pixels _{PX AF} above.

FIG. 3A is an enlarged view of four pixels PX in the first to second rows and first to second columns in the pixel array _APX . FIG. 3B is a schematic diagram illustrating a cross-sectional structure taken along the cut line XX ′, that is, a cross-sectional structure of two imaging pixels PX adjacent to each other. 3 (c) is a cross-sectional structure in the cut line Y-Y ', i.e., is a schematic view showing a sectional structure of two focus detection pixels PX _AF adjacent to each other.

As shown in FIGS. 3B and 3C, the photoelectric conversion unit PD and the amplification transistor T _SF (the gate pattern G _SF is shown) are formed on the substrate SUB. As the substrate SUB, a P-type semiconductor substrate may be used. However, a substrate in which a P-type well is formed on an N-type semiconductor substrate or a substrate in which a P-type epitaxial layer is formed on the substrate is used. May be. A structure ST composed of, for example, a wiring layer and an interlayer insulating film is disposed on the substrate SUB, and a microlens ML is disposed on the structure ST. Although not shown here, a color filter, an inner lens, and other optical elements may be further arranged between the structure ST and the microlens ML.

  As a typical example, there is a focus detection pixel provided with a light shielding portion for performing pupil division. The light shielding portion is, for example, a metal pattern having an opening for guiding a part of incident light that has passed through an optical system such as a microlens to the photoelectric conversion portion PD, and is provided in a predetermined wiring layer on the substrate. Can be. In this configuration, the focus detection accuracy is improved by setting the incident light condensing position in the vicinity of the light shielding portion.

On the other hand, in the present embodiment, instead of providing the light shielding part, the photoelectric conversion part PD of the focus detection pixel PX _AF is formed so as to be approximately half the width of the photoelectric conversion part PD of the imaging pixel PX. Yes. Specifically, in plan view (referring to plan view with respect to the upper surface of the substrate; hereinafter the same), the photoelectric conversion unit PD of the focus detection pixel PX _AF has an area or size that is equal to that of the photoelectric conversion unit PD of the imaging pixel PX. On the other hand, it is formed to be substantially half. Here, “substantially half” is preferably about 50%, but may be within a range of 40% to 60%, for example. Note that when the area of the photoelectric conversion unit PD is reduced, noise components due to dark current are reduced.

In order to perform pupil division, the photoelectric conversion unit PD is formed on one side of the pair of focus detection pixels PX _AF (for example, the left side in FIG. 3A), and the pair of focus detection pixels PX. The other side of the _AF is formed on the other side (for example, the right side in FIG. 3A). As a result, the distance between the transistor T _SF or the like (T _SF , T _SEL, and T _RES ) and the photoelectric conversion unit PD is different between one and the other of the pair of focus detection pixels PX _AF .

In this structure, the focus detection accuracy is improved by making the condensing position of incident light near the surface of the substrate SUB. On the other hand, also in the imaging pixel PX, the condensing position of incident light may be near the surface of the substrate SUB. For that reason, according to the present structure, the microlens ML and other optical elements, in the image pickup pixel PX and the focus detection pixels PX _AF, the lens power is not required to be formed differently from each other. Therefore, according to the present embodiment, it is only necessary to form optical systems having the same optical characteristics between the pixels, which is advantageous in terms of process.

Here, as shown in FIG. 3 (a), in plan view, the area of the gate pattern _{G SF} of the amplifying transistor _{T SF} of the focus detection pixel _{PX AF,} the gate pattern _{G SF} of the amplifying transistor _{T SF} imaging pixels PX Is larger than the area. As described above, the area of the photoelectric conversion unit PD of the focus detection pixel PX _AF is smaller than the area of the photoelectric conversion unit PD of the imaging pixel PX. Therefore, the area of the gate pattern G _SF can be increased in the focus detection pixel PX _AF . When the area of the gate pattern G _SF is increased, flicker noise that can be generated in the amplification transistor T _SF can be reduced.

  Flicker noise is noise caused by the interface trap of the MOS transistor, and the mean square value of the noise voltage and the gate size of the MOS transistor are inversely proportional to each other. Therefore, the noise voltage can be effectively reduced by increasing the gate size. For example, the gate size may be increased by increasing the gate width, the gate size may be increased by increasing the gate length, or both the gate width and the gate length may be changed. In a typical MOS transistor, the gate size is determined by the product of channel width and channel length. That is, flicker noise can be reduced by increasing the area of the channel region. The channel region is defined by a gate end and an element isolation portion that defines an active region in plan view.

According to the present embodiment, since the width of the photoelectric conversion unit PD of the focus detection pixel PX _AF is small, the area of the gate pattern G _SF can be increased, and flicker noise in the amplification transistor T _SF of the focus detection pixel PX _AF is reduced. Can be reduced. As described above, according to the present embodiment, it is advantageous to improve the focus detection accuracy of the solid-state imaging device including the imaging pixels and the focus detection pixels.

  In the present embodiment, a focus detection pixel is taken as an example of a pixel with a small amount of incident light. However, even when the area of the photoelectric conversion unit of the first pixel is larger than the area of the photoelectric conversion unit of the second pixel, the incident light of the second pixel having a small area of the photoelectric conversion unit is not used for purposes other than focus detection. The amount of light decreases. Therefore, in the second pixel, the effect of reducing noise such as flicker noise can be obtained by increasing the area of the gate or channel region of the amplification transistor.

(Second Embodiment)
FIG. 4 is a schematic diagram illustrating a top surface layout (portions of first to second rows and first to second columns) of the pixel array _{APX according} to the second embodiment. The present embodiment is different from the first embodiment described above in that the positions of the transistors T _{SF and the} like (T _SF , T _SEL and T _RES ) with respect to the photoelectric conversion unit PD are mainly changed.

Specifically, in one of the pair of focus detection pixels PX _AF , the transistor T _{SF and the} like are formed on one side (for example, the right side in FIG. 4) with respect to the photoelectric conversion unit PD. In the other of the pair of focus detection pixels PX _AF , the transistor _{TSF and the} like are formed on the other side (for example, the left side in FIG. 4) with respect to the photoelectric conversion unit PD.

According to the present embodiment, the same effects as those of the first embodiment can be obtained, and the arrangement of the transistors _{TSF and the} like can be changed, which is advantageous in terms of layout design. Therefore, it is possible to increase the area of the gate pattern G _SF than the first embodiment.

(Third embodiment)
In the third embodiment, as illustrated in FIG. 5, the transistors T _{SF and the} like (T _SF , T _SEL and T _RES ) of the focus detection pixel PX _AF are mainly formed individually in different active regions. This is different from the second embodiment described above.

As described above, the photoelectric conversion unit PD of the focus detection pixel PX _AF is formed so as to be approximately half the width of the photoelectric conversion unit PD of the imaging pixel PX. Therefore, for the focus detection pixel PX _AF , the transistor _{TSF and the} like can be individually formed in different active regions. That is, the transistor _{TSF and the} like are formed at positions separated from each other.

FIG. 5 illustrates a configuration in which all of the transistors T _SF , T _SEL, and T _RES are formed on one side or the other side with respect to the photoelectric conversion unit PD. However, the present embodiment is limited to this configuration. It is not a thing. For example, a part of the transistors T _SF , T _SEL and T _RES is formed on one side with respect to the photoelectric conversion unit PD, and the other transistors except for the part are formed on the other side with respect to the photoelectric conversion unit PD. It is also possible to form it.

  According to the present embodiment, the arrangement of the transistors of the pixel PX can be appropriately changed according to the circuit configuration of the pixel PX, which is advantageous in terms of layout design.

As described above, according to the present embodiment, the same effects as those of the second embodiment can be obtained, and the layout design of the pixel array is further advantageous. Since the different active regions each transistor are formed separately, it is possible to increase further the area of the gate pattern G _SF than the second embodiment.

(Fourth embodiment)
FIG. 6 is a schematic diagram illustrating a top surface layout (first to third rows and first to second column portions) of the pixel array A _{PX according} to the second embodiment. The imaging pixels PX are arranged in the first and second rows, and the focus detection pixels PX _AF are arranged in the third row. In the present embodiment, as illustrated in FIG. 6, two imaging pixels PX that are adjacent to each other mainly share transistors T _{SF and the} like (T _SF , T _SEL, and T _RES ). Different from the third embodiment described above. Specifically, for example, an imaging pixel of the first row and the first column, the imaging pixels of the second row and the first column, share the transistor T _SF and the like.

Note that in the signal readout from the two imaging pixels PX adjacent to each other, the transfer transistor T _TX of one of the two imaging pixels PX (the imaging pixel PX in one row that is the target of signal readout) is turned on. By doing it individually.

As illustrated in FIG. 6, one of the two imaging pixels PX includes a photoelectric conversion unit PD, a transfer transistor _TTX, and a floating diffusion region that are translationally symmetric with respect to the other imaging pixel PX. It is formed to become. More specifically, it is only necessary that the two members or parts to be compared are arranged in parallel (substantially at regular intervals).

The floating diffusion regions of both of the two imaging pixels PX are electrically connected to each other through, for example, a wiring pattern (not shown). Here, in this configuration, the two imaging pixels PX share the transistor _{TSF and the} like between adjacent pixels, while each of the two imaging pixels PX individually has a floating diffusion region ( Not shared). Therefore, in this configuration, the capacitance of the floating diffusion FD of the imaging pixel PX is larger than that in the configuration not sharing the transistor _TSF or the like. When the capacity of the floating diffusion FD is increased, the dynamic range of the pixel PX is increased and the pixel signal is less likely to be saturated.

Therefore, according to the present embodiment, the same effects as those of the third embodiment described above can be obtained, and the dynamic range of the imaging pixel PX can be increased. Here, a configuration in which two imaging pixels PX adjacent to each other share the transistor T _SF or the like is illustrated, but a configuration in which three or more imaging pixels PX share the transistor T _SF or the like may be employed.

In the configuration of the present embodiment, the signal lines for supplying the control signals SEL and RES to each pixel PX (referred to as “signal lines L _SEL and L _RES ”) are 1 for every two rows for the imaging pixels PX. The focus detection pixels PX _AF are arranged one by one for each row. Note that one signal line (referred to as “signal line L _TX ”) for supplying the control signal TX to each pixel PX may be arranged in each row.

(Fifth embodiment)
FIG. 7 is a schematic diagram showing a top layout (portions of the first to fourth rows and first to second columns) of the pixel array _{APX according} to the fifth embodiment. The imaging pixels PX are arranged in the first and second rows, and the focus detection pixels PX _AF are arranged in the third to fourth rows. As illustrated in FIG. 7, the present embodiment is different from the above-described fourth embodiment in that the focus detection pixel PX _AF shares the transistor _{TSF and the} like between adjacent pixels.

In the present embodiment, since both the imaging pixel PX and the focus detection pixel PX _AF share the transistor T _{SF and the} like between the adjacent pixels, the signal lines L _SEL and L _RES are connected to the imaging pixel PX and the focus detection pixel PX _AF . For both, one is arranged every two rows. Therefore, according to the present embodiment, the circuit design of the pixel array A _PX may be performed similarly for both the imaging pixel PX and the focus detection pixel PX _AF , which is advantageous in terms of circuit design.

As illustrated in FIG. 7, in each imaging pixel PX, as in the above-described fourth embodiment, the photoelectric conversion unit PD, the transfer transistor _TTX, and the floating diffusion region are translationally symmetric with respect to the other imaging pixels PX. It is formed to become. In contrast, one of the two focus detection pixels PX _AF adjacent to each other is formed such that the photoelectric conversion unit PD, the transfer transistor _TTX, and the floating diffusion region are line-symmetric or mirror-symmetric with respect to the other. ing.

Here, the floating diffusion FD of the focus detection pixel PX _AF may be formed so that the added capacitance component does not increase. Specifically, two focus detection pixels PX _AF adjacent to each other share a floating diffusion region. In other words, the floating diffusion region of one focus detection pixel PX _{AF and} the floating diffusion region of the other focus detection pixel PX _AF are integrally formed. For example, a focus detection pixel PX _AF in the third row, first column, and the focus detection pixels PX _AF in the fourth row, first column, share a floating diffusion region. The floating diffusion region that is the shared, the photoelectric conversion unit PD and the transfer transistor _{T TX} of one focus detection pixel _{PX AF,} and the photoelectric conversion unit PD and the transfer transistor of the other focus detection pixels _{PX AF T TX,} the Arranged in between.

According to this configuration, the capacity of the floating diffusion FD of the imaging pixel PX is larger than the capacity of the floating diffusion FD of the focus detection pixel PX _AF .

When the capacitance of the floating diffusion FD is reduced, the amount of potential fluctuation of the floating diffusion FD is increased, so that the sensor sensitivity of the pixel PX is increased. Since each focus detection pixel performs pupil division, the amount of light detected by the focus detection pixel is smaller than the amount of light detected by the imaging pixel. Therefore, for the focus detection pixel PX _AF , it is required to increase the sensor sensitivity rather than increasing the dynamic range.

According to the present embodiment, for the imaging pixel PX, the dynamic range can be increased, while for the focus detection pixel PX _AF , the sensor sensitivity can be increased. Therefore, according to the present embodiment, the same effects as those of the fourth embodiment described above can be obtained, the sensor sensitivity of the focus detection pixel PX _AF is increased, and the circuit design of the pixel array A _PX is advantageous. .

(Sixth embodiment)
In the fifth embodiment described above, the two focus detection pixels PX _AF adjacent to each other exemplify a configuration in which the photoelectric conversion unit PD, the transfer transistor T _TX and the floating diffusion region are line-symmetric or mirror-symmetric with respect to each other. However, these symmetries are not limited to this configuration.

FIG. 8 is a schematic diagram illustrating a top surface layout (portions of the first to fourth rows and first to second columns) of the pixel array _{APX according} to the sixth embodiment. This embodiment is different from the fifth embodiment mainly in that a pair of focus detection pixels PX _AF for performing focus detection according to the phase difference detection method share a floating diffusion region. For example, a focus detection pixel PX _AF in the third row, first column, and the focus detection pixels PX _AF in the fourth row, first column, forms a pair of focus detection pixels PX _AF, these floating diffusion Sharing area. One of the pair of focus detection pixels PX _AF is formed so that the photoelectric conversion unit PD and the transfer transistor T _TX are point-symmetric with respect to the other, with the floating diffusion region as the center. According to this embodiment, the same effect as that of the fifth embodiment can be obtained.

Further, the transistors T _{SF and the} like (T _SF , T _SEL and T _RES ) may be formed at positions separated from each other as in the third embodiment. According to the present embodiment, for example, a part of the transistors T _SF , T _SEL, and T _RES is formed in one of the pair of focus detection pixels PX _AF , and other transistors excluding the part are used as a pair of focus detection pixels. It is also possible to form it on the other side of PX _AF . For example, the transistor T _SF is formed in the focus detection pixel PX _AF in the third row / first column, and the transistors T _SEL and T _RES are formed in the focus detection pixel PX _AF in the fourth row / first column. ing. Therefore, according to the present embodiment, the arrangement of the transistors of the pixel PX can be appropriately changed according to the circuit configuration of the pixel PX, which is advantageous in terms of layout design.

(Other)
In the above, some preferred embodiments have been exemplified, but the present invention is not limited to these, and a part thereof may be changed according to the purpose or the like, or in combination with other embodiments. Also good. Further, the relationship between the row and the column of each pixel PX exemplified in each embodiment may be reversed. For example, the configuration in which the adjacent pixel PX in the adjacent row shares the transistor _{TSF and the} like is the adjacent pixel PX in the adjacent column. May be applied. The same applies to the case where the two focus detection pixels PX _AF share the floating diffusion region.

  In each of the above embodiments, a solid-state imaging device included in an imaging system represented by a camera or the like has been described. The concept of the imaging system includes not only a device mainly for photographing, but also a device (for example, a personal computer, a portable terminal, etc.) that has a photographing function as an auxiliary. The imaging system may include the solid-state imaging device exemplified in each of the above-described embodiments and a processing unit that processes a signal output from the solid-state imaging device. The processing unit can include, for example, a processor that processes digital data output from the A / D conversion unit or the A / D converter. The focus detection process may be performed by the processing unit, or a focus detection unit that performs the focus detection process may be provided separately from the processing unit.

IA: solid-state imaging device, PX: pixel, PD: photoelectric conversion unit, FD: floating diffusion, T _TX : transfer transistor, T _SF : amplification transistor, G _SF : gate pattern of amplification transistor.

Claims (17)

A solid-state imaging device including a plurality of pixels arranged on a semiconductor substrate,
Each pixel is
A photoelectric conversion part formed on the semiconductor substrate;
An amplification transistor that outputs a signal corresponding to the charge generated in the photoelectric conversion unit;
Another transistor different from the amplification transistor;
Have
The plurality of pixels include an imaging pixel and a focus detection pixel,
In plan view with respect to the upper surface of the semiconductor substrate, the area of the photoelectric conversion unit of the focus detection pixel is smaller than the area of the photoelectric conversion unit of the imaging pixel, and the gate of the amplification transistor of the focus detection pixel area is much larger than the area of the gate of the amplifying transistor of the imaging pixels,
In the imaging pixel, the other transistor and the amplification transistor are formed in one active region in the semiconductor substrate,
In the focus detection pixel, the other transistor and the amplification transistor are individually formed in different active regions of the semiconductor substrate . 2. The solid according to claim 1, wherein a product of a channel length and a channel width of the amplification transistor of the focus detection pixel is larger than a product of a channel length and a channel width of the amplification transistor of the imaging pixel. Imaging device. The area of the photoelectric conversion unit of the focus detection pixel is in a range of 40% to 60% of the area of the photoelectric conversion unit of the imaging pixel. The solid-state imaging device described. The plurality of pixels include a plurality of the focus detection pixels,
A distance between the photoelectric conversion unit of the first focus detection pixel of the plurality of focus detection pixels and the amplification transistor;
4. The distance between the photoelectric conversion unit of the second focus detection pixel of the plurality of focus detection pixels and the amplification transistor is different from each other. 5. The solid-state imaging device described. In the first focus detection pixel, the amplification transistor is disposed on a first side with respect to the photoelectric conversion unit,
Wherein in the second focus detection pixels, the amplifying transistor to the photoelectric conversion unit, in claim 4, wherein the first side, characterized in that it is arranged on a second side opposite The solid-state imaging device described. The plurality of pixels include a plurality of the focus detection pixels,
In the first focus detection pixel of the plurality of focus detection pixels, the amplification transistor is disposed on the first side with respect to the photoelectric conversion unit,
In the second focus detection pixel of the plurality of focus detection pixels, the amplification transistor is disposed on a second side opposite to the first side with respect to the photoelectric conversion unit. The solid-state imaging device according to any one of claims 1 to 3. Each pixel is
A floating diffusion region formed in the semiconductor substrate;
A transfer transistor for transferring charge from the photoelectric conversion unit to the floating diffusion region,
The plurality of pixels include a plurality of focus detection pixels, and the plurality of focus detection pixels include a first focus detection pixel and a second focus detection pixel,
The floating diffusion region of the first focus detection pixel and the floating diffusion region of the second focus detection pixel are the photoelectric conversion unit and the transfer transistor of the first focus detection pixel, and the second Formed integrally between the photoelectric conversion unit and the transfer transistor of the focus detection pixel,
The photoelectric conversion unit and the transfer transistor of the first focus detection pixel and the photoelectric conversion unit and the transfer transistor of the second focus detection pixel are arranged so as to have symmetry. The solid-state imaging device according to any one of claims 1 to 3. The solid-state imaging device according to claim 7, wherein the symmetry satisfies one of line symmetry and point symmetry. The plurality of pixels include a plurality of the imaging pixels,
The floating diffusion region of the first imaging pixel of the plurality of imaging pixels and the floating diffusion region of the second imaging pixel of the plurality of imaging pixels are electrically connected. The solid-state imaging device according to any one of claims 1 to 8 . The solid-state imaging device according to claim 9 , wherein the first imaging pixel and the second imaging pixel share one amplification transistor. A solid-state imaging device according to any one of claims 1 to 10 ,
And a processing unit that processes a signal from the solid-state imaging device. The camera according to claim 11 , further comprising a focus detection unit that performs focus detection according to a phase difference detection method based on a signal from the focus detection pixel.   A solid-state imaging device including a plurality of pixels arranged on a semiconductor substrate,
  Each pixel is
    A photoelectric conversion part formed on the semiconductor substrate;
    An amplification transistor that outputs a signal corresponding to the charge generated in the photoelectric conversion unit;
  Have
  The plurality of pixels includes a plurality of imaging pixels and a plurality of focus detection pixels,
  In plan view with respect to the upper surface of the semiconductor substrate, the area of the photoelectric conversion unit of the focus detection pixel is smaller than the area of the photoelectric conversion unit of the imaging pixel, and the gate of the amplification transistor of the focus detection pixel The area is larger than the area of the gate of the amplification transistor of the imaging pixel,
  A distance between the photoelectric conversion unit of the first focus detection pixel of the plurality of focus detection pixels and the amplification transistor; and a photoelectric conversion unit of the second focus detection pixel of the plurality of focus detection pixels. The distance from the amplification transistor is different from each other.
  A solid-state imaging device.   The product of the channel length and the channel width of the amplification transistor of the focus detection pixel is larger than the product of the channel length and the channel width of the amplification transistor of the imaging pixel.
  The solid-state imaging device according to claim 13.   The area of the photoelectric conversion unit of the focus detection pixel is in a range of 40% to 60% of the area of the photoelectric conversion unit of the imaging pixel.
  The solid-state imaging device according to claim 13 or 14,   In the first focus detection pixel, the amplification transistor is disposed on a first side with respect to the photoelectric conversion unit,
  In the second focus detection pixel, the amplification transistor is disposed on a second side opposite to the first side with respect to the photoelectric conversion unit.
  The solid-state imaging device according to claim 13, wherein the solid-state imaging device is provided.   The floating diffusion region of the first imaging pixel of the plurality of imaging pixels and the floating diffusion region of the second imaging pixel of the plurality of imaging pixels are electrically connected.
  The solid-state imaging device according to claim 13, wherein the solid-state imaging device is provided.

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