JP2012058522A - Focus detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a conventional problem with detection accuracy in a focus detector corresponding to a pupil division system.SOLUTION: In a focus detector comprising a first focus detection pixel which makes a first pupil-split luminous flux incident and outputs a first focus detection signal and a second focus detection pixel which makes a second luminous flux paired with the first luminous flux incident and outputs a second focus detection signal, the first focus detection pixel and the second focus detection pixel comprises a photoelectric conversion part for accumulating electrons and holes corresponding to the quantity of incident light, an electron read-out part for reading out the electrical signal corresponding to the amount of the electrons accumulated in the photoelectric conversion part and a hole read-out part for reading out the electric signal corresponding to the amount of the holes accumulated in the photoelectric conversion part.

Description

  The present invention relates to a focus detection apparatus.

  A normal electronic camera has a focus detection function for detecting a focus position with respect to a subject image. As one of such focus detection functions, a focus detection method based on a pupil division method is known, and an image sensor in which a pair of focus detection pixels are embedded in a part of shooting pixels has been developed (for example, , See Patent Document 1).

JP 2007-282109 A

  However, the focus detection pixel corresponding to the pupil division method shields half of the photoelectric conversion unit, so that the SN ratio of the focus detection signal is deteriorated and the focus detection accuracy is deteriorated.

  An object of the present invention is to provide a focus detection device capable of improving focus detection accuracy.

  The focus detection apparatus according to the present invention receives a first focus detection pixel that outputs a first focus detection signal by entering a pupil-divided first light beam, and a second light beam that forms a pair with the first light beam. And a second focus detection pixel that outputs a second focus detection signal and the first focus detection pixel and the second focus detection pixel emit electrons and holes according to the amount of incident light. A photoelectric conversion unit that accumulates, an electronic readout unit that reads out an electrical signal corresponding to the amount of electrons accumulated in the photoelectric conversion unit, and a hole readout that reads out an electrical signal corresponding to the amount of holes accumulated in the photoelectric conversion unit Part.

  The focus detection apparatus according to the present invention can improve the accuracy of focus detection.

It is a figure which shows the structural example of the image pick-up element 101 which concerns on embodiment. It is a figure which shows the example of arrangement | positioning of the pixel Px for imaging, and the pixel FPx for focus detection. It is a figure which shows the circuit example of the pixel Px for imaging. It is a figure which shows the example of a layout of the pixel Px for imaging. It is a figure which shows the example of operation timing of the pixel Px for imaging. It is a figure which shows the circuit example of the pixel FPx for focus detection. It is a figure which shows the example of a layout of the pixel FPx for focus detection. It is a figure which shows the example of operation timing of the pixel FPx for focus detection. It is a figure which shows the example of a layout of the conventional focus detection pixel. It is explanatory drawing which compares a pixel layout.

Hereinafter, embodiments of a focus detection apparatus according to the present invention will be described in detail with reference to the drawings. In the present embodiment, the image sensor 101 including the focus detection apparatus according to the present invention will be described as an example.
[Configuration Example of Image Sensor 101]
FIG. 1 is a diagram illustrating a configuration example of the image sensor 101. In the example of FIG. 1, the image sensor 101 has 16 pixels of 4 rows and 4 columns arranged in a matrix, but an image sensor actually used in an electronic camera or the like has about 5 million pixels.

  Here, the imaging element 101 according to the present embodiment includes imaging pixels for imaging a subject image and focus detection pixels for performing focus detection by the pupil division method. For example, in FIG. 1, the pixel Px (1,1) in the first row to the pixel Px (1,4), the pixel Px (3,1) in the third row, the pixel Px (3,4), and the pixel in the fourth row Pixels Px (4, 4) from Px (4, 1) are imaging pixels. In the second row, the pixel Px (2,1) in the first column and the pixel Px (2,4) in the fourth column are also imaging pixels, but the pixel FPx (2,2) in the second column The pixel FPx (2, 3) in the third column is a focus detection pixel. In the following description, when common to all pixels for imaging, it is referred to as an imaging pixel Px. Similarly, when common to all pixels for focus detection, it is referred to as a focus detection pixel FPx.

  In general, in a focus detection method using a pupil division method (also called a phase difference detection method), an image shift amount is detected from an output corresponding to each of a focus detection pixel for a left aperture and a focus detection pixel for a right aperture to determine a focus position. Ask. Here, in order to obtain the image shift amount, a plurality of pairs of focus detection pixels are actually arranged in a straight line, but in FIG. 1, a pair of focus detection pixels FPx ( 2, 2) and only the focus detection pixel FPx (2, 3) for the right opening are shown. For example, in the case of FIG. 2, a plurality of pairs of focus detection pixels are arranged from the pixels Px (6,4) to Px (6,19) in the sixth row, and a pair of odd columns and even columns is paired. This constitutes a focus detection pixel. In this case, for example, even-numbered columns are left-opening focus detection pixels, and odd-numbered columns are right-opening focus detection pixels.

  In FIG. 1, the image sensor 101 includes a vertical scanning circuit 102, a horizontal output circuit 103, and an output amplifier 104. The electrical signal read from the imaging pixel Px is output to the horizontal output circuit 103 via the vertical signal lines VLs (1) to VLs (4) arranged for each column. Further, current sources Pws (1) to Pws (4) connected to the negative power source Vss are arranged in the vertical signal lines VLs (1) to VLs (4), respectively. Here, the electrical signal read from the imaging pixel Px is a negative signal (negative single-ended signal).

  On the other hand, the electrical signal read from the focus detection pixel FPx is a positive / negative differential signal. Then, the negative electrical signal read from the focus detection pixel FPx is output to the horizontal output circuit 103 via the vertical signal lines VLs (2) and VLs (3) arranged in the column where the focus detection pixel FPx is located. Is output. Further, the positive electrical signal read from the focus detection pixel FPx is output to the horizontal output circuit 103 via the vertical signal lines VLd (2) and VLd (3) arranged in the column where the focus detection pixel FPx is located. Is output. Note that current sources Pwd (2) and Pwd (3) connected to the positive power supply Vdd are arranged on the vertical signal lines VLd (2) and VLd (3), respectively.

  Here, in the following description, the current source Pws (1) to Pws (4) common to the current sources Pws (4) is referred to as the current source Pws, and the vertical signal line VLs (1) to VLs (4) common to the vertical signal lines. It shall be called VLs. Similarly, when common to the current sources Pwd (2), Pwd (3) and the vertical signal lines VLd (2), VLd (3), they are referred to as the current source Pwd and the vertical signal line VLd, respectively.

  The vertical scanning circuit 102 reads out from the imaging pixels Px and the focus detection pixels FPx to the vertical signal lines VLs (1) to VLs (4), VLd (2), and VLd (3) for each row. Timing signals (φRn, φSELn, φRp, φSELp) are output in order for each row. The function of the timing signal will be described in detail when the circuit configuration of each pixel is described later.

  The horizontal output circuit 103 temporarily holds the signal of each column (each pixel) read for each row from each imaging pixel Px and each focus detection pixel FPx, and then reads out the signals in the column order (pixel unit). And output to the outside of the image sensor 104 via the output amplifier 104. Here, the horizontal output circuit 103 may independently output a single-end signal read from the imaging pixel Px and a differential signal read from the focus detection pixel FPx to the outside of the imaging element 101. Alternatively, a circuit for converting a single end signal into a differential signal or converting a differential signal into a single end signal may be provided in the horizontal output circuit 103 and output to the outside of the image sensor 103. As the output amplifier, a single-ended amplifier or a differential amplifier is used according to the output form.

  In this manner, the image sensor 101 has a pair of focus detection pixels FPx arranged in a part of an array of a plurality of image pickup pixels, and a signal photoelectrically converted by the image pickup pixels Px is a single-end signal, and focus detection is performed. Signals photoelectrically converted by the pixel FPx are differential signals, which are read out to the horizontal output circuit 103 and output to the outside via the output amplifier 104.

In the above description, the signal photoelectrically converted by the focus detection pixel FPx is read as a differential signal to the horizontal output circuit 103. However, each focus detection pixel FPx converts the signal into a single-end signal and outputs it horizontally. You may make it read to the circuit 103. FIG. Alternatively, a signal photoelectrically converted by the imaging pixel Px may be shared as a negative signal on one side of a differential signal instead of a single end signal and read to the horizontal output circuit 103.
[Circuit Example of Imaging Pixel Px]
FIG. 3 shows a circuit example of the imaging pixel Px. The imaging pixel Px includes a photodiode PD and NMOS transistors SFn, Rn, and SELn.

  The photodiode PD accumulates electrons according to the amount of incident light. Here, in a general photodiode, electrons (electrons) or holes (holes) are generated by incident photons (photons), and the electrons or holes are accumulated in the potential well region of the semiconductor circuit. Then, either electrons or holes are read out and used as a pixel output. Here, the photodiode PD of the imaging pixel Px accumulates electrons and outputs an electrical signal corresponding to the accumulated amount of electrons (because it is an electron, a negative signal).

  The NMOS transistor Rn resets electrons accumulated in the photodiode PD when the timing signal ΦRn is given from the vertical scanning circuit 102.

  The NMOS transistor SFn constitutes a current source Pws and a source follower circuit via the NMOS transistor SELn, and converts it into an electrical signal corresponding to the amount of electrons accumulated in the photodiode PD.

  When the timing signal ΦSELn is given from the vertical scanning circuit 102, the NMOS transistor SELn reads the electrical signal converted by the NMOS transistor SFn as the output OUT (−) of the pixel Px.

  Next, FIG. 4 shows a circuit layout example of the imaging pixel Px. FIG. 4 is a plan view of the imaging pixel Px as viewed from the light incident direction. In FIG. 4, the same reference numerals as those in FIG. In the imaging pixel Px, a readout circuit for reading out electrons stored in the photodiode PD and converting them into an electric signal is arranged below the pixel area, and the photodiode PD is arranged above the pixel area so as to obtain as large an area as possible. Has been.

  As described above, the imaging pixel Px converts the amount of electrons accumulated in accordance with incident light into an electrical signal, and is read out from each pixel to the vertical signal line VLs as an image signal.

  Here, the timing when the subject image is captured by the electronic camera equipped with the image sensor 101 will be described with reference to FIG. FIG. 5 is a diagram illustrating timing when the imaging pixel Px of FIGS. 3 and 4 performs exposure and outputs an electrical signal to the output OUT (−). Actually, the output OUT (−) appears only when the NMOS transistor SELn is turned on in the circuit of FIG. 3, but in FIG. 5, the output OUT is output even when the NMOS transistor SELn is not turned on. The signal level of (-) is depicted as changing. Further, the period from timing T1 to T4 is one shooting period, and the same cycle is repeated in preview display, moving image shooting, and the like.

  Hereinafter, description will be made in order according to the timing of FIG.

  (Timing T1) When the timing signal ΦRn of the vertical scanning circuit 102 changes from the Low level to the High level, the NMOS transistor Rn becomes conductive, and the electrons accumulated in the photodiode PD are reset.

  (Timing T2) When the timing signal ΦRn of the vertical scanning circuit 102 changes from the High level to the Low level, the NMOS transistor Rn is turned off and exposure is started. Here, it is assumed that the shutter is an electronic shutter, and light from the subject is always incident on each pixel of the image sensor 101. Then, since electrons are accumulated in the photodiode PD until timing T3, the output OUT (−) decreases in the negative direction.

  (Timing T3) After the exposure for a predetermined time according to the shutter speed, when the timing signal ΦSELn of the vertical scanning circuit 102 changes from Low level to High level, the NMOS transistor SELn is turned on, and the electrons of the photodiode PD The electric signal converted by the NMOS transistor SFn according to the amount is read out from the output OUT (−) of the pixel Px to each vertical signal line VLs.

  (Timing T4) When the timing signal ΦSELn of the vertical scanning circuit 102 changes from the High level to the Low level, the NMOS transistor SELn is turned off, and the reading of the electric signal according to the amount of electrons of the photodiode PD is completed. At the same time, the next imaging period is started, and the timing signal ΦRn of the vertical scanning circuit 102 changes from the low level to the high level similarly to the timing T1, and the electrons accumulated in the photodiode PD are reset.

In this way, the subject image can be taken with the imaging pixel Px.
[Circuit Example of Focus Detection Pixel FPx]
FIG. 6 shows a circuit example of the focus detection pixel FPx. The focus detection pixel FPx includes a photodiode PDf, NMOS transistors SFn, Rn, and SELn, and PMOS transistors SFp, Rp, and SELp. The NMOS transistors SFn, Rn, and SELn have the same circuit configuration as that of the imaging pixel Px, and therefore the same reference numerals are used.

  The photodiode PDf accumulates electrons and holes according to the amount of incident light.

  The NMOS transistor Rn resets electrons accumulated in the photodiode PDf when the timing signal ΦRn is given from the vertical scanning circuit 102.

  The NMOS transistor SFn constitutes a current source Pws and a source follower circuit via the NMOS transistor SELn, and converts it into an electrical signal corresponding to the amount of electrons accumulated in the photodiode PDf.

  When the timing signal ΦSELn is given from the vertical scanning circuit 102, the NMOS transistor SELn reads the electrical signal converted by the NMOS transistor SFn as the output OUT (−) of the pixel Px.

  The PMOS transistor Rp resets holes accumulated in the photodiode PDf when the timing signal ΦRp is given from the vertical scanning circuit 102.

  The PMOS transistor SFp constitutes a current source Pwd and a source follower circuit via the PMOS transistor SELp, and converts it into an electrical signal corresponding to the amount of holes accumulated in the photodiode PDf.

  When the timing signal ΦSELp is given from the vertical scanning circuit 102, the PMOS transistor SELp reads the electrical signal converted by the PMOS transistor SFp as the output OUT (+) of the pixel Px.

  Next, FIG. 7 shows a circuit layout example of the focus detection pixel FPx. FIG. 7 is a plan view of the focus detection pixel FPx as seen from the incident direction of light. In FIG. 7, the same reference numerals as those in FIG. 6 denote the same components. In the focus detection pixel FPx, a readout circuit for reading out the electrons accumulated in the photodiode PDf and converting it into a negative electrical signal, and a hole accumulated in the photodiode PDf are read out and converted into a positive electrical signal. The photodiode PDf is arranged on the right side of the pixel area and the photodiode PDf so as to obtain the largest possible area on the left side. FIG. 7 is an example of a circuit layout of the focus detection pixel FPx (2, 2) in the left opening. The circuit layout of the focus detection pixel FPx (2, 3) in the right opening is symmetrical to that in FIG. become.

  In this way, the focus detection pixel FPx converts the amount of electrons and holes accumulated according to incident light into positive and negative electrical signals, respectively, and outputs a differential signal from each focus detection pixel FPx to the vertical signal lines VLd, Each is read out to VLs.

  Here, timing when a focus detection signal is acquired in order to perform focus detection of a subject with an electronic camera equipped with the image sensor 101 will be described with reference to FIG. FIG. 8 is a diagram illustrating timings when the focus detection pixels FPx in FIGS. 6 and 7 are exposed to output positive and negative electrical signals to the output OUT (−) and the output OUT (+), respectively. As in the case of FIG. 3, in practice, in the circuit of FIG. 6, a signal appears at the output OUT (−) only when the NMOS transistor SELn is turned on, and the PMOS transistor SELp is turned on. Only when the signal appears at the output OUT (+), the output OUT (−) and the output OUT are output even when the NMOS transistor SELn and the PMOS transistor SELp are in the non-conducting state as shown in FIGS. The (+) signal level is depicted as changing. Similarly to the case of FIG. 3, the timing T1 to T4 is one focus detection signal acquisition period, and the same cycle is repeated during the focus detection operation.

  Hereinafter, description will be made in order according to the timing of FIG. 8A and 8B show the case where the amount of electrons of the photodiode PDf is converted into an electric signal for reading, and FIGS. 8C and 8D show the amount of holes of the photodiode PDf. It is a figure which shows each timing chart and signal change at the time of converting into an electrical signal and reading.

  (Timing T1) In FIG. 8B, when the timing signal ΦRn of the vertical scanning circuit 102 changes from the Low level to the High level, the NMOS transistor Rn becomes conductive, and the electrons accumulated in the photodiode PDf are reset. . On the other hand, in FIG. 8D, when the timing signal ΦRp of the vertical scanning circuit 102 changes from the High level to the Low level, the PMOS transistor Rp becomes conductive, and the holes accumulated in the photodiode PDf are reset.

  (Timing T2) When the timing signal ΦRn of the vertical scanning circuit 102 changes from the High level to the Low level, the NMOS transistor Rn is turned off and exposure is started. On the other hand, when the timing signal ΦRp of the vertical scanning circuit 102 changes from the Low level to the High level, the PMOS transistor Rp is turned off and exposure is started.

  Here, it is assumed that the shutter is an electronic shutter, and light from the subject is always incident on each pixel of the image sensor 101. Then, electrons and holes are accumulated in the photodiode PDf until timing T3, and the output OUT (−), which is a signal output corresponding to the amount of electrons accumulated in the photodiode PDf, is negative as shown in FIG. As shown in FIG. 8C, the output OUT (+), which is a signal output corresponding to the amount of holes accumulated in the photodiode PDf, increases in the positive direction.

  (Timing T3) After the exposure for a predetermined time according to the shutter speed, when the timing signal ΦSELn of the vertical scanning circuit 102 changes from Low level to High level, the NMOS transistor SELn becomes conductive, and the electrons of the photodiode PDf A negative electric signal converted by the NMOS transistor SFn according to the amount is read from the output OUT (−) of the pixel Px to each vertical signal line VLs. On the other hand, when the timing signal ΦSELp of the vertical scanning circuit 102 changes from the High level to the Low level, the PMOS transistor SELp becomes conductive, and the positive electric signal converted by the PMOS transistor SFp according to the amount of holes of the photodiode PDf. Are read out from the output OUT (+) of the pixel Px to each vertical signal line VLd.

  (Timing T4) When the timing signal ΦSELn of the vertical scanning circuit 102 changes from the High level to the Low level, the NMOS transistor SELn is turned off, and reading of the negative electric signal corresponding to the amount of electrons of the photodiode PDf is completed. . On the other hand, when the timing signal ΦSELp of the vertical scanning circuit 102 changes from the Low level to the High level, the PMOS transistor SELp is turned off, and the reading of the positive electric signal corresponding to the hole amount of the photodiode PDf is completed.

  At the same time, the acquisition period of the next focus detection signal is started, and the timing signal ΦRn of the vertical scanning circuit 102 is changed from the low level to the high level similarly to the timing T1, and the electrons accumulated in the photodiode PDf are reset. At the same time, the timing signal ΦRp of the vertical scanning circuit 102 changes from the high level to the low level, and the holes accumulated in the photodiode PDf are reset.

  In this way, in the focus detection pixel FPx, the amount of electrons and the amount of holes accumulated in accordance with the incident light are converted into positive and negative electrical signals (output OUT (+) and output OUT (−)), respectively. Read out from the detection pixel FPx to the vertical signal lines VLd and VLs, respectively.

  Here, FIG. 8E shows the output OUTds when the output OUT (+) and the output OUT (−) read from each focus detection pixel FPx are differential signals. If the amplitude of the output OUT (−) is Va and the amplitude of the output OUT (+) is Vb, the differential signal output OUTds is (Va + Vb). In general, assuming that the amount of electrons and the amount of holes accumulated in the photodiode PDf are the same for the same amount of light, the output OUTds of the differential signal is the amplitude of the negative output OUT (−) or the positive output. This is twice the amplitude of OUT (+). Thereby, the SN ratio of the focus detection signal output from the focus detection pixel FPx is improved. Furthermore, since it is a differential signal, common mode noise can be removed, and the quality of the focus detection signal can be further improved. Since the focus position is detected using the focus detection signal obtained in this way, highly accurate focus detection can be performed.

  The conventional focus detection pixel uses the same circuit and layout as the image pickup pixel Px described in FIGS. 3 and 4 and uses a light shielding mask (in the right half of the image pickup pixel Px as shown in FIG. 9A). Mask) is arranged to form focus detection pixels for the left opening, and similarly, as shown in FIG. 9B, a light shielding mask is arranged on the left half of the imaging pixel Px to detect focus for the right opening. Pixels were formed. For this reason, there is a problem that a part of the opening becomes a readout circuit, and the area is small and a sufficient SN ratio cannot be secured. There is also a problem that a part of the photodiode PD under the light shielding mask is wasted.

  Therefore, in the image sensor 101 according to the present embodiment, the photodiode PDf is arranged so as to obtain as large an opening area as possible even though the pixel has the same area as the imaging pixel Px. Can be improved. Furthermore, by disposing a differential circuit with a larger area within the pixel that can be used for the readout circuit than before, common mode noise can be removed and the signal level of the focus detection signal can be increased to twice that of the prior art. The SN ratio of the focus detection signal can be improved.

  Here, FIG. 10 shows a comparative example of the pixel layout of the imaging pixel Px, the focus detection pixel FPx of the present embodiment, and the conventional focus detection pixel FPx2. FIG. 10A shows the layout of the imaging pixels Px, which is the same as FIG. FIG. 10B shows the layout of the conventional focus detection pixel FPx2, in which the right or left half of the imaging pixel Px is covered with a light shielding mask. FIG. 10C is a diagram showing the layout of the focus detection pixel FPx of the present embodiment. The opening area of the photodiode PDf is larger than that of the conventional focus detection pixel FPx2, and the mask region (insensitive region) is formed. Since the area that can be used for the readout circuit disposed below is widened, a differential circuit having a circuit scale larger than that of the imaging pixel Px can be disposed. Although it is conceivable to dispose a differential circuit also in the imaging pixel Px, in the case of the same pixel area, the area of the photodiode PD is reduced by the increase in the area of the readout circuit. Like the image sensor 101, it is appropriate that the imaging pixel Px is a conventional single-ended circuit and only the focus detection pixel FPx is a differential circuit.

  As described above, the imaging device 101 according to the present embodiment can improve the focus detection accuracy by improving the SN ratio of the focus detection signal output from the focus detection pixel FPx.

  As described above, the focus detection apparatus according to the present invention has been described by way of example in the embodiment, but can be implemented in various other forms without departing from the spirit or main features thereof. Therefore, the above-described embodiment is merely an example in all respects and should not be interpreted in a limited manner. The present invention is defined by the claims, and the present invention is not limited to the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

DESCRIPTION OF SYMBOLS 101 ... Imaging device; 102 ... Vertical scanning circuit; 103 ... Horizontal output circuit; 104 ... Output amplifier; Px ... Imaging pixel; FPx ... Focus detection pixel; VLs (1) to VLs (4), VLd (2), VLd (3): vertical signal line; Pws (1) to Pws (4), Pwd (2), Pwd (3): current source; Vdd: positive power source; Vss: negative power source; φRn, φSELn, φRp, φSELp ... Timing signal; PD, PDf ... photodiode; SFn, Rn, SELn ... NMOS transistor; SFp, Rp, SELp ... PMOS transistor

Claims (7)

A first focus detection pixel that outputs the first focus detection signal by entering the pupil-divided first light flux and a second light flux that forms a pair with the first light flux are incident and a second focus detection signal is output. In a focus detection device having a second focus detection pixel,
The first focus detection pixel and the second focus detection pixel are:
A photoelectric conversion unit that accumulates electrons and holes according to the amount of incident light; and
An electronic reading unit that reads an electrical signal corresponding to the amount of electrons accumulated in the photoelectric conversion unit;
A focus detection apparatus comprising: a hole reading unit that reads out an electrical signal corresponding to the amount of holes accumulated in the photoelectric conversion unit. The focus detection apparatus according to claim 1,
A differential output circuit for outputting the first focus detection signal and the second focus detection signal, which uses two electrical signals read from the electronic readout unit and the hole readout unit as differential signals; A focus detection device. The focus detection apparatus according to claim 1 or 2,
In the first focus detection pixel and the second focus detection pixel, in the case of a right opening, the electron reading portion and the hole reading portion are arranged in the left light shielding portion, and in the case of the left opening, the right light shielding portion. The focus detection device is characterized in that the electronic readout unit and the positive hole readout unit are arranged in a frame. In the focus detection apparatus according to any one of claims 1 to 3,
A plurality of imaging pixels for capturing an image are provided,
The focus detection apparatus, wherein the first focus detection pixel and the second focus detection pixel are arranged at some pixel positions of the plurality of imaging pixels. The focus detection apparatus according to claim 4,
The imaging pixel includes an imaging photoelectric conversion unit that accumulates either electrons or holes according to the amount of incident light, and an electrical signal according to the amount of electrons or holes accumulated in the imaging photoelectric conversion unit. A focus detection device that outputs a single-end signal read from the imaging readout unit as an imaging signal. The focus detection apparatus according to claim 4 or 5,
The imaging photoelectric conversion unit is laid out at a position having a maximum area in the imaging pixel, and the photoelectric conversion unit of the first focus detection pixel and the second focus detection pixel is divided into a left opening or a right opening for pupil division A focus detection apparatus laid out at a position having a maximum area in any of the sections. In the focus detection apparatus according to any one of claims 1 to 6,
The electron reading unit includes an NMOS type reset transistor that resets electrons accumulated in the photoelectric conversion unit, an NMOS type amplification transistor that converts an electric signal according to the amount of electrons, and the electric signal as a negative electric signal. It consists of an NMOS type select transistor that outputs from the pixel,
The hole readout unit includes a PMOS type reset transistor that resets holes accumulated in the photoelectric conversion unit, a PMOS type amplification transistor that converts the electrical signal according to the amount of holes, and the electrical signal to be positive. A focus detection device comprising a PMOS type selection transistor that outputs an electrical signal from a pixel.

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