JP2014042037A - Electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a chip component structure easy for structuring and mounting, and having absolute necessary mounting strength and electric characteristics, and capable of suppressing the occurrence of a vibration sound.SOLUTION: Upper surface electrodes 1211 and 1221 are formed on one main surface on which a laminate ceramic capacitor 11 is mounted in an insulating substrate 120 of an interposer 12. The insulating substrate 120 is formed with almost the same shape as the laminate ceramic capacitor 11 to be mounted when viewed in a direction orthogonal to the main surface, and the laminate ceramic capacitor 11 is mounted such that their lengthwise directions are almost coincident. Notches Cd11, Cd12, Cd13 and Cd14 having side via electrodes are formed at four corners when viewed from a direction orthogonal to the main surface in the insulating substrate 120. The upper surface electrodes 1211 and 1221 on the main surface are respectively connected via the side via electrodes to lower surface electrodes 1212 and 1222 formed on the other main surface connected to a circuit board.

Description

  The present invention generally relates to an electronic component having an interposer, which is used when a chip component such as a multilayer ceramic capacitor is mounted on a circuit board.

  Currently, chip components, particularly small multilayer ceramic capacitors, are widely used for mobile terminals such as mobile phones. The multilayer ceramic capacitor is composed of a rectangular component body that functions as a capacitor, and external electrodes formed at opposite ends of the component body.

  Conventionally, generally, as shown in Patent Document 1, in a multilayer ceramic capacitor, an external electrode is directly placed on a mounting land of a circuit board of a mobile terminal, and the mounting land and the external electrode are soldered or the like. It was electrically and physically connected to the circuit board by bonding with a bonding agent.

  However, mechanical distortion may occur in the multilayer ceramic capacitor due to a voltage change that occurs in an electronic circuit including the multilayer ceramic capacitor. When the distortion occurs, the distortion is transmitted to the circuit board, and the circuit board vibrates. When the circuit board vibrates, a vibration sound that can be heard by human ears may be generated.

  As a configuration for solving this problem, for example, Patent Documents 2 and 3 describe that a multilayer ceramic capacitor is not directly mounted on a mounting land. In Patent Documents 2 and 3, an interposer made of an insulating substrate is used. When an interposer is used, the multilayer ceramic capacitor is bonded to the upper electrode of the interposer, and the lower electrode of the interposer is bonded to the mounting electrode of the circuit board. The upper surface electrode and the lower surface electrode are electrically connected by a via hole penetrating the interposer.

JP-A-8-55752 JP-A-7-11380 JP 2004-134430 A

  However, in the configuration of the above-mentioned Patent Document 2, the component substrate is overlaid on the support substrate and bonded with a bonding material, and then a solder resist is formed only on the side surface of the component substrate, and solder when mounted on the circuit substrate. Prevents the component board from getting wet. That is, the solder at the time of mounting wets to the side surface of the support substrate, but does not adhere to the external electrodes of the component substrate, so that the component substrate is not strongly restrained. As a result, even if the component board vibrates, it is possible to suppress the vibration from propagating to the circuit board or the like via the support board. However, with this structure, after bonding the component substrate to the support substrate with a bonding material, it is necessary to form a solder resist only on the side surface of the component substrate, which may increase manufacturing costs.

  Further, in the configuration of Patent Document 3, the arrangement direction of the lower electrode in the interposer and the arrangement direction of the upper electrode intersect, that is, the arrangement direction of the external electrodes of the multilayer ceramic capacitor and the arrangement of the mounting electrodes on the circuit board of the interposer A special structure is used in which the directions intersect. Therefore, the interposer is increased in size, the electrode shape of the interposer is complicated, and the cost may be further increased.

  Therefore, the object of the present invention is to realize an electronic component that is easy to design and mount, has the same mounting strength and electrical characteristics as a conventional general mounting structure, and can more effectively suppress the generation of vibration noise. There is to do.

  The present invention provides a flat insulating substrate, a first upper surface electrode formed on one main surface of the insulating substrate, and a second upper surface electrode formed on the insulating substrate along a direction perpendicular to the one main surface. A substrate having a plurality of connection electrodes connected to the first upper surface electrode or the second upper surface electrode, and a first external electrode and a second external electrode facing each of both ends in the longitudinal direction of the main body, The present invention relates to an electronic component including: a multilayer ceramic capacitor in which one external electrode is mounted on a first upper surface electrode and a second external electrode is mounted on the second upper surface electrode. In this electronic component, when the multilayer ceramic capacitor is mounted, the insulating substrate is formed with an outer shape smaller than the outer shape of the multilayer ceramic capacitor when viewed from the direction orthogonal to the main surface, and the connection electrode is When viewed from the direction perpendicular to the main surface, it overlaps with the multilayer ceramic capacitor.

  In this configuration, when an electronic component composed of a chip component and a substrate is bonded to a circuit board, a bonding member such as solder (hereinafter, representatively described as an example of solder) is used.

  At this time, depending on the amount of solder supplied, a large amount of solder may wet the electronic component. If the solder spreads to the center of the end surface of the chip component through the insulating substrate, both ends of the chip component are strongly restrained, and the vibration of the chip component is easily transmitted to the circuit substrate through the insulating substrate. May produce sound. However, if the structure of the present invention is used, even if the solder wets from the electronic component and reaches the first and second external electrodes of the chip component, it adheres to the bottom surface side of the chip component and the solder is near the center of the external electrode. Adhering to is regulated. Thereby, generation | occurrence | production of the above-mentioned vibration sound can be suppressed.

  Furthermore, since the electronic component has a structure in which a flat insulating substrate is simply added to the chip component, it is possible to reduce the height and obtain the same bonding strength as in the prior art. In addition, since no special structure is required, it is possible to easily change parts and design.

  The electronic component according to the present invention satisfies the relationship LiA <Lci when the length of the insulating substrate in the length direction is LiA and the length of the multilayer ceramic capacitor in the length direction is Lci. When the width of the insulating substrate in the width direction orthogonal to the direction is WiA and the width of the multilayer ceramic capacitor in the length direction is Wci, it is preferable to satisfy the relationship of WiA <Wci.

  In the electronic component of the present invention, it is preferable that at least one notch is formed in the insulating substrate, and a connection electrode is formed on the inner wall surface of the notch.

  In the electronic component of the present invention, it is preferable that the cutout portion overlaps at least one of the first external electrode and the second external electrode when viewed from a direction orthogonal to the one main surface.

  If a chip component such as a multilayer ceramic capacitor is mounted on a circuit board using the electronic component shown in the present invention, the generation of vibration noise can be suppressed. Furthermore, the structure is simple and the size can be reduced, and the mounting structure on the circuit board becomes easy. Further, it is possible to ensure mounting strength and electrical characteristics equivalent to those of a conventional general mounting structure.

1 is a three-view diagram illustrating a configuration of an electronic component 10 including an interposer 12 according to a first embodiment, and a diagram illustrating a shape relationship between the interposer 12 and the multilayer ceramic capacitor 11. FIG. It is a trihedral view of the interposer 12 according to the first embodiment. FIG. 3 is a three-side view of the electronic component 10 according to the first embodiment mounted on a circuit board 20. It is a figure which shows the sound pressure level-frequency characteristic by the structure of 1st Embodiment, and the conventional structure. It is a figure which shows the three-plane figure which shows the structure of 10 A of electronic components containing 12 A of interposers which concern on 2nd Embodiment, and the relationship of the shape of 12 A of interposers, and the multilayer ceramic capacitor. FIG. 6 is a three-sided view in a state where an electronic component 10A according to a second embodiment is mounted on a circuit board 20; It is a figure which shows the three-plane figure which shows the structure of the electronic component 10B containing the interposer 12B which concerns on 3rd Embodiment, and the relationship of the shape of the interposer 12B and the multilayer ceramic capacitor 11. FIG. It is a three-view figure which shows the structure of 10 C of electronic components containing the interposer 12C which concerns on 4th Embodiment. It is a three-plane figure which shows the structure of electronic component 10D containing interposer 12D which concerns on 5th Embodiment. It is a three-plane figure which shows the structure of the electronic component 10E containing the interposer 12E which concerns on 6th Embodiment. It is a three-plane figure which shows the structure of the electronic component 10F containing the interposer 12F which concerns on 7th Embodiment. It is a trihedral view showing the configuration of an electronic component 10G including an interposer 12G according to the eighth embodiment. It is a three-view figure which shows the structure of the electronic component 10H containing the interposer 12H which concerns on 9th Embodiment. It is a three-view figure which shows the structure of the electronic component 10K containing the interposer 12K which concerns on 10th Embodiment. It is a three-view figure which shows the structure of 10 L of electronic components containing the interposer 12L which concerns on 11th Embodiment. FIG. 10 is a three-sided view illustrating a state in which an electronic component 10J according to another embodiment is mounted on a circuit board 200.

  An electronic component including an interposer according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a three-view diagram illustrating a configuration of an electronic component 10 including an interposer 12 according to the present embodiment, and a diagram illustrating a shape relationship between the interposer 12 and the multilayer ceramic capacitor 11. FIG. 2 is a three-side view of the interposer 12 according to this embodiment. FIG. 3 is a three-side view showing a state in which the electronic component 10 according to the present embodiment is mounted on the circuit board 200. 1, 2, and 3, each view (A) is a plan view, each view (B) is a length side view, and each view (C) is a width side view. Yes. Here, the plan view is a view of the interposer 12 or the electronic component 10 as viewed from the upper surface side. The side view in the length direction shows that the interposer 12 or the electronic component 10 is orthogonal to the direction in which intermediate connection electrodes (hereinafter referred to as “IP electrodes”) 121 and 122 of the interposer 12 are arranged. It is the figure seen from the direction parallel to a surface (mounting surface of the multilayer ceramic capacitor 11). Further, the side view in the width direction shows that the interposer 12 or the electronic component 10 is parallel to the direction in which the IP electrodes 121 and 122 of the interposer 12 are arranged, and is on the main surface of the interposer 12 (mounting surface of the multilayer ceramic capacitor 11). It is the figure seen from the parallel direction. Although hatching is performed in each figure, these are intended to facilitate identification of each part and do not show a cross-sectional view. In addition, it describes similarly also in each following figure, and when it is sectional drawing, it shows that it is sectional drawing each time.

  The multilayer ceramic capacitor 11 corresponds to a “chip component” of the present invention, and includes a component main body 110. The component main body 110 is formed by laminating a predetermined number of dielectric layers and inner electrode layers and firing. The multilayer ceramic capacitor 11 has an external electrode 111 (corresponding to the “first external electrode” in the present invention) formed at one end in the length direction of the component main body 110 (the horizontal direction of the drawing shown in FIG. 1A). The external electrode 112 (corresponding to the “second external electrode” of the present invention) is formed at the opposite end. The external electrodes 111 and 112 are formed by firing a predetermined conductive paste, and the surface thereof is tin-plated. Hereinafter, the direction in which the external electrodes 111 and 112 are arranged is defined as the length direction of the multilayer ceramic capacitor 11, and the direction perpendicular to the length direction and parallel to the mounting surface on which the multilayer ceramic capacitor 11 is mounted is defined as the multilayer ceramic capacitor. 11 will be described as the width direction.

  The external electrodes 111 and 112 are formed so as to spread not only from both end surfaces in the length direction of the component body 110 but from both end surfaces in the length direction to both end surfaces in the width direction, the top surface, and the bottom surface.

  The multilayer ceramic capacitor 11 thus formed has, for example, a length × width of 3.2 mm × 1.6 mm, 2.0 mm × 1.25 mm, 1.6 mm × 0.8 mm, 1.0 mm × 0. It is formed with dimensions of 5 mm, 0.6 mm × 0.3 mm, and the like.

  The interposer 12 corresponds to a “substrate” of the present invention, and includes an insulating substrate 120 as shown in FIG. The insulating substrate 120 has a thickness of about 0.5 mm to about 1.0 mm, for example, and is made of an insulating resin. The insulating substrate 120 is formed in a substantially rectangular shape similar to the multilayer ceramic capacitor 11 when viewed from the direction orthogonal to the main surface. The insulating substrate 120 has notches Cd11, Cd12, Cd13, and Cd14 formed in a shape in which four corners are recessed toward the center of the main surface when viewed from a direction orthogonal to the main surface. At this time, the notches Cd11, Cd12, Cd13, and Cd14 have a shape that is notched at a predetermined radius R around each corner of the rectangular insulating substrate 120 when viewed from the direction orthogonal to the main surface. Is formed. Such notches Cd11, Cd12, Cd13, and Cd14 are points where four adjacent insulating substrates 120 contact each other when the individual insulating substrates 120 are divided from the base substrate on which the plurality of insulating substrates 120 are arranged. It can be easily formed by forming a cylindrical through-hole and then cutting and dividing it so as to pass through the through-hole forming portion.

  The insulating substrate 120 is formed such that the length and width in plan view are slightly larger than the length and width of the multilayer ceramic capacitor 11 to be mounted. That is, as shown in FIG. 1D, when the length of the multilayer ceramic capacitor 11 is Lci and the length of the insulating substrate 120 (interposer 12) is Li, Li≈Lci and Li> Lci. To do. Similarly, when the width of the multilayer ceramic capacitor 11 is Wci and the width of the insulating substrate 120 (interposer 12) is Wi, Wi≈Wci and Wi> Wci.

  At this time, the central portion of the curved surface that defines the notches Cd11, Cd12, Cd13, and Cd14 is formed so as to fall within the outer shape range of the mounted multilayer ceramic capacitor 11.

  Upper surface electrodes 1211 and 1221 are formed on one main surface of the insulating substrate 120 on which the multilayer ceramic capacitor 11 is mounted. The upper surface electrodes 1211 and 1221 are formed apart from each other. The upper surface electrode 1211 corresponds to the “first upper surface electrode” of the present invention, and the upper surface electrode 1221 corresponds to the “second upper surface electrode” of the present invention.

  Upper surface electrode 1211 is formed in a region at one end in the length direction of one main surface. At this time, when the multilayer ceramic capacitor 11 is mounted on one main surface of the interposer 12 (insulating substrate 120) so that the length directions of the top electrode 1211 substantially coincide with each other, The formation dimension of the electrode with respect to the length direction is set so as to include a region where the bottom surface of the external electrode 111 is in contact. The upper surface electrode 1211 is formed over the entire width in the width direction.

  The upper surface electrode 1221 is formed in the other end region in the length direction of the one main surface. At this time, when the multilayer ceramic capacitor 11 is mounted on the one main surface of the interposer 12 (insulating substrate 120) so that the length directions of the top electrode 1221 are substantially coincident with each other, The formation dimension of the electrode in the length direction is set so as to include a region where the bottom surface of the external electrode 112 is in contact. The upper surface electrode 1221 is formed over the entire width in the width direction.

  Lower surface electrodes 1212 and 1222 are formed on the other main surface of the insulating substrate 120 opposite to the side on which the multilayer ceramic capacitor 11 is mounted. The lower surface electrodes 1212 and 1222 are formed apart from each other. The lower electrode 1212 corresponds to the “first lower electrode” of the present invention, and the lower electrode 1222 corresponds to the “second lower electrode” of the present invention.

  The lower surface electrode 1212 is formed in a region of one end in the length direction of the other main surface of the insulating substrate 120 so as to substantially face the upper surface electrode 1211. The lower surface electrode 1222 is formed in a shape substantially opposite to the upper surface electrode 1221 in the region of the other end in the length direction of the other main surface of the insulating substrate 120. At this time, the lower surface electrodes 1212 and 1222 are formed so that the electrodes are present at positions overlapping the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 to be mounted as viewed from the direction orthogonal to the main surface. More preferred.

  The upper surface electrode 1211 and the lower surface electrode 1212 formed at one end in the length direction of the insulating substrate 120 are connected to each other by connection electrodes 401 and 402 formed on the wall surfaces of the notches Cd11 and Cd12. The upper surface electrode 1211, the lower surface electrode 1212, the connection electrode 401 of the notch Cd11, and the connection electrode 402 of the notch Cd12 form the above-described IP electrode 121.

  The upper surface electrode 1221 and the lower surface electrode 1222 formed at the other end in the length direction of the insulating substrate 120 are connected by connection electrodes 403 and 403 formed on the wall surfaces of the notches Cd13 and Cd14, respectively. The upper electrode 1221, the lower electrode 1222, the connection electrode 403 of the notch Cd13, and the connection electrode 404 of the notch Cd14 form the IP electrode 122 described above.

  When the multilayer ceramic capacitor 11 is mounted on such an interposer 12, the upper electrode 1211 of the IP electrode 121 of the interposer 12 and the external electrode 111 of the multilayer ceramic capacitor 11 are re-plated with tin plating of the external electrode 111. Electrically and mechanically connected by melting. Further, the upper electrode 1221 of the IP electrode 122 of the interposer 12 and the external electrode 112 of the multilayer ceramic capacitor 11 are electrically and mechanically connected by remelting tin plating of the external electrode 112. If tin plating is performed on the IP electrodes 121 and 122 in advance, the IP electrodes 121 and 122 are connected including the tin plating. By using tin plating in this way, it is possible to join with the minimum necessary amount, and to restrain the vicinity of the center of the external electrode of the chip component as much as possible. Thereby, the electronic component 10 is formed. The multilayer ceramic capacitor 11 and the interposer 12 may be joined with substantially the same amount of solder without using the tin plating of the external electrodes 111 and 112 or the tin plating of the interposer 12.

  The electronic component 10 is mounted on the circuit board 20 as shown in FIG. At this time, the mounting is performed so that the lower surface electrode 1212 of the IP electrode 121 of the interposer 12 is connected to the mounting land 201 of the circuit board 20 and the lower surface electrode 1222 of the IP electrode 122 of the interposer 12 is connected to the mounting land 202. Is done. Solder 300 is used to connect the IP electrodes 121 and 122 of the interposer 12 and the mounting lands 201 and 202 of the circuit board 20.

  In such joining by the solder 300, solder joining is performed so that a solder fillet is formed at least from the mounting lands 201, 201 of the circuit board 20 to the connection electrodes 401-404 of the interposer 12. By forming the fillet in this way, it is very effective because it can prevent floating when the electronic component 10 is mounted, can secure the bonding strength, and can visually confirm that the soldering is surely performed. It is.

  Note that a material other than the solder 300 may be used as long as the bonding agent has wettability and conductivity.

  When joining with such solder 300 is performed, when a large amount of solder is supplied, the solder electrodes are connected to each other through the connection electrodes 401-404 rather than forming the solder fillets with the connection electrodes 401-404 of the IP electrodes 121, 122. The solder 300 may rise up to the upper surface side of the positioner 12.

  However, in the configuration of the present embodiment, the connection electrodes 401-404 are formed only at the four corners of the interposer 12, and the notches Cd11, Cd12, Cd13, Cd14 in which the connection electrodes 401-404 are formed have the main parts. This coincides with the four corners of the multilayer ceramic capacitor 11 viewed from the direction orthogonal to the plane, that is, the positions of the four ridge lines extending in the direction orthogonal to the main surface of the external electrodes 111 and 112. With this configuration, as shown in FIG. 3, the solder 300 extends from the lower ends of the four ridge lines of the external electrodes 111 and 112 corresponding to the notches Cd11, Cd12, Cd13, and Cd14 near the four corners to the four ridge lines. It adheres along. Thereby, the solder 300 does not adhere to the vicinity of the center of the end surfaces of the external electrodes 111 and 112, and generation of vibration noise due to the distortion of the multilayer ceramic capacitor 11 as described above can be effectively suppressed.

  FIG. 4 is a diagram showing sound pressure level-frequency characteristics according to the configuration of the present embodiment and the conventional configuration. The conventional configuration in FIG. 4 is a configuration in which a multilayer ceramic capacitor is directly mounted on a circuit board without using an interposer (mode T0), and a configuration in which the end surface center of the external electrode is soldered mainly over the entire end surface while using the interposer. (Aspect I0). As shown in FIG. 4, by using the configuration of the present embodiment, the sound pressure level of the vibration sound can be significantly suppressed in a wide frequency band as compared with the conventional aspect T0. Similarly, the sound pressure level of the vibration sound can be effectively suppressed as compared with the conventional mode I0.

  Furthermore, by using the interposer 12 made of the insulating substrate 120 having a thin plate thickness as in this embodiment, the height of the electronic component 10 can be suppressed and the height can be reduced. In addition, since the multilayer ceramic capacitor 11 and the interposer 12 are stacked and mounted so that the main surfaces thereof coincide with the circuit board 20, high bonding strength can be realized. As a result, substantially the same bonding strength as when the multilayer ceramic capacitor 11 is directly mounted on the circuit board 20 can be obtained.

  Furthermore, in the above-described embodiment, the mounting lands 201 and 202 have the same specifications and the same intervals as the case where the multilayer ceramic capacitor 11 is directly mounted.

  As described above, the electronic component 10 of the present embodiment has the positions of the IP electrodes 121 and 122 of the interposer 12 and the positions of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 when viewed from the direction orthogonal to the main surface. Since the connection electrodes 401-404 are present at substantially the same positions as the four ridge lines of the external electrodes 111, 112 of the multilayer ceramic capacitor 11, the mounting lands 201, 202 have the same specifications as when the multilayer ceramic capacitor 11 is directly mounted. The electronic component 10 can be mounted as it is. That is, it is not necessary to change the design of the mounting lands 201 and 202 of the circuit board 20. Furthermore, it is possible to mount the electronic component 10 with substantially the same area as when the monolithic ceramic capacitor 11 is mounted on the circuit board 20. Thereby, even if the interposer 12 is used, the multilayer ceramic capacitor 11 can be connected to the circuit board 20 with almost no increase in size in plan view.

  Next, an electronic component according to a second embodiment will be described with reference to the drawings. FIG. 5A to FIG. 5C are three views showing the configuration of the electronic component 10A including the interposer 12A according to this embodiment. FIG. 5D is a diagram showing a shape relationship between the interposer 12 </ b> A and the multilayer ceramic capacitor 11. FIG. 6 is a three-side view of the electronic component 10 </ b> A according to this embodiment mounted on the circuit board 20.

  The basic configuration of the interposer 12A of this embodiment is the same as that of the interposer 12 shown in the first embodiment, but the length and width are different.

  As shown in FIG. 5D, the length LiA of the interposer 12A, that is, the insulating substrate 120A is slightly shorter than the length Lci of the multilayer ceramic capacitor 11. That is, LiA≈Lci and LiA <Lci. The width of the interposer 12A, that is, the insulating substrate 120A is substantially the same as the width of the multilayer ceramic capacitor 11 and is short. That is, WiA≈Wci and WiA <Wci.

  In such a configuration, when solder joining to the circuit board 20 similar to that of the first embodiment is performed, when a large amount of solder is supplied, the solder 300 is notched portion Cd11A as shown in FIG. , Cd12A, Cd13A, and Cd14A (connection electrodes 401A, 402A, 403A, and 404A) are attached along the four ridge lines from the lower ends of the four ridge lines of the external electrodes 111 and 112, respectively. Thereby, the solder 300 does not adhere to the vicinity of the center of the end surfaces of the external electrodes 111 and 112, and generation of vibration noise due to the distortion of the multilayer ceramic capacitor 11 as described above can be effectively suppressed.

  Further, in the configuration of the present embodiment, the same mounting land as that used when mounting the monolithic ceramic capacitor 11 on the circuit board 20 can be used. Also, the electronic component 10 can be mounted with the same area as when the multilayer ceramic capacitor 11 is mounted alone. Thereby, even if the interposer 12 is used, further downsizing is possible.

  Next, an electronic component according to a third embodiment will be described with reference to the drawings. FIG. 7A to FIG. 7C are three views showing the configuration of the electronic component 10B including the interposer 12B according to the present embodiment. FIG. 7D is a diagram showing a shape relationship between the interposer 12 </ b> B and the multilayer ceramic capacitor 11.

  As shown in FIG. 7D, the interposer 12B of the present embodiment has a structure in which the length and width are larger than the interposer 12 shown in the first embodiment. Specifically, when the length of the interposer 12B is LiB and the width is WiB, LiB> Lci and WiB> Wci.

  In the interposer 12B, the notches Cd11B, Cd12B, Cd13B, and Cd14B are formed so as to be linear when viewed from the direction orthogonal to the main surface. The notches Cd11B, Cd12B, Cd13B, and Cd14B are formed in a shape that does not enter the inside of the outer shape of the multilayer ceramic capacitor 11 when viewed from the direction orthogonal to the main surface. Even in such a shape, the connection electrodes 401B, 402B, 403B, and 404B formed in the notches Cd11B, Cd12B, Cd13B, and Cd14B are connected to the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 with respect to the external electrodes 111 and 112. It is closest to the end portion on the side of the interposer 12B of the four ridges extending in the direction orthogonal to the main surface of the electrodes 111, 112. Thereby, even if the solder gets wet through the connection electrodes 401B, 402B, 403B, and 404B and adheres to the external electrodes 111 and 112, it adheres only to the vicinity of the four ridges of the external electrodes 111 and 112. Therefore, the generation of vibration noise can be suppressed as in the above-described embodiments.

  Furthermore, the upper surface electrode 1211B of the IP electrode 121B of the interposer 12B is configured by partial upper surface electrodes 1211LB and 1211RB formed to be separated along the width direction. That is, an electrode separation portion 500 (corresponding to “contact restricting means” of the present invention) sandwiched between the partial upper surface electrodes 1211LB and 1211RB is formed on the upper surface of the interposer 12B. These partial upper surface electrodes 1211LB and 1211RB are formed in a range including the positions of the two ridge lines of the external electrode 111.

  The upper surface electrode 1221B of the IP electrode 122B of the interposer 12B includes partial upper surface electrodes 1221LB and 1221RB that are formed apart from each other along the width direction. That is, an electrode separation portion 500 (corresponding to “contact restricting means” of the present invention) sandwiched between the partial upper surface electrodes 1221LB and 1221RB is formed on the upper surface of the interposer 12B. These partial upper surface electrodes 1221LB and 1221RB are formed within a range including the positions of the two ridge lines of the external electrode 112.

  With such a configuration, the upper surface electrode is not formed near the center in the width direction (electrode separation portion 500) on the end surfaces of the external electrodes 111 and 112, and the width direction on the end surfaces of the external electrodes 111 and 112 is not formed. Solder adhesion near the center can be prevented. Thereby, generation | occurrence | production of a vibration sound can be suppressed more reliably.

  In FIG. 7, the bottom electrodes of the IP electrodes 121B and 122B are not separated in the width direction, but may be separated.

  An electronic component according to a fourth embodiment will be described with reference to the drawings. FIG. 8 is a three-side view showing the configuration of an electronic component 10C including the interposer 12C according to this embodiment.

  The interposer 12C of the present embodiment has an upper surface electrode formed over the entire width of the interposer 12C, and other configurations are the same as the interposer 12B shown in the third embodiment.

  The upper surface electrode 1211C of the IP electrode 121C of this embodiment is formed over the entire width of the interposer 12C. The upper surface electrode 1221C of the IP electrode 122C is also formed over the entire width of the interposer 12C.

  Even in such a configuration, as shown in the third embodiment, the connection electrodes 401C, 402C, 403C, and 404C formed in the notches Cd11C, Cd12C, Cd13C, and Cd14C are not formed in the multilayer ceramic capacitor 11. The outer electrodes 111 and 112 are closest to the interposer 12C side end portion of the four ridges extending in the direction orthogonal to the main surface of the outer electrodes 111 and 112. As a result, even if the solder wets through the connection electrodes 401C, 402C, 403C, and 404C and adheres to the external electrodes 111 and 112, it adheres only to the vicinity of the four ridge lines of the external electrodes 111 and 112. Therefore, the generation of vibration noise can be suppressed as in the third embodiment.

  Next, an electronic component according to a fifth embodiment will be described with reference to the drawings. FIG. 9 is a trihedral view showing the configuration of an electronic component 10D including the interposer 12D according to the present embodiment.

  The interposer 12D of this embodiment is obtained by forming a solder resist film Re12 on the upper surface electrodes 1211D and 1221D, and the other configuration is the same as that of the interposer 12 shown in the first embodiment.

  The solder resist film Re12 corresponds to the “contact restricting means” of the present invention, and a perpendicular line extending from the center position in the width direction of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 to the upper surface electrodes 1211D and 1221D becomes the upper surface electrodes 1211D and 1221D. It is formed in a range of a predetermined width including a position that is orthogonal. The solder resist film Re12 is also formed in a predetermined length range including the position where the perpendicular is orthogonal to the upper surface electrodes 1211D and 1221D in the length direction of the interposer 12D. Accordingly, the vicinity of the center in the width direction of the external electrodes 111 and 112 is not in contact with the upper surface electrodes 1211D and 1221D of the IP electrodes 121D and 122D.

  Therefore, as described above, even if the solder wets the upper surface electrodes 1211D and 1221D, the solder resist film Re12 does not adhere to the vicinity of the center. Thereby, generation | occurrence | production of a vibration sound can be suppressed more reliably.

  Next, an electronic component according to a sixth embodiment will be described with reference to the drawings. FIG. 10 is a three-plane view showing the configuration of an electronic component 10E including the interposer 12E according to this embodiment. In FIG. 10, the illustration of the multilayer ceramic capacitor 11 is simplified in order to clearly show the structure of the interposer 12E.

  The interposer 12E of the present embodiment is different from the third embodiment in the formation positions of the notches Cd61 and Cd62, and the other configurations are the same as the interposer 12B shown in the third embodiment. The same.

  The upper surface electrode 1211E of the IP electrode 121E of the interposer 12E includes partial upper surface electrodes 1211LE and 1211RE that are spaced apart along the width direction of the interposer 12E, that is, the insulating substrate 120E. That is, an electrode separation portion 501 sandwiched between the partial upper surface electrodes 1211LE and 1211RE is formed on the upper surface of the interposer 12E. In the electrode separation portion 501, the upper surface of the insulating substrate 120E of the interposer 12E and the external electrode 111 of the multilayer ceramic capacitor 11 directly face each other. The partial upper surface electrodes 1211LE and 1211RE are connected by connection electrodes formed near one end in the length direction of the insulating substrate 120E and closer to the end than the position where the external electrode 111 of the multilayer ceramic capacitor 11 is placed. Has been.

  The notch Cd61 is an end surface of the insulating substrate 120E on the side where the IP electrode 121E is formed, and is formed at a substantially central position in the width direction of the insulating substrate 120E. The shape of the notch Cd61 is an arc shape when viewed from the direction orthogonal to the main surface, like the notches Cd11, Cd12, Cd13, and Cd14 shown in the first embodiment. . A connection electrode 411E is formed on the wall surface of the notch Cd61, and is connected to the partial upper surface electrodes 1211LE and 1211RE via the electrodes connecting the partial upper surface electrodes 1211LE and 1211RE.

  The upper surface electrode 1221E of the IP electrode 122E of the interposer 12E includes partial upper surface electrodes 1221LE and 1221RE that are spaced apart along the width direction of the interposer 12E, that is, the insulating substrate 120E. In other words, an electrode separation portion 501 sandwiched between the partial upper surface electrodes 1221LE and 1221RE is formed on the upper surface of the interposer 12E. In the electrode separation portion 501, the upper surface of the insulating substrate 120E of the interposer 12E and the external electrode 112 of the multilayer ceramic capacitor 11 directly face each other. The partial upper surface electrodes 1221LE and 1221RE are connected by connection electrodes formed near the other end in the length direction of the insulating substrate 120E and on the end side from the position where the external electrode 112 of the multilayer ceramic capacitor 11 is placed. Has been.

  The notch Cd62 is an end surface of the insulating substrate 120E on the side where the IP electrode 122E is formed, and is formed at a substantially central position in the width direction of the insulating substrate 120E. Similarly to the notch Cd61, the shape of the notch Cd62 is an arc shape when viewed from the direction orthogonal to the main surface. A connection electrode 412E is formed on the wall surface of the notch Cd62, and is connected to the partial upper surface electrodes 1221LE and 1221RE via the electrodes connecting the partial upper surface electrodes 1221LE and 1221RE.

  By adopting such a configuration, even when the notches Cd61 and Cd62 provided with the connection electrodes 411E and 412E, respectively, are installed at the center in the width direction of the interposer 12E, the top surface is provided as described in the above embodiments. The solder wetted on the electrodes 121E and 122E adheres to the vicinity of the four ridge lines of the external electrodes 111 and 112, and does not adhere to the vicinity of the center in the width direction. Thereby, like the above-mentioned each embodiment, generation | occurrence | production of a vibration sound can be suppressed and there can exist each above-mentioned effect.

  Next, an electronic component according to a seventh embodiment will be described with reference to the drawings. FIG. 11 is a trihedral view showing the configuration of the electronic component 10F including the interposer 12F according to the present embodiment. In FIG. 11, the multilayer ceramic capacitor 11 is simplified in order to clearly show the structure of the interposer 12F.

  The interposer 12F according to the present embodiment is formed by forming upper surface electrodes 1211F and 1221F so as to cover substantially the entire width of the insulating substrate 120F with respect to the interposer 12E shown in the sixth embodiment. The formation parts 131F and 132F are provided, and the other configurations are the same.

  The electrode non-forming portion 131F is formed in a range of a predetermined width including a position where a perpendicular extending from the center position in the width direction of the external electrode 111 of the multilayer ceramic capacitor 11 to the upper surface electrode 1211F is orthogonal to the upper surface electrode 1211F. The electrode non-forming portion 131F is formed in a predetermined length range including a position where the perpendicular is orthogonal to the upper surface electrode 1211F in the length direction of the interposer 12F, that is, the length direction of the insulating substrate 120F. In other words, an electrode opening pattern is formed near the center in the width direction of the external electrode 111 on the upper surface of the interposer 12F. Thus, the vicinity of the center in the width direction of the external electrode 111 is not in contact with the upper surface electrode 1211F of the IP electrode 121F.

  Similarly, the electrode non-forming portion 132F is formed in a range of a predetermined width including a position where a perpendicular line extending from the center position in the width direction of the external electrode 112 of the multilayer ceramic capacitor 11 to the upper surface electrode 1221F is orthogonal to the upper surface electrode 1221F. . The electrode non-forming portion 132F is formed in a range of a predetermined length including the position where the perpendicular is orthogonal to the upper surface electrode 1221F in the length direction of the interposer 12F, that is, the length direction of the insulating substrate 120F. In other words, an electrode opening pattern is formed near the center in the width direction of the external electrode 112 on the upper surface of the interposer 12F. Thereby, the vicinity of the center in the width direction of the external electrode 112 is not in contact with the upper surface electrode 1221F of the IP electrode 122F.

  For this reason, as described above, even if the solder wets the upper surface electrodes 1211F and 1221F via the connection electrodes 411F and 412F, the non-electrode forming portions 131F and 132F do not adhere to the vicinity of the center of the external electrodes 111 and 112. . Thereby, generation | occurrence | production of a vibration sound can be suppressed.

  Next, an electronic component according to an eighth embodiment will be described with reference to the drawings. FIG. 12 is a three-view diagram illustrating the configuration of an electronic component 10G including the interposer 12G according to the present embodiment. In FIG. 12, the multilayer ceramic capacitor 11 is simplified to clearly show the structure of the interposer 12G.

  The interposer 12G of the present embodiment is obtained by forming a solder resist film Re12G at the same position as the electrode non-forming portions 131F and 132F shown in the seventh embodiment, and other configurations are the seventh embodiment. Is the same. In this case, in FIG. 12, the upper surface electrode is illustrated as being formed at the position, but the upper surface electrode may or may not be formed at the position. This solder resist film Re12G corresponds to the “contact regulating means” of the present invention.

  In such a configuration, as described above, even if the solder wets the upper surface electrodes 1211G and 1221G via the connection electrodes 411G and 412G, the solder resist film Re12G does not adhere to the vicinity of the center of the external electrodes 111 and 112. . Thereby, generation | occurrence | production of a vibration sound can be suppressed.

  Next, an electronic component according to a ninth embodiment will be described with reference to the drawings. FIG. 13 is a three-view diagram illustrating the configuration of an electronic component 10H including the interposer 12H according to the present embodiment. In FIG. 13, the multilayer ceramic capacitor 11 is simplified to clearly show the structure of the interposer 12H.

  The interposer 12H of this embodiment does not form the electrode non-forming portions 131F and 132F shown in the seventh embodiment, and the upper surface electrodes 1211H and 1221H are formed over substantially the entire width of the insulating substrate 120H. A solder resist film Re12H is formed on the upper surface electrodes 1211H and 1221H. Other configurations are the same as those of the seventh embodiment.

  The solder resist film Re12H is formed in a range of a predetermined width including a position where a perpendicular extending from the center position in the width direction of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 to the upper surface electrodes 1211H and 1221H is orthogonal to the upper surface electrodes 1211H and 1221H. ing. The solder resist film Re12H is also formed in a predetermined length range including the positions where the perpendiculars are orthogonal to the upper surface electrodes 1211H and 1221H with respect to the length direction of the interposer 12H. This solder resist film Re12H corresponds to the “contact regulating means” of the present invention.

  Further, the solder resist film Re12H includes a region where the upper surface electrodes 1211H and 1221H are connected to the connection electrodes 411H and 412H of the notches Cd61 and Cd62, and a region where the upper surface electrodes 1211H and 1221H are in contact with the four ridge lines of the external electrodes 111 and 112. Are formed in such a shape that they are divided when viewed from the direction orthogonal to the main surface of the insulating substrate 120H. For example, as shown in FIG. 13A, it is formed in an arc shape having a center on the cutout portions Cd61 and Cd62 side, passing through the vicinity of the center in the width direction of the external electrodes 111 and 112, and having a predetermined width.

  With such a configuration, even when the solder wets up to the upper surface electrodes 1211H and 1221H via the connection electrodes 411H and 412H as described above, the external electrodes 111 and 112 are completely free of solder due to the solder resist film Re12H. Does not adhere. Thereby, generation | occurrence | production of a vibration sound can be suppressed more reliably.

  Next, an electronic component according to a tenth embodiment will be described with reference to the drawings. FIG. 14 is a three-view diagram illustrating the configuration of an electronic component 10K including the interposer 12K according to the present embodiment. In FIG. 14, the multilayer ceramic capacitor 11 is simplified to clearly show the structure of the interposer 12K.

  The interposer 12K of this embodiment is different from the interposer 12H shown in the ninth embodiment in the shape of the solder resist film Re12K, and the other configurations are the same.

  The solder resist film Re12K is perpendicular to the upper surface electrodes 1211K and 1221K with respect to the longitudinal direction of the interposer 12K. And a shape that reaches both ends in the length direction. This solder resist film Re12K corresponds to the “regulator” of the present invention.

  At this time, the solder resist film Re12K is formed so as to cover the opening ends on the upper surface electrodes 1211K and 1221K side of the notches Cd61 and Cd62 including the connection electrodes 411K and 412K.

  With such a structure, when the electronic component 10K is mounted on the circuit board, even if the solder wets along the connection electrodes 411K and 412K of the notches Cd61 and Cd62, the solder resist film Re12K causes the solder. The wetting up to the upper surface side of the interposer 12K can be blocked. Thereby, it is possible to prevent the solder for mounting on the circuit board from unnecessarily adhering to the upper surface side of the interposer 12K, that is, the external electrodes 111 and 112 of the multilayer ceramic capacitor 11. As a result, the generation of vibration noise can be suppressed as in the above-described embodiments.

  Next, an electronic component according to an eleventh embodiment will be described with reference to the drawings. FIG. 15 is a three-view diagram illustrating the configuration of an electronic component 10L including the interposer 12L according to the present embodiment. In FIG. 15, the multilayer ceramic capacitor 11 is simplified in order to clearly show the structure of the interposer 12L.

  The interposer 12L of this embodiment is different from the interposer 12K shown in the tenth embodiment in the shape of the solder resist film Re12L, and the other configurations are the same.

  Similarly to the interposer 12K of the tenth embodiment, the solder resist film Re12L is formed so as to cover the upper surface electrodes 1211L and 1221L side of the notches Cd61 and Cd62 including the connection electrodes 411L and 412L of the interposer 12L. Has been. However, the solder resist film Re12L of the present embodiment has the end portion on the center side in the length direction up to a position where the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 are in contact with (mounted on) the upper surface electrodes 1211L and 1221L. It is formed in a shape that does not reach. In other words, the solder resist film Re12L is formed in a shape as small as possible while minimizing covering the notches Cd61 and Cd62. This solder resist film Re12L corresponds to the “regulator” of the present invention.

  When the solder resist film Re12L having such a structure is formed, similarly to the interposer 12K shown in the tenth embodiment, the interposer 12L of the present embodiment also has solder for mounting on the circuit board. It is possible to prevent unnecessary attachment to the upper surface side of the interposer 12L, that is, the external electrodes 111 and 112 of the multilayer ceramic capacitor 11. As a result, the generation of vibration noise can be suppressed as in the above-described embodiments.

  Furthermore, by using the structure of the present embodiment, the solder resist film Re12L has a shape that does not extend to the region where the multilayer ceramic capacitor 11 is mounted. Therefore, when the multilayer ceramic capacitor 11 is mounted on the upper surface electrodes 1211L and 1221L, The solder resist film Re12L is not interposed between the bottom surfaces of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 and the top surface electrodes 1211L and 1221L. As a result, the bottom surfaces of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 and the top surface electrodes 1211L and 1221L are reliably in contact with each other without being separated. Therefore, the bonding strength between the bottom surfaces of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11 and the top surface electrodes 1211L and 1221L is improved.

  Note that the solder resist films shown in the tenth and eleventh embodiments are formed only in the center region in the width direction of the interposer, but may be formed over the entire region in the width direction.

  The interposers shown in the tenth embodiment and the eleventh embodiment have a notch formed at the center in the width direction. Even if the portion is provided, the solder resist film can be formed so as to cover the notch. As a result, as in the tenth and eleventh embodiments, unnecessary adhesion of solder to the external electrodes can be prevented.

  In the interposer shown in the tenth embodiment and the eleventh embodiment, the solder resist film is used as an example. However, even if the metal film is formed so as to cover the notch from the upper surface electrode side. Any plate-like member can be used as long as it prevents the solder from getting wet.

  Moreover, although the structure of each above-mentioned embodiment may be used independently, it can also be used combining the structure of several embodiment. Furthermore, if the shape can be inferred based on the configuration of these embodiments, the same effects as those of the above-described embodiments can be obtained.

  In the above-described embodiment, the formation of the electrode non-forming portion and the resist film on the insulating substrate suppresses the solder from adhering to the center of the end surfaces of the external electrodes 111 and 112 of the multilayer ceramic capacitor 11. Such an electrode non-formation portion or a resist film can be formed on the external electrodes 111 and 112.

  FIG. 16 is a three-sided view illustrating a state in which the electronic component 10 </ b> J according to another embodiment is mounted on the circuit board 200.

  The electronic component 10J shown in FIG. 16 is different from the electronic component 10 shown in the first embodiment in the external electrodes of the multilayer ceramic capacitor 11J, and the other configurations are the same.

  As shown in FIG. 16C, the external electrodes 111J and 112J of the multilayer ceramic capacitor 11J of the electronic component 10J have a predetermined area at the end surface in the longitudinal direction of the component body 110, that is, at the center of the formation surface of the external electrodes 111J and 112J. The electrode non-forming part 140 is provided. By adopting such a configuration, it is possible to more reliably prevent solder from attaching to the center of the end surface where the external electrodes 111J and 112J of the component main body 110 are formed. This electrode non-forming portion 140 corresponds to the “joining restricting means” of the present invention.

  In addition, it is possible to suppress the generation of vibration sound even in a configuration in which a non-formed portion is provided on the external electrode or a resist film is formed and directly bonded to the circuit board, but the generation of vibration noise can be suppressed, but the interposer having the above-described configuration is used. As a result, it is possible to more reliably suppress the generation of vibration noise and to suppress the floating during mounting and obtain the stability of the joint.

  FIG. 16 shows an example in which the electrode non-forming portion 140 is provided. However, a resist film may be formed in the region regardless of the presence or absence of the electrode. Furthermore, the structure which forms an external electrode only in a bottom face may be sufficient. Such a configuration similar to FIG. 16 can be combined with the configuration of any of the above-described embodiments.

  In the above description, a multilayer ceramic capacitor is used as a chip component. However, the above configuration can be applied to other chip components that generate similar vibrations.

  The substantially rectangular shape shown in the present invention is not limited to a rectangular shape, but a square, a polygon obtained by cutting off the corners (corners) of these rectangles and squares, and the corners (corners) of the rectangles and squares are curved. Also includes shapes molded into

10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10K, 10L: electronic components,
11, 11J: Multilayer ceramic capacitor,
110: Parts main body,
111, 112, 111J, 112J: external electrodes,
12, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12K, 12L: Interposer,
120, 120A, 120B, 120C, 120D, 120E, 120E, 120G, 120H, 120K, 120L: Insulating substrate,
121, 122, 121A, 122A, 121B, 122B, 121C, 122C, 121D, 122D, 121E, 122E, 121F, 122F, 121G, 122G, 121H, 122H, 121K, 122K, 121L, 122L: IP electrodes,
1211, 1221, 1211A, 1221A, 1211B, 1221B, 1211C, 1221C, 1211D, 1221D, 1211E, 1221E, 1211F, 1221F, 1211G, 1221G, 1211H, 1221H, 1211K, 1221K, 1211L, 1221L: upper surface electrode,
1211LB, 1211RB, 1221LB, 1221RB, 1211LE, 1211RE, 1221LE, 1221RE: partial upper surface electrodes,
1212, 1222: bottom electrode,
131F, 132F: electrode non-formation part,
140: electrode non-formation part (external electrode),
Cd11, Cd12, Cd13, Cd14, Cd11A, Cd12A, Cd13A, Cd14A, Cd11B, Cd12B, Cd13B, Cd14B, Cd11C, Cd12C, Cd13C, Cd14C, Cd11D, Cd12D, Cd13D, Cd14D, Cd14D, Cd14C
Re12, Re12G, Re12H, Re12K, Re12L: solder resist film,
20: circuit board,
201, 202: mounting lands,
401, 402, 403, 404, 401A, 402A, 403A, 404A, 401B, 402B, 403B, 404B, 401C, 402C, 403C, 404C, 401D, 402D, 403D, 404D, 411E, 412E, 411F, 412F, 411G, 412G, 411H, 412H, 411K, 412K, 411L, 412L: connection electrodes,
500, 501: electrode separation part

Claims (4)

A flat insulating substrate; a first upper surface electrode and a second upper surface electrode formed on one main surface of the insulating substrate; formed on the insulating substrate along a direction orthogonal to the one main surface; A substrate comprising a plurality of connection electrodes connected to one upper surface electrode or the second upper surface electrode;
A first external electrode and a second external electrode are formed opposite to both ends in the longitudinal direction of the main body, the first external electrode is mounted on the first upper surface electrode, and the second external electrode is the second external electrode. A multilayer ceramic capacitor mounted on the top electrode;
An electronic component comprising:
The insulating substrate is formed with an outer shape smaller than the outer shape of the multilayer ceramic capacitor in a state viewed from a direction orthogonal to the one main surface when the multilayer ceramic capacitor is mounted,
The connection electrode is an electronic component that overlaps the multilayer ceramic capacitor when viewed from a direction orthogonal to the one main surface. The electronic component according to claim 1,
When the length of the insulating substrate in the length direction is LiA and the length of the multilayer ceramic capacitor in the length direction is Lci, the relationship LiA <Lci is satisfied.
An electronic component that satisfies a relationship of WiA <Wci, where WiA is a width of the insulating substrate in a width direction orthogonal to the length direction and Wci is a width of the multilayer ceramic capacitor in the length direction. The electronic component according to claim 2,
The insulating substrate has at least one notch formed;
An electronic component, wherein the connection electrode is formed on an inner wall surface of the notch. The electronic component according to claim 3,
The notch is an electronic component that overlaps at least one of the first external electrode and the second external electrode when viewed from a direction orthogonal to the one main surface.

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