JP2013544033A - 信頼性を向上したスルーシリコンビア - Google Patents
信頼性を向上したスルーシリコンビア Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 21
- 239000010703 silicon Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000009623 Bosch process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
本明細書で説明される実施の形態は、半導体装置に関し、特に、シリコン装置を相互接続するためのスルーシリコンビアおよびそれを形成する方法に関する。
回路密度を増加させるとともに単一パッケージ内に複数の装置を集積するために、パッケージ内において、異なるダイ上の2以上の集積回路(integrated circuit(IC))が垂直方向または水平方向にスタックされ得る。このようにスタックダイ(stacked-die)の装置では、複数の装置を相互接続するとともに装置をパッケージ上のパッドに接続するために、スルーシリコンビア(through-silicon via(TSV))が用いられ得る。装置の外縁の周囲に生成された接続に限定される、従来のワイヤボンディング技術とは異なり、TSVは、シリコンダイ本体を介して装置間の垂直接続を可能にする。このことは、装置間の物理的接続を短くし得るとともに、高密度かつ高アスペクト比の接続を可能にする。ある特定の位置(または複数の位置)において、断面寸法が低減されたTSVを提供することが望ましい。
ある実施の形態に従うと、半導体装置は、頂面および底面を有する基板を含み得る。スルーシリコンビア(TSV)は、基板の頂面から基板の底面に延在し得る。TSVは、長手軸に沿って延在する高さプロファイルおよびサイドプロファイルを有し得る。サイドプロファイルは、長手軸に対して第1の角度をなす上方セグメントと、長手軸に対して第2の角度をなす下方セグメントとを有し得る。第2の角度は、第1の角度と異なり得る。下方セグメントは、TSVの高さの20%未満の高さを有し得る。
図面は実施の形態の設計および有用性を示し、同様の構成要素には共通の参照符号が付されている。これら図面は必ずしも正確な尺度に従って描かれていない。上記および他の効果および対象をいかに得られるのかについて正しく理解するために、添付図面に示される実施の形態のより具体的な説明が提供されるであろう。これら図面は単に典型的な実施の形態を描くため、その範囲に限定されるものではない。
以下、図面を参照して、さまざまな実施の形態が説明される。図面は正確な尺度に従って描かれていないこと、および図面を通じて同様の構造または機能の要素には同様の参照符号が付されていることに留意すべきである。図面は1以上の実施の形態の説明を円滑にすることのみを意図するものであることにも留意すべきである。さらに、示された実施の形態は、表されたすべての態様または効果を有さなくてもよい。具体的実施の形態と併せて説明される内容または効果は必ずしもその実施の形態に限定されず、たとえそのように説明されていなくとも、すべての他の実施の形態において実現されてもよい。
Claims (15)
- 半導体装置であって、
頂面および底面を有する基板と、
前記基板の前記頂面から前記基板の前記底面に延在するスルーシリコンビア(through-silicon via(TSV))とを備え、
前記TSVは、長手軸に沿って延在する高さプロファイルおよびサイドプロファイルを有し、
前記サイドプロファイルは、前記長手軸に対して第1の角度をなす上方セグメントと、前記長手軸に対して第2の角度をなす下方セグメントとを有し、
前記第2の角度は、前記第1の角度と異なり、
前記下方セグメントは、前記TSVの高さの20%未満の高さを有する、半導体装置。 - 前記第2の角度は、前記第1の角度よりも大きい、請求項1に記載の半導体装置。
- 前記第1の角度は、約0度である、請求項1または2に記載の半導体装置。
- 前記下方セグメントは、テーパー構造を有する、請求項1〜3のいずれか一項に記載の半導体装置。
- 前記下方セグメントは、曲面構造を有する、請求項1〜3のいずれか一項に記載の半導体装置。
- 前記上方セグメントは、第1のテーパー構造を有し、
前記第1の角度は、0度よりも大きい、請求項1,2,4,5のいずれか一項に記載の半導体装置。 - 前記下方セグメントは、第2のテーパー構造を有し、
前記第2の角度は、前記第1の角度よりも大きい、請求項6に記載の半導体装置。 - 前記TSVは、長方形の水平断面を有する、請求項1〜7のいずれか一項に記載の半導体装置。
- 前記TSVは、中心部と、前記中心部を取り囲む層とを有し、
前記中心部は、導電性材料を備え、
前記層は、絶縁性材料を備える、請求項1〜8のいずれか一項に記載の半導体装置。 - 前記基板の上にスタックされた追加基板と、
前記TSVの形状と同一形状を有する追加TSVとをさらに備える、請求項1〜9のいずれか一項に記載の半導体装置。 - 前記サイドプロファイルは、中間セグメントを有し、
前記上方セグメントおよび前記下方セグメントのうちの少なくとも一方は、前記中間セグメントの断面寸法よりも小さな断面寸法を有する、請求項1〜10のいずれか一項に記載の半導体装置。 - 長手軸に沿って延在する高さプロファイルおよびサイドプロファイルを有するスルーシリコンビア(through-silicon via(TSV))を形成する方法であって、
基板を供給するステップと、
前記サイドプロファイルの上方セグメントを形成するために、前記基板を異方性エッチングするステップと、
前記サイドプロファイルの下方セグメントを形成するために、前記基板を等方性エッチングするステップとを備え、
前記上方セグメントは、前記長手軸に対して第1の角度をなし、
前記下方セグメントは、前記長手軸に対して第2の角度をなし、
前記第2の角度は、前記第1の角度と異なり、
前記下方セグメントは、前記TSVの高さの20%未満の高さを有する、方法。 - 前記第2の角度は、前記第1の角度よりも大きく、
前記下方セグメントは、曲面構造を有する、請求項12に記載の方法。 - 前記上方セグメントは、第1のテーパー構造を有し、
前記第1の角度は、0度よりも大きい、請求項12または13に記載の方法。 - 前記サイドプロファイルは、中間セグメントを有し、
前記上方セグメントおよび前記下方セグメントのうちの少なくとも一方は、前記中間セグメントの断面寸法よりも小さな断面寸法を有する、請求項12〜14のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/945,700 US8384225B2 (en) | 2010-11-12 | 2010-11-12 | Through silicon via with improved reliability |
US12/945,700 | 2010-11-12 | ||
PCT/US2011/055129 WO2012064435A1 (en) | 2010-11-12 | 2011-10-06 | Through silicon via with improved reliability |
Publications (2)
Publication Number | Publication Date |
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JP2013544033A true JP2013544033A (ja) | 2013-12-09 |
JP5607836B2 JP5607836B2 (ja) | 2014-10-15 |
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Application Number | Title | Priority Date | Filing Date |
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JP2013538729A Active JP5607836B2 (ja) | 2010-11-12 | 2011-10-06 | 信頼性を向上したスルーシリコンビア |
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Country | Link |
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US (1) | US8384225B2 (ja) |
EP (1) | EP2638568B1 (ja) |
JP (1) | JP5607836B2 (ja) |
KR (1) | KR101513381B1 (ja) |
CN (1) | CN103262232B (ja) |
TW (1) | TWI450377B (ja) |
WO (1) | WO2012064435A1 (ja) |
Cited By (2)
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JP2016072449A (ja) * | 2014-09-30 | 2016-05-09 | 大日本印刷株式会社 | 導電材充填貫通電極基板及びその製造方法 |
JP2018170356A (ja) * | 2017-03-29 | 2018-11-01 | 公益財団法人福岡県産業・科学技術振興財団 | 半導体装置の製造方法 |
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US9257337B2 (en) | 2013-04-17 | 2016-02-09 | Industrial Technology Research Institute | Semiconductor structure and manufacturing method thereof |
TWI492345B (zh) * | 2013-04-17 | 2015-07-11 | Ind Tech Res Inst | 半導體結構及其製作方法 |
US9318414B2 (en) | 2013-10-29 | 2016-04-19 | Globalfoundries Inc. | Integrated circuit structure with through-semiconductor via |
US9318413B2 (en) | 2013-10-29 | 2016-04-19 | Globalfoundries Inc. | Integrated circuit structure with metal cap and methods of fabrication |
US9230936B2 (en) | 2014-03-04 | 2016-01-05 | Qualcomm Incorporated | Integrated device comprising high density interconnects and redistribution layers |
US9123738B1 (en) | 2014-05-16 | 2015-09-01 | Xilinx, Inc. | Transmission line via structure |
US9515035B2 (en) | 2014-12-19 | 2016-12-06 | International Business Machines Corporation | Three-dimensional integrated circuit integration |
US10049981B2 (en) * | 2016-09-08 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Through via structure, semiconductor device and manufacturing method thereof |
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KR101513381B1 (ko) | 2015-04-17 |
CN103262232B (zh) | 2015-12-09 |
TW201225241A (en) | 2012-06-16 |
EP2638568A1 (en) | 2013-09-18 |
JP5607836B2 (ja) | 2014-10-15 |
KR20130081309A (ko) | 2013-07-16 |
EP2638568B1 (en) | 2020-08-26 |
WO2012064435A1 (en) | 2012-05-18 |
US20120119374A1 (en) | 2012-05-17 |
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