JP2013243859A - Inverter gate control circuit and inverter power supply device having the inverter gate control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter gate control circuit and an inverter power supply device that supply power to a load without delay after a restart command is output, and suppress fluctuations in an inverter output voltage by solving a magnetic deflection while following inverter output control.SOLUTION: An inverter gate control circuit 20A that has an inverter 1 and a transformer 2 for transforming an output voltage of the inverter 1 to output a desired voltage and that is applied to a power supply connected with a load 8 with a switch function on the transformed voltage output side of the transformer 2 includes: a magnetic deviation detection circuit 23A for operating the transformer 2 in an unloaded condition after gate-blocking the inverter 1, and detecting whether there is a magnetic deviation on the basis of an integral value of inverter output currents in the period; and a magnetic deviation compensation circuit 24A for feeding a modulation factor for magnetic deviation compensation different from a modulation factor for a normal operation with no magnetic deviation detected to a gate pulse creation circuit 25 while a magnetic deviation is detected.

Description

  The present invention relates to an inverter gate control circuit and an inverter power supply apparatus including the inverter gate control circuit.

  In a power converter (hereinafter referred to as “inverter”) for converting DC power into AC power, a main circuit in which power semiconductor elements such as a gate turn-off thyristor (GTO) are bridge-connected, and the power semiconductor elements And a control circuit for generating a gate pulse necessary for the above. The control circuit creates a gate pulse while feeding back the measured value of the inverter output voltage in order to obtain a required inverter output voltage.

  When a high-voltage or large-current inverter output is required, a transformer is arranged on the inverter output side, and the voltage is stepped up and down by the transformer. An AC power supply equipped with a transformer that transforms the output of such an inverter into a desired voltage or current is a relatively small-capacity inverter that can handle high-voltage or large-current output, and requires a high-voltage or large-current power supply. It is used in various industrial fields such as welding equipment, fusion acceleration power supplies and uninterruptible power supplies.

  In the above inverter, when the iron core of the transformer arranged on the output side is saturated, an excessive excitation current flows to the primary side of the transformer, which may damage the power supply. Therefore, transformers used in power converters such as inverters are generally designed to have operating conditions with sufficient likelihood for the core's saturated magnetic flux, with a core gap. is there.

  However, even in the case of an AC power supply having a transformer with a core gap, in the power supply in which the output voltage changes suddenly due to a load change or repeats stop-restart, the inverter output state is When changing, a large direct current component is generated in the magnetic flux of the transformer core, and the magnetic bias may not be suppressed by the core gap alone.

  In view of this, for example, a technique for suppressing the demagnetization generated in the transformer has been proposed, such as the technique disclosed in Japanese Patent Application Laid-Open No. 2001-112247 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2001-231269 (Patent Document 2). ing.

  More specifically, in the technique disclosed in Patent Document 1, in an inverter that repeats restarting with a gate block, the gate pulse is converted into phase information, the phase information at the time of gate block is held, and a restart command is issued. This is a technology that suppresses the bias magnetism by balancing the duration of the inverter output signal with positive and negative by outputting a restart timing signal in comparison with the phase information held at the time of input.

  The technique disclosed in Patent Document 2 predicts a period in which the excitation current is maximum from the voltage command, and corrects the voltage command value from the integral value of the current on the primary side or the secondary side of the transformer only during that period. By this, it is the technique which suppresses an inrush current and suppresses a magnetization.

JP 2001-111247 A JP 2001-231269 A

  However, in the technique disclosed in Patent Document 1, since the inverter is restarted at a timing such that the duration of the inverter output signal is balanced between positive and negative, the supply of power to the load is delayed after the restart command is output. Since the gate pulse is output so as to balance positive and negative immediately after restart, inverter output control such as feedback control and soft start control is ignored.

  Further, in the technique disclosed in Patent Document 2, in a 1-pulse inverter in which the AC voltage command has a substantially constant value, the period during which the excitation current is maximum cannot be predicted from the AC voltage command. The problem is that it is difficult to apply to a one-pulse inverter having a constant value, and that when the magnetism occurs, both positive and negative poles are corrected in the same direction, so that the output voltage of the inverter decreases or increases. is there.

  In other words, in these conventional technologies, after the restart command is output, power is supplied to the load without delay, and the bias magnetism is eliminated while following inverter output control such as feedback control and soft start control. The problem is that the vertical movement of the output voltage cannot be suppressed.

  The present invention has been made to solve the above-described problems, and supplies power to a load without delay after a restart command is output, and follows inverter output control such as feedback control and soft start control. It is another object of the present invention to provide an inverter gate control circuit that eliminates the bias and suppresses the vertical movement of the inverter output voltage and an inverter power supply device including the inverter gate control circuit.

  In order to solve the above-described problem, an inverter gate control circuit according to an embodiment of the present invention includes an inverter that converts DC power into AC power, and a transformer that converts the output voltage of the inverter into a desired voltage and outputs the voltage. And is applied to a power source in which a load without a switch function and one of a load switch and a load with a switch function are connected to a side where a voltage transformed by the transformer is output, and gate control of the inverter is performed. An inverter gate control circuit to perform, after the inverter is gate-blocked, the load switch and the load with the switch function are switched off, and the load without the switch function and the load with the switch function are connected to the transformer The transformer is operated in a no-load state with the load opened, and the output power of the inverter in the meantime A magnetic field detection circuit that detects the presence or absence of magnetic bias based on the integral value of the magnetic field, and a gate pulse that generates a gate pulse by comparing the carrier wave and the modulation factor while the magnetic field detection circuit detects the magnetic bias The creation circuit includes a demagnetization correction circuit that provides a modulation factor for demagnetization correction that is different from the modulation rate during normal operation in which no demagnetization is detected.

  In order to solve the above-described problems, an inverter power supply apparatus according to an embodiment of the present invention includes the inverter gate control circuit.

  According to the present invention, power is supplied to the load without delay after the restart command is output, and the inverter output voltage is corrected by correcting the bias while following inverter output control such as feedback control and soft start control. Can be suppressed.

Schematic which shows the structure of the inverter power supply device (when the load connected is a load without a switch function) provided with the inverter gate control circuit which concerns on the 1st Embodiment of this invention. Schematic which shows the structure of the inverter power supply device (when the load connected is a load with a switch function) provided with the inverter gate control circuit which concerns on the 1st Embodiment of this invention. Schematic which showed the structure of the inverter gate control circuit which concerns on the 1st Embodiment of this invention. Explanatory drawing which showed the operation timing of each arm in the inverter which the inverter gate control circuit which concerns on embodiment of this invention controls. Explanatory drawing which showed the relationship between the gate pulse which the inverter gate control circuit based on the 1st Embodiment of this invention produces | generates, a carrier wave, and a modulation factor from a normal driving | operation to a power supply stop. Explanatory drawing which showed the relationship between the gate pulse which the inverter gate control circuit which concerns on the 1st Embodiment of this invention generate | occur | produces, a carrier wave, and a modulation factor from a demagnetization correction operation power supply stop to a normal operation through a demagnetization correction operation. . Schematic which shows the structure of the inverter power supply device provided with the inverter gate control circuit which concerns on the 2nd Embodiment of this invention. Schematic which shows the structure of the inverter gate control circuit which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which showed the example of the polarized-magnetic-pole correction amount calculated in the inverter gate control circuit which concerns on the 2nd Embodiment of this invention, and a reverse-polarity correction amount, (A) is a polarized-magnetic-pole correction amount and a reverse-polarization correction amount. The figure which showed the 1st example of this, (B) is the figure which showed the 2nd example of the polarized-magnetic-pole correction amount and the reverse-polarity correction amount, (C) is the 3rd of the polarized-magnetic-pole correction amount and the reverse-polarity correction amount. The figure which showed the example. Schematic which shows the structure of the inverter gate control circuit which concerns on the 3rd Embodiment of this invention.

  Hereinafter, an inverter gate control circuit according to an embodiment of the present invention and an inverter power supply device including the inverter gate control circuit will be described with reference to the accompanying drawings.

[First Embodiment]
1 and 2 are schematic diagrams showing a configuration of a first inverter power supply apparatus 50A including a first inverter gate control circuit 20A that is an example of the inverter gate control circuit according to the first embodiment of the present invention. .

  The first inverter power supply device 50A includes an inverter 1 connected to a DC power supply or a rectifier, and a three-phase transformer that converts the output voltage of the inverter 1 connected to the primary side into a desired voltage and outputs it to the secondary side 2 and a first inverter gate control circuit 20 </ b> A that generates gate pulses of power semiconductor arms (inverter arms) 11, 12, 13, and 14 constituting the inverter 1 and inputs them to the inverter 1. Further, the first inverter power supply device 50A includes, for example, a rectifier 3 that converts AC power into DC power on the secondary side of the three-phase transformer 2, that is, the side that transforms and outputs the output voltage of the inverter 1. It is connected to a smoothing capacitor 4 for reducing the DC voltage ripple, a voltage divider 5 for dividing the voltage, a load (no switch function) 6 and a load switch 7.

  The first inverter gate control circuit 20A includes an output voltage control circuit 22, a first bias detection circuit 23A, a first bias correction circuit 24A, a gate pulse generation circuit 25, and an SR (set / reset). And the gate pulse generation circuit 25 inputs the generated gate pulses of the power semiconductor arms 11, 12, 13, 14 to the inverter 1, and controls the DC voltage supplied to the load 6. The bias of the phase transformer 2 is suppressed.

  The output voltage control circuit 22 normally performs, for example, PI control, generates an output voltage control command for controlling the output voltage while feeding back the measured value of the power supply output voltage (DC voltage), and the first bias magnetism. This is given to the correction circuit 24A.

  The first demagnetization detection circuit 23A measures the demagnetization amount of the three-phase transformer 2 during a predetermined period, more specifically, while the output from the SR latch circuit 26 is H (1), and detects the positive demagnetization. Is detected, whether or not a negative magnetic bias has occurred, or whether any magnetic bias has occurred.

  The first bias correction circuit 24A is a gate pulse generating circuit based on the output voltage command received from the output voltage control circuit 22 and the bias state of the three-phase transformer 2 detected by the first bias detection circuit 23A. 25, the modulation factor of each power semiconductor arm 11, 12, 13, 14 is determined.

  The gate pulse generation circuit 25 includes, for example, a triangular wave generation circuit (not shown) as a carrier wave generation circuit that generates a triangular wave as a carrier wave (carrier wave), and the triangular wave as the carrier wave generated by the triangular wave generation circuit and the first wave The modulation rate of each power semiconductor arm 11, 12, 13, 14 provided from the magnetic bias correction circuit 24 </ b> A, that is, the power semiconductor arm (hereinafter referred to as “first arm”) 11 and the power semiconductor arm. (Hereinafter referred to as “fourth arm”) 14 modulation rate, power semiconductor arm (hereinafter referred to as “second arm”) 12 and power semiconductor arm (hereinafter referred to as “third arm”). Based on the modulation rate of 13, the gate pulses of the power semiconductor arms 11, 12, 13, and 14 to be input to the inverter 1 are generated.

  The SR latch circuit 26 has a set terminal (shown as “S” in the figure) and a reset terminal (shown as “R” in the figure). A no-load operation command is given to the set terminal of the SR latch circuit 26, and a restart command is given to the reset terminal as a digital signal (L (0) or H (1)).

  In the SR latch circuit 26, when the signals applied to the set terminal and the reset terminal are both L (0), the current output state is held. When the signal applied to the set terminal is H (1) and the signal L is applied to the reset terminal, H is output to the first magnetic bias detection circuit 23A, and the first magnetic bias detection circuit 23A is activated. Make it work. Further, when the signal applied to the set terminal is L and the signal H is applied to the reset terminal, L is output to the first bias detection circuit 23A, and the first bias detection circuit 23A is stopped.

  The first inverter power supply device 50A shown in FIG. 1 is an example in which a load 6 and a load switch 7 in which the load itself does not have a switch function (load switching function) are connected in series in the main circuit. However, as shown in FIG. 2, instead of the load 6 and the load switch 7, a load 8 with a switch function in which the function of the load switch 7 (load switching function) is incorporated in the load itself may be used. That is, the first inverter power supply device 50A shown in FIG. 1 and the first inverter power supply device 50A shown in FIG.

  FIG. 3 is a schematic diagram showing the configuration of the first inverter gate control circuit 20A which is an example of the inverter gate control circuit according to the first embodiment of the present invention.

  In the first inverter gate control circuit 20A, the measured value of the output voltage (DC voltage) of the first inverter power supply 50A is given to the output voltage control circuit 22, while the output of the SR latch circuit 26 and the U, V of the inverter 1 , W, the measured value of the inverter output current in each phase is given to the first bias detection circuit 23A.

The output voltage control circuit 22 determines the modulation factor e _j as an output voltage control command is determined according to the ratio of the DC voltage measurement and the voltage command value, the modulation factor e _j first magnetic bias correction circuit Give to 24A.

  The first bias detection circuit 23A includes an integrator 31 serving as a bias amount calculating element for integrating the inverter output current of each phase during no-load operation and obtaining the amount of bias in each phase, and the integrator 31 includes A comparator as a demagnetization determination element and a demagnetization polarity determination element for comparing the obtained demagnetization amount and the positive demagnetization detection threshold and the demagnetization amount obtained by the integrator 31 and the negative demagnetization detection threshold, respectively. 32 (32a, 32b).

  The integrator 31 receives the output of the SR latch circuit 26 and the measured value of the inverter output current in each of the U, V, and W phases of the inverter 1, and while the output of the SR latch circuit 26 becomes H (1), that is, there is nothing. The inverter output current during the load operation is integrated by the integrator 31 to determine the amount of bias in each phase. The amount of demagnetization obtained by the integrator 31 has a sign of the demagnetized polarity.

  The comparator 32 (32a, 32b) compares the amount of demagnetization obtained by the integrator 31 with the threshold value to determine whether or not the amount of demagnetization exceeds the threshold value, that is, the demagnetization has reached a predetermined level or more. Whether or not the amount of magnetic bias exceeds the threshold value is given to the first magnetic bias correction circuit 24A as information indicating the determination result. For example, as the information indicating the comparison result, the comparator 32 (32a, 32b) outputs L (0) when the value is equal to or less than the threshold value, and sets H (1) as the first when it is determined that the information exceeds the threshold value. To the magnetic bias correction circuit 24A.

  The first bias detection circuit 23A compares, for example, a comparator 32a that determines whether or not the amount of bias obtained by the integrator 31 exceeds a positive bias detection threshold and determines whether there is a positive bias, and an integrator. 31 is compared to determine whether or not the amount of demagnetization obtained exceeds the negative demagnetization detection threshold (the absolute value of the demagnetization amount exceeds the absolute value of the negative demagnetization detection threshold). And a comparator 32b.

  The first demagnetization correction circuit 24A includes an AND circuit 34 that provides information indicating whether or not demagnetization is detected, and a switch 35 (a modulation factor switching element that selects a modulation factor according to the presence or absence of demagnetization. 35a, 35b), a switch 36 (36a, 36b) as a polarity switching element for selecting a modulation rate according to the polarity of the demagnetization, and a correction modulation rate calculation for calculating a correction modulation rate to be applied during the demagnetization correction operation A proportional device 37 (37a, 37b) as an element is provided.

  The AND circuit 34 indicates whether or not the positive magnetic bias detection signal indicating whether or not the positive magnetic bias provided from the two comparators 32 of the first magnetic bias detection circuit 23A has been detected, and whether or not the negative magnetic bias has been detected. An AND operation is performed based on the negative-polarization detection signal, and the result of the AND operation is given to the switch 35. For example, when a signal indicating that the first magnetism detection circuit 23A has detected the magnetism is supplied to the AND circuit 34 as H (1), the AND circuit 34 is H when the magnetism is detected. When (1) is not detected, L (0) is given to the switches 35a and 35b.

  The switchers 35a and 35b serving as modulation factor switching elements select one of the two modulation factors given from the proportional devices 37a and 37b according to the result of the AND operation performed by the AND circuit 34, that is, whether or not the magnetic bias is detected. It selects and gives to switch 36a, 36b.

More specifically, the switching device 35a does not detect a bias magnetism among the two modulation factors e _j and e _i (e _j <e _i ) given from the proportional device 37a (L from the AND circuit 34). When given), the modulation rate e _j is selected and output, while when the bias is detected (when H is given from the AND circuit 34), the modulation rate e _i is selected and output.

Further, the switch 35b does not detect a bias among the two modulation factors e _h and e _j (e _h <e _j ) given from the proportional unit 37b (when L is given from the AND circuit 34). ) Selects and outputs the modulation factor e _j, while selecting and outputting the modulation factor e _h when the bias is detected (when H is given from the AND circuit 34).

  The switchers 36a and 36b serving as polarity switching elements select one of the two modulation factors given from the switchers 35a and 35b in accordance with the detection result of the negative pole magnetization, and the modulation factors for the first and fourth arms. The modulation rates for the second and third arms are supplied to the gate pulse generating circuit 25. The modulation factor is selected so that the gate pulse width of the biased polarity is short and the other gate pulse width is long.

The switch 36a is a modulation that is supplied from the switch 35b with a modulation factor used for generating a gate pulse of the arm (the first and fourth arms 11 and 14 in FIGS. The rate (e _j or e _h ) or the modulation rate (e _i ) given from the switch 35a is switched and output. The switch 36a selects and outputs the modulation rate (e _j or e _h ) given from the switch 35b when negative polarity bias is not detected (when L is given from the comparator 32). When negative polarity bias is detected (when H is given from the comparator 32), the modulation factor (e _i ) given from the switch 35a is selected and output.

Further, the switch 36b changes the modulation rate used for creating the gate pulse of the other arm (the second and third arms 12 and 13 in FIGS. 5 and 6 described later) with respect to the biased polarity from the switch 35a. A modulation rate (e _j or e _i ) to be given or a modulation rate (e _h ) given from the switch 35 b is switched and output. The switch 36b selects and outputs the modulation factor (e _j or e _i ) given from the switch 35a when the negative pole bias is not detected (when L is given from the comparator 32). In the case where the negative pole magnetism is detected (when H is given from the comparator 32), the modulation factor (e _h ) given from the switch 35a is selected and output.

Proportional unit 37a, 37b as the correction modulation factor computation element, on the basis of the modulation factor _{e j} determined by the output voltage control circuit 22 determines the modulation factor _e i, _{e h} for magnetic deviation correction, the switch 35a , 35b.

More specifically, the proportional device 37a gives the switching device 35a with a reverse polarity correction modulation rate e _i obtained by, for example, multiplying the modulation rate e _j by a reverse polarity correction amount given by a constant larger than 1. Further, the proportional unit 37b, for example, gives the polarization magnetic pole correction modulation factor e _h obtained by multiplying the polarization magnetic pole correction amount given in small constant than 1 to the modulation factor e _j to the switch 35b.

The correction modulation factor calculation element of the first demagnetization correction circuit 24A does not necessarily need to be configured by the proportional device 37. Any arithmetic unit may be used as long as the relationship between the modulation rates satisfies e _h <e _j <e _i . For example, the adder proportional unit 37a, to constitute a proportional unit 37b in a subtractor, if so adding or subtracting the constant _{α (e j>α> 0} ) to the modulation factor _{e j, e} h _<e It is possible to obtain the reverse polarity correction modulation rate e _i and the polarized magnetic pole correction modulation rate e _h satisfying _j <e _i .

Further, since the quotient (division result) can be expressed as the product of the reciprocal (multiplication result), the correction modulation factor calculation element can also be configured by a divider. When the correction modulation factor calculation element is configured by a divider, the relationship between the respective modulation factors can be obtained by setting the reverse pole correction amount to a constant larger than 1 and the polarization correction amount to a constant smaller than 1. e _h <e _j <e _i can be satisfied.

  The gate pulse generating circuit 25 is a triangular wave generating circuit (not shown) serving as a carrier wave generating circuit, and generates a triangular wave (carrier wave) as shown in FIGS. 5 and 6 to be described later. Based on the modulation factors of the first and fourth arms 11 and 14 and the second and third arms 12 and 13 given from the bias correction circuit 24A, the power semiconductor arms 11, 12, and 13 to be input to the inverter 1 are used. , 14 gate pulses are generated.

  Next, an inverter gate control method (inverter gate pulse generation method) performed by the inverter gate control circuit according to the embodiment of the present invention will be described using a 1-pulse single-phase inverter as an example (FIGS. 4, 5, and 6). . Here, as an example of the inverter gate control circuit according to the embodiment of the present invention, the first inverter power supply device 50A shown in FIG. 1 (the load 6 having no switch function is opened (turned off) and turned on (turned on) by the load switch 7. The case of the first inverter gate control circuit 20A in the example of switching) will be described.

  FIG. 4 shows the operation timing of each arm 11, 12, 13, 14 in the inverter 1 controlled by the inverter gate control circuit according to the embodiment of the present invention when there is no bias correction (FIG. 4A and FIG. 4). FIG. 4B is an explanatory diagram showing a comparison between the case (FIG. 4C and FIG. 4D).

  If the first inverter power supply 50A must be stopped immediately and there is no demagnetization correction, as shown in FIG. 4 (A), a DC component corresponding to the timing at which the inverter 1 is gate-blocked is output to the inverter. And the three-phase transformer 2 is demagnetized. When the restart instruction of the first inverter power supply device 50A is received and the inverter 1 is restarted and the load 6 is turned on, the amount of magnetic bias of the three-phase transformer 2 further increases, as shown in FIG. As a result, a large inrush current may flow. Therefore, in order to prevent such a large inrush current from flowing, the bias correction is performed before restarting the inverter 1 and applying the load.

  As shown in FIG. 4 (C), the bias correction is performed in the no-load state in which the load switch 7 is turned off in advance before the restart command, and the U, V, and W phases during the no-load operation. By detecting the inverter output current, the bias is detected, and the width of the gate pulse input to the inverter 1 is adjusted (bias correction operation) according to the detected amount of bias. The bias can be detected by detecting the inverter output current when there is no load. This is because the inverter output current when there is no load does not include the load current and is equal to the excitation current of the three-phase transformer 2, and as shown in FIG. This is because of the flow.

  FIG. 5 is an explanatory diagram showing the relationship between the gate pulse generated by the first inverter gate control circuit 20A, the carrier wave, and the modulation rate from the normal operation to the power supply stop, and FIG. 6 shows the first inverter gate control circuit. It is explanatory drawing which showed the relationship between the gate pulse which 20A produces | generates, a carrier wave, and a modulation factor from a power supply stop to a normal operation through a bias correction operation | movement.

The first inverter gate control circuit 20A, as shown in FIG. 5, during normal operation, the modulation factor e _j given to the first magnetic deviation correction circuit from the output voltage control circuit, it is generated in the gate pulse forming circuit A gate pulse of each arm 11, 12, 13, 14 is created by comparing with a carrier wave (carrier wave). Thereafter, when a power supply stop command is given to the first inverter gate control circuit 20A, the first inverter gate control circuit 20A stops the generation of the gate pulse (inverter gate block).

  Subsequently, no-load operation is performed, and the magnetism is detected by detecting the inverter output current of each phase of U, V, and W during no-load operation. Whether or not there is a bias is determined based on whether or not the amount of bias obtained by the first bias detection circuit 23A exceeds the positive bias detection threshold or the negative bias detection threshold, and the first bias detection circuit 23A. Is greater than the positive-polarity detection threshold or negative-polarization detection threshold, the first magnetic detection circuit 23A detects the magnetic detection signal (positive magnetic detection signal or (Negative polarity detection signal) is output to the first bias correction circuit 24A.

When the magnetic bias is detected during the no-load operation, the first inverter gate control circuit 20A starts the magnetic bias correction operation. In magnetic deflection correction during operation, pulse polarity is biased magnetization (in FIGS. 5 and 6 indicated by "+".), Using the polarized magnetic pole correction modulation factor e _h, so that the pulse width is reduced The other pulse (indicated by “−” in FIGS. 5 and 6) is adjusted so that the pulse width is widened by using the reverse polarity correction modulation rate e _i .

However, because the first inverter gate control circuit 20A uses two different types of modulation rates for correcting the magnetic bias, that is, the magnetic polarization correction modulation rate e _h and the reverse polarity correction modulation rate e _i during the magnetic polarization correction operation. It is necessary to prevent the first arm 11 and the second arm 12 and the third arm 13 and the fourth arm 14 from being short-circuited. Therefore, as shown in FIG. 6, the forbidden region 45 is generated when the gate pulse is generated in the arms having the biased polarity (first and fourth arms 11 and 14 indicated by “+” in FIGS. 5 and 6). (Prohibition processing).

  When the first inverter gate control circuit 20A starts the bias correction operation and eventually the bias is not detected, that is, the bias amount obtained by the first bias detection circuit 23A is the positive pole detection threshold. If the value is equal to or less than or equal to or less than the negative-polarization detection threshold, the signal from the comparator 32 is L (0), and the bias correction operation is stopped.

  When a restart command is given to the first inverter gate control circuit 20A and a load is turned on (the load switch 7 is switched to “ON”), the first inverter power supply device 50A enters a normal operation and supplies power to the load 6. Will start immediately.

  According to the inverter gate control method provided with the processing steps as described above, by performing the demagnetization correction operation, the demagnetization of the three-phase transformer 2 can be reduced (demagnetization correction), and the inrush at the time of loading the load An overcurrent trip due to current (= excitation current + load current) can be avoided. Also, by setting the positive or negative magnetic detection threshold corresponding to the saturation characteristics of the three-phase transformer 2 as the magnetic detection threshold, the magnetic bias correction operation is performed only while detecting the magnetic bias. It can be performed.

  Further, in the first inverter gate control circuit 20A, during the demagnetization correction operation, the width of the gate pulse of the demagnetized pole is adjusted to be narrow, and the width of the gate pulse of the other pole is widened. Adjusted to That is, negative correction is performed on the pole that is demagnetized and positive correction is performed on the other pole, so that efficient demagnetization correction can be performed and the vertical movement of the inverter output voltage is suppressed. Can do.

Furthermore, polarized magnetic pole correction modulation factor e _h and the reverse pole correction modulation factor e _i is created based on the modulation factor e _j with feedback of the output voltage, to take a certain balance to increase or decrease the pulse width in bipolar output voltage Does not deviate significantly from the target voltage and can follow the output voltage control even during the bias correction operation.

  According to the inverter gate control method performed by the first inverter gate control circuit 20A, the first inverter power supply device 50A, and the first inverter gate control circuit 20A, the inverter output current during no-load operation is used for the three-phase transformer 2 Since the demagnetization and its polarity are detected and the demagnetization correction operation is performed according to the detected polarity only while the demagnetization is detected, efficient demagnetization correction can be performed.

Further, according to the inverter gate control method performed by the first inverter gate control circuit 20A, the first inverter power supply device 50A, and the first inverter gate control circuit 20A, the output voltage control circuit 22 performs the bias correction operation. Since two different modulation factors e _h and e _i for correcting demagnetization calculated based on the determined modulation factor e _j are used, the load 6 (or load with a switch function) is not delayed after the restart command is output. 8) While supplying power to the inverter and following inverter output control such as feedback control and soft start control, the operation can be resumed in a state in which the demagnetization that occurred when the power supply was stopped was eliminated. Can be suppressed.

  Furthermore, according to the inverter gate control method performed by the first inverter gate control circuit 20A, the first inverter power supply device 50A, and the first inverter gate control circuit 20A, the integration time of the excitation current when obtaining the amount of bias is calculated. Since it is determined without depending on the AC voltage command, for example, it is applied to the inverter gate control technology that determines the integration time of the current based on the AC voltage command when determining the amount of bias as disclosed in Patent Document 2 and the like. Even a 1-pulse inverter in which a difficult AC voltage command has a substantially constant value can be applied.

[Second Embodiment]
FIG. 7 is a schematic diagram showing a configuration of a second inverter power supply device 50B including a second inverter gate control circuit 20B which is an example of the inverter gate control circuit according to the second embodiment of the present invention. FIG. 5 is a schematic diagram showing the configuration of a second inverter gate control circuit 20B.

  The second inverter power supply device 50B is different from the first inverter power supply device 50A in that it includes a second inverter gate control circuit 20B instead of the first inverter gate control circuit 20A. Therefore, in the description of the present embodiment, the difference will be mainly described, and the same components are denoted by the same reference numerals and description thereof will be omitted.

  For example, as shown in FIG. 7, the second inverter gate control circuit 20B further includes a first demagnetization correction amount calculation circuit 27A with respect to the first inverter gate control circuit 20A. The difference is that a second bias correction circuit 24B is provided instead of the bias correction circuit 24A.

  The first demagnetization correction amount calculation circuit 27A calculates the demagnetization correction amount indicating the relationship between the demagnetization amount detected by the first demagnetization detection circuit 23A and the correction amount (depolarization correction amount and reverse polarity correction amount). Information, and based on the demagnetization amount detected by the first demagnetization detection circuit 23A and the demagnetization correction amount calculation information, the depolarization correction amount and the depolarization correction amount are calculated, The correction amount and the reverse pole correction amount are supplied to the second bias correction circuit 24B. When the correction amount for the amount of magnetic bias is set symmetrically between the positive side and the negative side, the magnetic amount correction amount calculation information is an absolute value of the amount of magnetic bias as shown in FIG. It can be expressed as information indicating the relationship between the magnetic quantity | and the correction amount.

  The second demagnetization correction circuit 24B detects the demagnetization correction amount and the reverse pole correction amount given to the proportional devices 37a and 37b by the first demagnetization detection circuit 23A with respect to the first demagnetization correction circuit 24A. It differs in whether it depends on the amount of bias. That is, in the first demagnetization correction circuit 24A, for example, as shown in FIG. 3, although it is a set constant regardless of the magnitude of the demagnetization amount detected by the first demagnetization detection circuit 23A. On the other hand, in the second demagnetization correction circuit 24B, for example, as shown in FIG. 8, the correction amount given from the first demagnetization correction amount calculation circuit 27A (the demagnetization detected by the first demagnetization detection circuit 23A) is obtained. It differs in that it is a variable that varies depending on the magnetic quantity.

  FIG. 9 is an explanatory diagram showing an example of the depolarization correction amount and the reverse polarity correction amount calculated in the second inverter gate control circuit 20B. FIG. 9A shows the depolarization correction amount and the reverse polarity correction amount. FIG. 9B is a diagram showing a second example of the depolarization correction amount and the reverse pole correction amount, and FIG. 9C is a diagram showing the depolarization correction amount and the reverse pole correction amount. It is the figure which showed the 3rd example.

  As a first example of the depolarization correction amount and the reverse polarization correction amount, as shown in FIG. 9A, | the demagnetization amount | which is the absolute value of the demagnetization amount is the first demagnetization detection circuit. When the value is smaller than the positive-polarity detection threshold value or negative-polarization detection threshold value (shown as “positive / negative-polarization detection threshold value” in FIG. 9) set for detection of magnetic polarization in 23A, The pole correction amount is set to 1.0. When the pole correction amount is large, the polarization correction amount is set to a constant value smaller than 1.0, while the reverse pole correction amount is set to a constant value larger than 1.0. That is, after changing in a stepwise manner with the positive / negative polarity demagnetization detection threshold, both the depolarization correction amount and the reverse polarity correction amount take a constant value regardless of the demagnetization amount.

  Further, the second and third examples of the polarized magnetic pole correction amount and the reversed pole correction amount have a | biased magnetic amount | of the first example of the polarized magnetic pole correction amount and the reversed pole correction amount. Is different in that the depolarization correction amount changes according to the | demagnetization amount | in a range larger than the positive demagnetization detection threshold or the negative demagnetization detection threshold set for demagnetization detection in the demagnetization detection circuit 23A. . Specifically, as shown in FIG. 9B and FIG. 9C, in the range larger than the positive-polarization detection threshold or the negative-polarization detection threshold, the polarization correction amount is | It is a variable smaller than 1.0 that decreases with an increase, and the reverse pole correction amount is a variable larger than 1.0 that increases with an increase in | bias amount |. That is, the greater the amount of bias, the greater the voltage superimposed on the inverter output voltage.

  According to the inverter gate control method performed by the second inverter gate control circuit 20B, the second inverter power supply device 50B, and the second inverter gate control circuit 20B, the first inverter gate control circuit 20A, the first inverter power supply device In addition to the effects similar to those of the inverter gate control method performed by 50A and the first inverter gate control circuit 20A, the first demagnetization correction amount calculation circuit 27A has an optimum depolarization correction amount according to the demagnetization amount and Since the reverse pole correction amount is calculated and applied to the second bias correction circuit 24B, the bias can be more efficiently eliminated (in a short time) even when the bias generated when the power supply is stopped is large. .

  The second inverter gate control circuit 20B shown in FIG. 8 shows the case where the proportional devices 37a and 37b are used as the correction modulation factor calculation elements, but the same applies to the case where the adder and the subtractor are used. An effect can be obtained. When an adder and a subtractor are used as the correction modulation factor calculation element, the depolarization correction amount and the reverse pole correction amount may be changed in the range of 0 to 1.

[Third Embodiment]
FIG. 10 is a schematic diagram showing a configuration of a third inverter gate control circuit 20C which is an example of the inverter gate control circuit according to the third embodiment of the present invention.

  The third inverter power supply device including the third inverter gate control circuit 20C is different from the second inverter power supply device 50B including the second inverter gate control circuit 20B in place of the second inverter gate control circuit 20B. In addition, the third inverter gate control circuit 20C is different in that the third inverter gate control circuit 20C is provided, but is not substantially different in other points. In other words, the third inverter power supply apparatus has a configuration in which the second inverter control circuit 20B shown in FIG. 7 as an example is replaced with a third inverter gate control circuit 20C shown in FIG. 10 as an example. Therefore, in the description of the present embodiment, the description will focus on the third inverter gate control circuit 20C, which is the difference, and the same components are denoted by the same reference numerals and description thereof is omitted.

  The third inverter gate control circuit 20C replaces the first bias detection circuit 23A with the second bias detection circuit 23B instead of the first bias control circuit 20B, and calculates the first bias correction amount. Instead of the circuit 27A, a second bias correction amount calculating circuit 27B is provided, and a third bias correction circuit 24C is provided instead of the second bias correction circuit 24B. The entire circuit includes a second inverter control circuit. The simplification of the component for detecting the demagnetization and the component for correcting the demagnetization is performed more than 20B.

  In the second inverter control circuit 20B, in consideration of the case where noise becomes a problem or the case where the bias correction is not performed for the low level bias, the first bias detection circuit 23A applies a bias exceeding a predetermined level. Although the comparator 32 for detection is provided, if noise is not a problem or if it is necessary to correct even a low level of bias, it is sufficient to obtain the amount of bias. A second bias detection circuit 23B in which the comparator 32 is omitted can be applied to the magnetism detection circuit 23A.

  In addition, when the comparator 32 that performs comparison with the threshold value is omitted, it is not necessary to determine the correction amount according to the threshold value, so the second bias correction amount calculation that simplifies the calculation process for determining the correction amount. The circuit 27B can be employed. If the second demagnetization correction amount calculation circuit 27B can perform a calculation process for obtaining a correction amount whose absolute value falls within the range of 0 to 1 in accordance with the demagnetization amount given from the second demagnetization detection circuit 23B, The configuration thereof is arbitrary. For example, an arithmetic unit such as a proportional unit 51 that obtains a correction amount by which a demagnetizing amount given from the second demagnetizing detection circuit 23B is multiplied by a constant and an absolute value thereof falls within the range of 0 to 1. Can be configured.

Further, the second inverter control circuit 20B obtains two different types of modulation factors e _h and e _i for correcting the demagnetization so as to adjust the gate pulse widths of both poles from the viewpoint of suppressing fluctuations in the output voltage. It is provided with the magnetic deviation correction circuit 24B, when the allowable range of fluctuation of the output voltage is more wide, since it also as a pulse width adjustment of the unipolar, the third magnetic bias correction to obtain a modulation factor e _h The circuit 24C can be applied.

For example, if the third pole correction circuit 24C has a positive pole (the first arm 11 and the fourth arm 14) as one pole for adjusting the gate pulse, the third bias correction circuit 24C The pulse widths of the gate pulses for the first arm 11 and the fourth arm 14 are adjusted to be narrow when the positive electrode is demagnetized and wide when the negative electrode is demagnetized. A modulation factor e _h is determined. That is, the third magnetic bias correction circuit 24C is smaller than the modulation factor e _j of positive electrode in the case of being biased magnetization is determined modulation factor e _h is the output voltage control circuit 22 (e _j> e _h) , in the case where the anode is biased magnetization modulation factor _{e h} determines the modulation factor _e greater than _{j (e j} <e _h) so as to modulate rate _{e h.}

Examples configuration of the third magnetic bias correction circuit 24C, for example, as shown in FIG. 10, calculated from the modulation factor e _j which is determined in the second magnetic deviation correction amount calculating circuit 27B by the output voltage control circuit 22 subtracting the correction amount given as a result can be composed of a subtractor 52 to obtain a modulation factor e _h for magnetic bias correction. Polarized磁量obtained by the integrator 31, to have the sign of polarity being biased magnetization, if you are biased magnetization to positive modulation factor e _h is smaller than e _j (e _j> e _h ) is greater than _{e j} if you are biased magnetization to the negative electrode _(e j _<e h).

  According to the inverter gate control method performed by the third inverter gate control circuit 20C, the third inverter power supply device, and the third inverter gate control circuit 20C, the first and second inverter power supply devices 50A, 50B, The inverter gate control circuits 20A and 20B and the first and second inverter gate control circuits 20A and 20B have a simpler configuration and simple steps than the inverter control method, and follow the output voltage control even during the bias correction operation. Immediately after the restart command is output, turning on the load switch 7 or the load 8 with the switch function does not delay the power supply to the load 6 or the load 8 with the switch function, and the magnetic bias generated when the power is stopped. Operation can be resumed in a state where the problem is solved.

  As described above, according to the inverter power supply apparatus including the inverter gate control circuits 20A, 20B, and 20C, the inverter gate control circuits 20A, 20B, and 20C, and the inverter gate control method performed by the inverter gate control circuits 20A, 20B, and 20C, the inverter gate The control circuits 20A, 20B, and 20C detect the presence / absence of bias of the three-phase transformer 2 from the inverter output current during no-load operation, and can perform the bias correction operation only while detecting the bias. .

  The inverter gate control circuits 20A, 20B, and 20C supply power to the load 6 (or the load 8 with a switch function) without delay after the restart command is output, and are used for inverters such as feedback control and soft start control. While following the output control, the operation can be resumed in a state where the bias magnetism generated when the power supply is stopped is eliminated, and the vertical movement of the inverter output voltage can be suppressed. In particular, in the inverter gate control circuits 20A and 20B that adjust the width of the gate pulse of both poles, it is possible to obtain a greater effect of suppressing the vertical movement of the inverter output voltage than the inverter gate control circuit 20C that adjusts the width of the gate pulse of one pole. it can.

  Further, in the inverter gate control circuits 20A, 20B, and 20C, the AC voltage command that is difficult to apply with the inverter gate control technology that determines the current integration time when obtaining the amount of magnetic bias based on the AC voltage command has a substantially constant value. It can also be applied to gate control of a 1-pulse inverter.

  It should be noted that the present invention is not limited to the above-described embodiment as it is, and can be implemented in various forms other than the above-described examples in the implementation stage, and various modifications can be made without departing from the spirit of the invention. Can be omitted, added, replaced, or changed. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Inverter 2 Three-phase transformer 3 Rectifier 4 Smoothing capacitor 5 Voltage divider 6 Load 7 Load switch 8 Load with switch function 11, 12, 13, 14 Power semiconductor arm (inverter arm)
20A, 20B, 20C Inverter gate control circuit 22 Output voltage control circuit 23A, 23B Demagnetization detection circuit 24A, 24B, 24C Demagnetization correction circuit 25 Gate pulse generation circuit 26 SR latch circuit 27A, 27B Demagnetization correction amount calculation circuit 31 Integration (Bias amount calculation element)
32 (32a, 32b) comparator (demagnetization determination element, depolarization determination element)
34 AND circuit 35 (35a, 35b) switch (modulation factor switching element)
36 (36a, 36b) switcher (polarity switching element)
37 (37a, 37b) Proportional device (correction modulation factor calculation element)
45 Forbidden area 50A, 50B, 50C Inverter power supply 51 Proportional device 52 Subtractor

Claims (9)

An inverter that performs conversion from DC power to AC power; and a transformer that converts the output voltage of the inverter into a desired voltage and outputs the voltage. An inverter gate control circuit that is applied to a power source that connects one of a load having no switch function and a load switch and a load with a switch function, and performs gate control of the inverter,
After the inverter is gate-blocked, the load switch and the load with the switch function are turned off, and the load connected to the transformer is opened among the load without the switch function and the load with the switch function. And operating the transformer at the same time, based on the integral value of the output current of the inverter in the meantime to detect the presence or absence of bias,
While the demagnetization detection circuit detects the demagnetization, the gate pulse creation circuit that compares the carrier wave and the modulation rate to create the gate pulse is the modulation rate during normal operation in which no demagnetization is detected. An inverter gate control circuit comprising: a demagnetization correction circuit that provides a modulation factor for different demagnetization correction. A bias correction amount calculating circuit for determining a correction amount based on an integral value of the output current of the inverter obtained by the bias detection circuit;
The bias correction circuit performs a calculation selected from addition, subtraction, multiplication, and division on a correction amount determined by the bias correction amount calculation circuit to the modulation factor during the normal operation. 2. The inverter gate control circuit according to claim 1, wherein a modulation factor for correcting the demagnetization is obtained. The demagnetization correction amount calculation circuit has demagnetization correction amount calculation information indicating a relationship between an integral value of the output current of the inverter obtained by the demagnetization detection circuit and the correction amount. The inverter gate control circuit according to claim 2, wherein the correction amount corresponding to the integral value is determined based on. The demagnetization correction circuit uses a modulation factor during the normal operation and a correction amount determined by the demagnetization correction amount calculation circuit, and a first modulation factor larger than the modulation factor during the normal operation; 4. The inverter gate control circuit according to claim 2, wherein a second modulation factor smaller than the modulation factor during the normal operation is obtained. The demagnetization correction circuit performs any operation selected from addition, subtraction, multiplication and division on a correction amount given by a desired constant to the modulation factor during the normal operation, thereby correcting the demagnetization To obtain a modulation rate of
Using the modulation factor during the normal operation and the correction amount, a first modulation factor larger than the modulation factor during the normal operation and a second modulation factor smaller than the modulation factor during the normal operation, The inverter gate control circuit according to claim 1, wherein: The bias detection circuit further determines the polarity of bias based on the integrated value of the output current of the inverter during no-load operation of the transformer,
The demagnetization correction circuit discriminates between the pole that is demagnetized and the other pole based on the result of determination of the demagnetization polarity obtained by the demagnetization detection circuit, and determines the gate pulse of the demagnetization pole The second modulation factor is selected as the modulation factor used when creating, and the first modulation factor is selected as the modulation factor used when creating the other-pole gate pulse. The inverter gate control circuit according to claim 4 or 5. The demagnetization correction circuit, as a modulation factor to be given to the gate pulse generation circuit according to the result of detection of the presence or absence of demagnetization by the demagnetization detection circuit, the modulation factor during normal operation and the demagnetization correction 7. The inverter gate control circuit according to claim 1, wherein one of the modulation factors is selected. The bias detection circuit includes an integrator that calculates an integral value of the output current of the inverter;
A comparator for comparing an integral value of the output current of the inverter obtained by the integrator with a threshold value and providing information indicating the comparison result to the magnetic bias correction circuit. The inverter gate control circuit according to any one of 7. An inverter power supply apparatus comprising the inverter control circuit according to any one of claims 1 to 8.

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