JPH08340679A - Biased magnetization preventing circuit in high-frequency transformer - Google Patents

Abstract

PURPOSE: To make it possible to prevent biased magnetization in a simple setup, by using a resistor that controls a current carried to an input-side winding on the basis of positive and negative deviation values at an output voltage in a voltage inverter. CONSTITUTION: In a circuit, a resistor 30 is provided in series with a primary winding of a transformer 4. The transformer 4 is represented by an equivalent circuit made up of small resistors r1, r2, and g0, and reactance elements x1 and x2. In a high-frequency circuit with IGBT's, an inverter is operated at very high switching frequency, and a large deviation current is caused because of low resistance in the resistor r1 even when a very small positive and negative deviation factor is generated by positive and negative unsymmetrical waves at an input voltage V1 of the transformer 4. In this constitution, the resistor 30 is inserted in an input side of the transformer 4, and thereby a saturation phenomenon caused by biased magnetization is prevented by inserting a resistor Re with a relation of Re/r1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency transformer for converting a high frequency AC voltage from an inverter into a technique for preventing a magnetic bias phenomenon caused by an imbalance of positive and negative waveforms of an input AC voltage. is there.

[0002]

2. Description of the Related Art FIG. 8 shows, for example, the 1990 Switching Power Supply System Symposium (sponsored by the Japan Management Association).
It is a figure which shows the conventional magnetic bias prevention circuit shown in Proceedings P7-1-3. In the figure, 1 is a DC power supply, 2 is an input capacitor (C1) connected in parallel with DC power supply 1, and 3 is The DC voltage Ed of the DC power source 1 is set to a high frequency (for example, 20 KHz).
Inverter for converting into an AC voltage V1 of about 4), and is composed of four-phase arms of U, X, V, and Y connected in a bridge, and each arm includes an insulated gate transistor (hereinafter referred to as an IGBT) as a switching element and this IGBT. It is composed of anti-parallel connected diodes.

Further, 4 is an AC voltage V from the inverter 3.
A high-frequency transformer (hereinafter referred to as a transformer) 1 is applied to its primary winding, and 5 is a rectifier that converts an AC voltage V2 from the secondary winding of the transformer 4 into a DC voltage, which is bridge-connected. It is composed of diodes D1 to D4. 6 and 7
Are smoothing reactors (SL) that make up the smoothing circuit.
And smoothing capacitors (C2) and 8 are loads (R) connected in parallel with the smoothing capacitor 7.

Reference numeral 9 is a first current sensor (CT1) for detecting a current flowing through the capacitor 2, and 10 is a smoothing reactor 6.
A second current sensor (CT2) for detecting a current flowing through
11 is an output voltage reference (Vd ^* ) generator, 12 is the voltage of the smoothing capacitor 7, that is, the output voltage Vd and the output voltage reference Vd.
^A first subtractor that calculates the deviation from ^* , 13 is a voltage controller that amplifies the output signal from the first subtractor 12, 1
Reference numeral 4 denotes a second subtractor that calculates a deviation between the output I ^* of the voltage controller 13 and the output I from the second current sensor 10,
Reference numeral 15 is a current controller that amplifies the output signal from the second subtractor 14.

Reference numeral 16 is an anti-bias prevention control circuit, 17 is an adder for adding the outputs of the anti-bias control circuit 16 and the current controller 15, and 18 is a difference between the outputs of the anti-bias prevention control circuit 16 and the current controller 15. A third subtractor for calculation, 19 is a triangular wave carrier generation circuit, 20 is a first comparison circuit for comparing outputs from the adder 17 and the carrier signal generation circuit 19, and outputting a level signal of "1" or "0". A comparator, 21 is a second comparator for comparing outputs from the third subtractor 18 and the carrier signal generating circuit 19, and 22 is U, X from outputs from the first and second comparators 20, 21. , A pulse distribution circuit for generating V, Y phase pulses, and a gate amplifier circuit 23 for amplifying the pulse output from the pulse distribution circuit 22.

FIG. 9 is an internal block diagram of the magnetic bias prevention control circuit, in which 24 is a rectifier circuit for rectifying the output of the current sensor 9 of the capacitor 2, and 25 is a first ON / OFF switch for turning on / off the U-phase gate signal. Switch 26, a sign inversion circuit that inverts the sign of the output of the rectifier circuit 24, 27 is a second switch that is turned on / off by a V-phase gate signal, and 28 is the first and second switches.
Filter that smoothes the output from the switches 25 and 27 of
29 is an adder 17 and a subtracter 18 from the output of the filter 28.
Is a PI regulator that produces a signal to.

Next, the operation will be described. The electric power of the DC power supply 1 is converted into a rectangular wave AC by the input capacitor 2 and the inverter 3, and is converted into a DC voltage containing ripples through the transformer 4 and the rectifier 5. The generated ripple is smoothed by the smoothing reactor 6 and the smoothing capacitor 7, converted into direct current with less ripple, and supplied to the load 8. The output voltage Vd is controlled by changing the duty ratio α of the IGBT of the inverter 3.

A conventional magnetic bias prevention circuit prevents magnetic bias by individually controlling the U-phase and V-phase conduction ratios. The control method will be described below. The output voltage reference Vd ^* and the feedback output voltage Vd are the first
The deviation is calculated by the subtracter 12 and further amplified by the voltage controller 13. When there is a deviation between the output voltage reference Vd ^* and the output voltage feedback Vd, the output I ^* of the voltage controller 13 is given to the current controller 15 in the next stage as a current command to increase or decrease the output current I. This serves to control the output voltage Vd.

Further, the current controller 15 uses the current command I
The deviation between ^* and the output current feedback I from the first current sensor 10 is amplified. The magnetic bias prevention control circuit 16 outputs a signal proportional to the magnetic bias current ΔI flowing through the transformer 4, and is added to and subtracted from the output of the current controller 15 through an adder 17 and a third subtractor 18, respectively. The first comparator 20 and the second comparator 21 compare the triangular wave carrier signal from the carrier signal generation circuit 19 with the outputs of the adder 17 and the third subtractor 18, and the pulse distribution circuit 22 and the gate amplifier 23 SU, SX, SV, SY IGBs
Create a gate signal for T.

Now, as shown in FIG. 10A, when the U-phase pulse width of the output voltage V1 of the inverter 3 has a deviation of + Δt and the V-phase has a deviation of −Δt, the inverter output voltage is caused by this positive / negative asymmetric waveform. DC component is generated in the transformer 4, and the transformer 4 is demagnetized. In order to detect this DC component, the current Ic flowing through the first capacitor 2 is detected by the first current sensor 9,
The bias prevention control circuit 16 obtains a signal ΔI proportional to the bias amount.

The detection method is as follows. First, the current Ic (FIG. 10 (B)) flowing through the first capacitor 2 is rectified by the rectifier circuit 24, and the first switch 25 and the sign inversion circuit 26, V that turn on / off the gate signal of the U phase.
A signal obtained by combining the second switches 27 that are turned on / off by the phase gate signal is as shown in FIG. This signal contains a slight DC component ΔI due to the asymmetry of the positive / negative waveform of the inverter output voltage V1. This component ΔV is detected by being smoothed by the filter 28 and further amplified by the PI controller 29. This ΔI is a signal proportional to the amount of magnetic bias, and in order to reduce this ΔI, the pulse width is narrowed by subtracting it from the voltage command V _{I in} the case of the U phase, and added to the pulse in the case of the V phase. Control to widen the width.

[0012]

Since the conventional magnetic bias prevention circuit is constructed as described above, there are problems that the construction for detection and control becomes complicated and the apparatus becomes expensive. The present invention has been made to solve the above problems, and an object of the present invention is to obtain an anti-bias circuit for a high-frequency transformer capable of suppressing the bias with a simple and inexpensive structure.

[0013]

A bias prevention circuit for a high frequency transformer according to claim 1 of the present invention is inserted in series with an input side winding of the high frequency transformer, and a positive / negative deviation of an output voltage of a voltage source inverter. A resistor for suppressing the current flowing into the input side winding based on the component is provided.

The bias prevention circuit for a high-frequency transformer according to claim 2 adds a delay time to the rise of the gate signal to the switching element of the inverter, and adjusts the delay time to each switching element. A delay time adjusting circuit for suppressing a positive / negative deviation component of the output of the inverter is provided.

The bias magnetic prevention circuit for a high frequency transformer according to a third aspect includes a CR circuit having a variable resistor and a capacitor as a delay time adjusting circuit, and delays by changing the resistance value of the variable resistor. The time is adjusted.

The bias magnetic prevention circuit for a high frequency transformer according to a fourth aspect of the present invention includes a digital delay circuit having a counter as a delay time adjusting circuit and a setting device for setting the counter, and the setting of the setting device is performed. The delay time is adjusted by changing the value.

The bias prevention circuit for a high-frequency transformer according to a fifth aspect of the present invention includes means for detecting deviation information that varies depending on the positive / negative deviation component of the output of the inverter, and delay time is set so that the deviation information becomes smaller. The delay time of the adjusting circuit is controlled.

[0018]

According to the first aspect of the invention, when a positive / negative deviation component is generated in the output voltage of the voltage source inverter, the resistor suppresses the inflowing current due to the positive / negative deviation component, and accordingly, the demagnetization of the high frequency transformer is suppressed. It

According to the second aspect of the invention, the delay time is adjusted so that the delay time of the rising edge of the gate signal to the switching element becomes longer when the output pulse width of the inverter becomes longer.

In the third aspect of the invention, the delay time is lengthened by increasing the resistance value of the variable resistor, for example.

According to the fourth aspect of the invention, the delay time is lengthened by increasing the set count value of the setter, for example.

According to the fifth aspect of the present invention, for example, a switching element for increasing the delay time of the rise of the gate signal is selected according to the polarity of the deviation information.

[0023]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a diagram showing a magnetic bias prevention circuit according to a first embodiment of the present invention. The same or corresponding parts as those of the conventional one are designated by the same reference numerals and the description thereof will be omitted. The point different from the conventional one is that the resistor 30 is provided in series with the primary winding of the transformer 4,
Further, this is all of the magnetic bias prevention means.

FIG. 2 shows the transformer 4 in a well-known equivalent circuit. The principle and operation of suppressing the magnetic bias by inserting the resistor 30 will be described below with reference to FIG.

The transformer 4 has a small resistance r as shown in FIG.
It is represented by an equivalent circuit composed of ₁ , r ₂ , g ₀ and reactances x ₁ , x ₂ , b _{0 and the} like. In the case of a high-frequency inverter circuit using an IGBT or the like, since the switching frequency of the inverter is very high, the reactance component is dominant in the internal impedance of the transformer 4 viewed from the input side, and r ₁ << x ₁
Has been established. In this state, if a slight positive / negative deviation component due to positive / negative waveform asymmetry, that is, a direct current component ΔV is generated in the input voltage V1 of the transformer 4, the value of the resistance r ₁ is very small, so that a large bias current ΔI is generated. = ΔV / r ₁ will flow.

The effect of this is shown in FIG. FIG. 3 shows the magnetization characteristics of the transformer 4, in which the horizontal axis represents the exciting current I ₀ and the vertical axis represents the characteristics of the magnetic flux B. For example, when a bias magnetic current Δi = ΔV / r ₁ is applied to the magnetic flux B generated only by the AC component i of the exciting current, the magnetic flux becomes B ′ and the transformer 4 is completely saturated, and an excessive current flows to the input. become.

To prevent this, a resistor 30 is inserted on the input side of the transformer 4. If a resistance value Re that satisfies Re / r ₁ = n is inserted, the eccentricity current is Δi ′ = Δi / n, which is reduced to 1 / n and B≈B ′, thereby preventing a saturation phenomenon due to eccentricity. be able to. Since the internal resistance of the high-frequency transformer is originally a very small value of a few mΩ or less,
The value of Re may be a small value. For example, it can be realized by a simple change such as changing the material of a part of the wiring from the transformer 4 from copper, aluminum or the like to brass having a slightly higher resistivity.

Embodiment 2 FIG. FIG. 4 is a diagram showing a magnetic bias prevention circuit according to a second embodiment of the present invention. The same or corresponding parts as in the conventional case are designated by the same reference numerals, and the description thereof will be omitted. What is different from the conventional one is the Td creating circuit 31 as a delay time adjusting circuit.
The point is that this is a bias magnetic prevention circuit. As shown in FIG. 5, the Td creation circuit 31 has a CR circuit composed of a variable resistor 32 and a capacitor 33 and an AND circuit.
The circuit 34 is provided.

Next, the operation will be described. Variable resistor 32
The CR circuit including the capacitor 33 and the capacitor 33 functions as a delay time element with respect to the gate signal, and the AND circuit 34 generates the rising delay time Td. As shown in FIG. 6, the delay time Td1 when the inverter 3 generates a positive voltage and the timing when the Y-phase is turned on and the delay time Td2 when the V-phase and the X-phase that generate a negative voltage are turned on are individually set. Is adjusted in advance so that the difference Δt between the positive and negative ON time widths becomes zero.

As a result, it is possible to constantly prevent the demagnetization due to the deviation Δt of the positive and negative ON time widths. As described above, in this embodiment, it is possible to prevent the transformer from being demagnetized only by adding a simple control circuit.

Example 3. FIG. 7 shows a magnetic bias prevention circuit according to a third embodiment of the present invention. This embodiment employs a Td creating circuit 35 that digitally generates a delay, instead of the Td creating circuit 31 in the second embodiment. In the figure, 36 is a NOT circuit, 37 is a counter, 38 is an initial value setting circuit of the counter 37, 39 is a flip-flop, and 40 is an AND circuit.

The operation is as follows.
Is set in advance. The reset R is released and the counter 37 starts counting at the timing when the input gate signal becomes "H". When the output Qn of the counter 37 becomes "H" after counting up, the flip-flop 39 is set at that timing and the gate signal from the AND circuit 40 rises. That is, the turn-on timing of the output signal is delayed by the time when the counter 37 counts up with respect to the input signal.

Therefore, by adjusting the setting of the setter 38, an arbitrary delay time Td can be generated. In this embodiment, the delay time can be created with extremely high accuracy by taking measures such as increasing the clock frequency of the counter 37.

Embodiment 4 FIG. In the second and third embodiments, the Td generating circuits 31 and 35 are provided, and the delay time when the gate signal of each phase is turned on is adjusted in advance so that the positive / negative deviation component of the inverter output becomes zero. A method may be used in which means for detecting deviation information that varies according to the deviation component is provided, and each delay time is controlled by the Td creating circuit so that the deviation information becomes small. In this case, as the deviation information detecting means, for example, a method in which a current sensor is inserted in the primary winding of the transformer 4 and the direct current component thereof is used as deviation information may be used, and as described in FIG. A method of detecting the current of the capacitor 2 may be used.

Example 5. In addition, in each of the above-described embodiments, the case where the output voltage of the transformer 4 is applied to a so-called DC / DC converter device in which the rectifier 5 converts the output voltage to a direct current again is described, but the output voltage from the transformer 4 is directly supplied to the load. The present invention can be similarly applied to the configuration described above and has the same effect. Further, the inverter 3 and the transformer 4 are not limited to those that handle single-phase alternating current,
For example, it may handle three-phase alternating current.

[0036]

As described above, according to the first aspect of the present invention, the predetermined resistor is inserted in the winding on the input side of the high frequency transformer. Therefore, the demagnetization phenomenon of the high frequency transformer has a very simple structure. Can be suppressed.

Further, according to the second aspect of the invention, since the predetermined delay time adjusting circuit is provided, the biasing of the high frequency transformer can be performed by a simple method of adjusting the delay time of the rising of the gate signal to the switching element of the inverter. The phenomenon can be suppressed.

Further, according to the third aspect of the invention, since the delay time is adjusted by the predetermined CR circuit, it is possible to adjust the delay time with a simple structure and suppress the bias magnetization of the high frequency transformer.

Further, according to the invention of claim 4, since the delay time is adjusted by a predetermined digital delay circuit, it is possible to adjust the delay time with high accuracy and suppress the bias magnetization of the high frequency transformer.

Further, according to the invention of claim 5, the predetermined deviation information detecting means is provided, and the delay time is controlled in accordance with the detected output, so that the high-frequency transformer can be surely prevented from being demagnetized. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a magnetic bias prevention circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram in which a transformer is represented by an equivalent circuit for explaining the principle of suppressing magnetic bias.

FIG. 3 is a diagram showing a magnetization characteristic of a transformer.

FIG. 4 is a diagram showing a magnetic bias prevention circuit according to a second embodiment of the present invention.

5 is a diagram showing an internal configuration of a Td creation circuit of FIG.

FIG. 6 is a diagram for explaining the operation of the Td creation circuit of FIG.

FIG. 7 is a diagram showing an internal configuration of a Td creation circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a conventional magnetic bias prevention circuit.

9 is a diagram showing an internal configuration of the magnetic bias prevention control circuit of FIG.

FIG. 10 is a diagram showing a positive / negative deviation state of the inverter.

[Explanation of symbols]

1 DC power supply, 3 inverters, 4 transformers, 30 resistors, 31,35 Td creation circuit, 32 variable resistors, 3
3 condenser, 37 counter, 38 setter.

Claims (5)

[Claims] 1. A bias magnetic prevention circuit for a high-frequency transformer that performs voltage conversion of a high-frequency AC voltage converted from a DC voltage by a voltage-type inverter, which is inserted in series with an input side winding of the high-frequency transformer, An anti-bias circuit for a high-frequency transformer, comprising: a resistor for suppressing a current flowing into the input side winding based on a positive / negative deviation component of an output voltage of the inverter. 2. A bias-prevention circuit for a high-frequency transformer that performs voltage conversion of a high-frequency AC voltage converted from a DC voltage by an inverter, wherein a delay time is added to the rising of the gate signal to the switching element of the inverter, An eccentricity prevention circuit for a high-frequency transformer, comprising a delay time adjusting circuit for suppressing the positive / negative deviation component of the output of the inverter by adjusting the delay time to the switching element. 3. The delay time adjusting circuit is provided with a CR circuit having a variable resistor and a capacitor, and the delay time is adjusted by changing the resistance value of the variable resistor. Anti-bias circuit of high frequency transformer. 4. A digital delay circuit having a counter as a delay time adjusting circuit and a setter for setting the counter, wherein the delay time is adjusted by changing a set value of the setter. The bias magnetic prevention circuit for a high-frequency transformer according to claim 2, characterized in that: 5. A delay time adjusting circuit is controlled so as to reduce deviation information that varies according to positive and negative deviation components of the output of the inverter, and the delay time of the delay time adjusting circuit is controlled so as to reduce the deviation information. The bias magnetic prevention circuit for a high frequency transformer according to any one of claims 2 to 4.