JP5310000B2 - Power converter - Google Patents

Description

  The present invention relates to a technology for protecting a transformer from magnetism in an insulated DC-DC power converter, and in particular, electric power that can prevent the occurrence of magnetism when forcibly turning off an inverter gate by overcurrent detection. The present invention relates to a conversion device.

FIG. 11 shows a circuit of a conventional power converter. In FIG. 11, a power converter 51 includes a DC voltage input terminal 19 for applying a DC voltage, an input-side smoothing capacitor 1 for smoothing an input current supplied via the DC voltage input terminal 19, and semiconductor switching elements 2, 3 Series connection circuit, series connection circuit of semiconductor switching elements 4, 5, series connection contact of semiconductor switching elements 2, 3, and transformer with primary winding connected between series connection contact of semiconductor switching elements 4, 5 vessel 6 is connected to the secondary winding of the transformer 6, a rectifying circuit comprising a diode 7 to 10 for rectifying an alternating current output from the transformer secondary, the flat sliding reactor you smoothing the output of the rectifier circuit 11. The load 12 connected to the smoothing reactor 11, the DC output voltage applied to the load 12, is detected, and the error between the DC output voltage and the command value is detected by the built-in error amplifier. Accordingly, a pulse width control unit 16 that determines a pulse width command value of the gate pulse signal, and a gate pulse that outputs a gate pulse signal for turning on and off the gates of the semiconductor switching elements 2 to 5 according to the pulse width command value. An overcurrent detection unit 14 that monitors an input current of the transformer 6 that is input via a signal generator 15, a current detector 13 connected to the primary side of the transformer 6, and detects an overcurrent; and an overcurrent The detection unit 14 includes an overcurrent protection unit 17 that forcibly turns off the gate pulse signal output from the gate pulse signal generation unit 15 when an overcurrent is detected.

  In this configuration, when a DC voltage is applied with the DC voltage input terminal 19 on the upper side in the figure positive and the semiconductor switching elements 3 and 4 are turned off and the semiconductor switching elements 2 and 5 are turned on, a positive voltage is applied to the transformer 6. On the other hand, when the semiconductor switching elements 2 and 5 are turned off and the semiconductor switching elements 3 and 4 are turned on, a negative voltage is applied. A high-frequency alternating current is input to the transformer 6 by alternately applying positive and negative voltages.

  This is transformed and insulated by the transformer 6, then rectified by the diode rectifiers 7 to 10, and smoothed by the smoothing reactor 11, whereby a DC voltage is applied to the load 12. The voltage applied to the load 12 can be controlled by changing the time ratio (duty ratio) at which the semiconductor switching elements 2 to 5 are turned on by the pulse width controller 16 and the gate pulse signal generator 15.

  Here, in order to prevent a large current from flowing due to a sudden change in the load 12 and the switching element from being destroyed, the current flowing through the transformer 6 is monitored by the current detector 13, and a large current flows from the overcurrent detection unit 14. In general, the overcurrent protection unit 17 forcibly turns off the gate pulse to reduce the current.

  However, when the overcurrent protection unit 17 operates to forcibly turn off the gate pulse, a bias magnetism is generated due to the unbalance of positive and negative pulses generated thereby. When the magnetism occurs, in some cases, the transformer 6 causes magnetic saturation, and a large current flows through the device. In this case, even if the overcurrent protection unit 17 turns off the pulse, the current cannot be reduced and the device may be destroyed. It is necessary to prevent the occurrence of

  As a technique for suppressing the demagnetization caused by forcibly turning off the gate pulse for overcurrent protection that has been proposed in the past, in Patent Document 1, it is detected by an AC current detector provided on the primary side of the transformer. When it is detected that the AC output current has reached the overcurrent protection level, one arm is gate-blocked, and then the other arm is used for the period commensurate with the residual magnetic flux of the transformer when the gate is deblocked. The idea of shortening the pulse width of the first gate pulse applied to is disclosed.

JP 2008-228491 A

  However, since the first gate pulse after deblocking described in Patent Document 1 shifts the original gate pulse on-timing backward, the gate-on period is particularly short when an overvoltage occurs, and at high loads. May cause the output voltage to become unstable.

  The present invention has been made in view of the above-mentioned circumstances, and the output voltage of the output voltage against instantaneous and large fluctuations due to imbalance between positive and negative gate pulses caused by pulse-off for overcurrent protection. An object of the present invention is to provide a power converter capable of responding quickly and suppressing the demagnetization while suppressing fluctuations.

  In order to solve the above-described problems, a power conversion device according to the present invention includes a semiconductor switching element, converts a DC voltage into an AC voltage by turning on and off a gate of the semiconductor switching element, and converts the AC voltage to the AC voltage. An inverter that alternately outputs positive and negative voltage pulses, a transformer connected to the output of the inverter, to which a voltage pulse is applied, a rectifier circuit connected to the output of the transformer, and a smoothing connected to the output of the rectifier circuit A series connection circuit of a reactor and a load; a pulse width control unit that detects a DC output voltage applied to the load and determines a pulse width command value of a voltage pulse based on an error between the DC output voltage and the command value by an error amplifier; In accordance with the pulse width command value, a gate pulse signal for turning on and off the gate of the semiconductor switching element is output at a predetermined cycle. An overcurrent detection signal output unit, an overcurrent detection unit that outputs an overcurrent detection signal when an overcurrent is detected by detecting an input current of the transformer and comparing with a predetermined threshold In a power converter having an overcurrent protection unit that forcibly turns off the output of the gate pulse signal during a half cycle of the time point, the gate ON period of the next half cycle after the overcurrent detection signal is output By adjusting the OFF timing of the gate pulse signal output from the gate pulse signal generator, it is adjusted to be equal to the ON period of the gate when the overcurrent is detected and forcibly turned off. A gate pulse signal adjustment unit that outputs a gate pulse signal to the gate of the semiconductor switching element is provided.

  In the present invention, the gate pulse of the next half cycle in which the overcurrent detection unit detects the overcurrent is turned on only after a period equal to the on period of the gate pulse detected by overcurrent and forcibly turned off. By having a gate pulse signal adjustment unit that turns off automatically, the bias of the transformer is eliminated and the bias of the transformer caused by the unbalance of the positive and negative pulse widths is eliminated by adjusting the pulse width of the next half cycle. Generation of magnetic bias can be prevented.

  In particular, since the gate pulse is forcibly turned off when an overcurrent is detected, the gate pulse is controlled to have the same width by adjusting the gate pulse off timing after that half cycle. A more stable output voltage can be obtained without greatly disturbing the off period.

  The gate pulse signal adjustment unit starts at the rising edge of the gate pulse and counts up during the ON period of the gate pulse, and starts counting down from the set value. A pulse mask generation timer that generates a pulse mask signal that turns off the signal, and sets the count value of the pulse width measurement counter when the overcurrent detection signal is output as the setting value of the pulse mask generation timer. This can be realized by outputting the logical product of the gate pulse signal from the signal generator and the pulse mask signal as an adjusted gate pulse signal.

  The power converter according to the present invention has a pulse width measurement counter that measures an ON period until an overcurrent detection signal is output and outputs it as a pulse width command value, and further outputs an overcurrent detection signal. Only the difference between the ON period corresponding to the pulse width command value output from the pulse width measurement counter and the ON period corresponding to the pulse width command value determined by the pulse width controller is gated only for the next half period A gate pulse period adjustment unit that shortens the period of the gate pulse signal output from the pulse signal generation unit is provided.

  In the present invention, since the entire period is shortened as the on-period of the gate pulse is shortened, it is possible to prevent the output voltage from fluctuating due to a change in the on / off ratio.

  As described above, according to the present invention, by turning off the off timing of the gate pulse signal, the gate on-time when the on-period of the gate in the next half cycle in which the overcurrent is detected is forcibly turned off by overcurrent detection. Since the adjustment is made to be equal to the period, it is possible to eliminate the instantaneous unbalance of the positive and negative gate pulses caused by the pulse-off for overcurrent protection while suppressing the fluctuation of the output voltage, and to prevent the bias magnetism.

  In addition, by shortening the overall period as the gate pulse on-period is shortened, the duty ratio change due to elimination of gate pulse imbalance is prevented, and the effect of suppressing output voltage fluctuation is improved. Can do.

It is a block diagram of the power converter device by the 1st Embodiment of this invention. It is a figure which shows the waveform at the time of normal of each part of FIG. It is a wave form diagram at the time of the overcurrent generation | occurrence | production of each part when there is no gate pulse signal adjustment part 18 of FIG. It is a wave form diagram at the time of the overcurrent generation | occurrence | production of each part in case there exists the gate pulse signal adjustment part 18 of FIG. FIG. 2 is a circuit configuration diagram according to an embodiment of a gate pulse signal adjustment unit 18 of FIG. 1. It is a wave form diagram of each part for demonstrating operation | movement of the gate pulse signal adjustment part 18 of FIG. FIG. 6 is a circuit configuration diagram according to another embodiment of the gate pulse signal adjustment unit 18 of FIG. 1. It is a block diagram of the power converter device by the 2nd Embodiment of this invention. It is a wave form diagram of each part for demonstrating operation | movement of the power converter device of FIG. FIG. 9 is a configuration diagram of a gate pulse period adjustment unit 20 in FIG. 8. It is a block diagram of the power converter device by a prior art.

  Hereinafter, a first embodiment of the present invention will be described. FIG. 1 is a configuration diagram of a power conversion device 50 according to the first embodiment. 11, a gate pulse signal adjustment unit that adjusts the pulse width of the next half-cycle gate pulse in which the overcurrent detection unit 14 detects an overcurrent and the overcurrent protection unit 17 forcibly turns off the gate pulse. 18 is added.

Next, the operation of the power conversion device 50 having the above configuration will be described.
First, in normal operation, high-frequency alternating current is input to the transformer 6 by alternately turning on the semiconductor switching elements 2 and 5 and the semiconductor switching elements 3 and 4 constituting the inverter. This is transformed and insulated by the transformer 6, then rectified by the diode rectifiers 7 to 10, and smoothed by the smoothing reactor 11 to apply a DC voltage to the load 12. The voltage applied to the load 12 is controlled by changing the time ratio at which the semiconductor switching elements 2 to 5 are turned on by the gate pulse generated by the gate pulse signal generator 15 based on the command value determined by the pulse width controller 16. I do.

  FIG. 2 shows the waveforms of the respective parts at the normal time. In this figure, (1) is a gate pulse (hereinafter referred to as pulses 2 and 5) to the semiconductor switching elements 2 and 5 output from the overcurrent protection unit 17, and (2) is a gate to the semiconductor switching elements 3 and 4. Pulses (hereinafter referred to as pulses 3 and 4) and (3) represent the primary voltage of the transformer 6, (4) represents the primary current of the transformer 6, and (5) represents the output current of the smoothing reactor 11.

  When normal, the primary current of the transformer 6 does not exceed the overcurrent detection level, so the overcurrent protection unit 17 and the gate pulse signal adjustment unit 18 simply transmit the gate pulses output from the gate pulse signal generation unit 15 in sequence as they are. Then, the semiconductor switching elements 2 to 5 are turned on / off.

  Next, FIG. 3 shows a waveform when there is no gate pulse signal adjustment unit 18 when an overcurrent occurs. In this figure, the current on the positive side exceeds the detection level at time t1 (FIG. 3 (4)), whereby the overcurrent protection unit forcibly turns off the pulses 2 and 5. Due to the shortened pulse width, the current is suppressed, and the next time the pulses 3 and 4 are generated, the negative current falls below the detection level and a normal pulse is generated. Since the current is suppressed, the purpose of protection is achieved, but the pulse width for one cycle including the time t1 becomes unbalanced between positive and negative, and here, demagnetization occurs.

  FIG. 4 shows a waveform when the gate pulse signal adjustment unit 18 is provided. In this case, the on-time of the negative pulses 3 and 4 starting from the time t3 becomes a time t4 when equal to t1 to t0. Then, the pulses 3 and 4 are turned off. As a result, the balance between the positive and negative pulse widths is maintained, and magnetic bias can be prevented.

  FIG. 5 shows an example in which the gate pulse signal adjustment unit 18 is configured with a counter, a timer, and an AND gate. FIG. 6 shows the operation of each part in this configuration example. In this example, the pulse width measurement counter 18a counts up while the gate pulse is on ((3) in FIG. 6). When an overcurrent occurs at time t1, the count value of the pulse width measurement counter at that time is set in the pulse mask generation timer 18b (FIG. 6 (4)). Then, the pulse mask generation timer 18b starts counting down from the set value at time t3, which is the start of the next half cycle, and generates a pulse mask signal at time t4 when it reaches 0 (FIG. 6 (5)). Thereafter, a signal obtained by logical product of the gate pulse signal (FIG. 6 (2)) and the pulse mask signal (FIG. 6 (5)) by the AND gate 18c is used as the final adjusted gate pulse. The switching elements 3 and 4 are turned on (FIG. 6 (6)).

  In FIG. 5, an expression like a hardware configuration is used. However, this part can be configured by hardware, and a part or all of the part is realized by software using the function of the microcomputer. It is also possible. FIG. 7 shows another configuration example of the gate pulse signal adjustment unit 18. In this example, the pulse width control unit 16 uses the ON period until the overcurrent detection time measured by the pulse width measurement counter 18 a as the pulse width command value. The normal pulse width command value to be output is switched by the switch 18d and output as a command value to the gate pulse signal generator 15. This example can also be realized by hardware or software.

  As described above, according to the present embodiment, in accordance with the overcurrent protection in which the gate pulse is turned off at the time of overcurrent detection, the pulse timing of the pulse at the time of overcurrent detection is not changed without changing the on timing of the gate pulse after the half cycle. Since the off timing is adjusted in accordance with the width, the gate off period does not become longer than necessary, and the output voltage can be stabilized even at a high load.

Next, a second embodiment of the present invention will be described.
FIG. 8 is a configuration diagram of the power conversion device 50 according to the second embodiment. The operation in this configuration is as shown in FIG. That is, until an overcurrent is detected at time t1, the positive pulses 2 and 5 are forcibly turned off, and the next negative pulses 3 and 4 are forcibly turned off by the gate pulse signal adjustment unit 18 at time t4. It is the same as FIG. Thereafter, the gate pulse period adjusting unit 20 makes a difference between the time t2 when the gate pulse should have been turned off by the positive pulse and the time t1 when the actual gate pulse is turned off (that is, the pulse is turned off by the gate pulse forced off). The period ends at time t6 earlier than the time t7 when the original next positive-side gate pulse is turned on by the amount of the shortened time), and the next positive-side gate pulse is turned on. As a result, the ratio (duty ratio) between the on period and off period of the pulse is maintained, and fluctuations in the output voltage are suppressed. FIG. 10 shows an example in which the gate pulse period adjusting unit 20 is configured by an arithmetic unit. In this example, the pulse width measured by the gate pulse signal adjustment unit 18 is subtracted from the pulse width command value by the calculator 20a to calculate the time when the pulse is shortened, and the value is specified in advance by the calculator 20b. 9 is set in the gate pulse signal generator 15 as a set value for the period, and a gate pulse is output in the gate pulse signal generator 15 according to the set value. Can be realized. Also in this example, the configuration of FIG. 10 can be realized by software installed in a microcomputer.

  As described above, according to the present embodiment, the duty ratio of the gate pulse due to the unbalance of the gate pulse is reduced by shortening the entire period as the on-period of the gate pulse is shortened by the gate pulse period adjusting unit. Since the change is prevented, the fluctuation of the output voltage can be suppressed.

1 ·············· Input side smoothing capacitor 2 to 5 ······· Power conversion semiconductor switching element 6 ········· Transformer 7 to 10 ··· Output side rectifier diode 11 ... Smoothing reactor 12 ... Load 13 ... Current detector 14 ... …… Overcurrent detector 15 ・ ・ ・ ・ ・ ・ ・ ・ ・ Gate pulse signal generator 16 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Pulse width controller 17 ・ ・ ・ ・ Overcurrent Protection unit 18 ··········································································· Pulse width measurement counter 18b ··· AND gate 18d ·························· Pulse width command changer 19 ··· ·················· Input voltage terminal 20 ··············································································· Equipment 51 ・ ・ ・ ・ ・ ・ ・ ・ ・ Conventional power converter

Claims (1)

An inverter configured by a semiconductor switching element, converting a DC voltage into an AC voltage by turning on and off the gate of the semiconductor switching element, and alternately outputting the AC voltage as positive and negative voltage pulses;
A transformer connected to the output of the inverter and applied with the voltage pulse;
A rectifier circuit connected to the output of the transformer;
A series connection circuit of a smoothing reactor and a load connected to the output of the rectifier circuit;
A pulse width control unit that detects a DC output voltage applied to the load and determines a pulse width command value of the voltage pulse based on an error between the DC output voltage and the command value by an error amplifier;
In accordance with the pulse width command value, a gate pulse signal generator that outputs a gate pulse signal for turning on and off the gate of the semiconductor switching element at a predetermined period;
An overcurrent detection unit that detects an input current of the transformer and outputs an overcurrent detection signal when an overcurrent is detected in comparison with a predetermined threshold;
An overcurrent protection unit that forcibly turns off the output of the gate pulse signal during a half cycle when the overcurrent detection signal is output;
The over-current is detected and forced by shifting the off-time of the gate pulse signal output from the gate pulse signal generation unit during the on-period of the next half cycle of the gate when the over-current detection signal is output. A gate pulse signal adjustment unit that adjusts to be equal to the on period of the gate when it is turned off, and outputs the adjusted gate pulse signal to the gate of the semiconductor switching element;
In a power converter having
The gate pulse signal adjustment unit starts at the rising edge of the gate pulse and counts up during the ON period of the gate pulse, starts counting down from the set value, and outputs the gate pulse signal when it becomes zero. A pulse mask generation timer for generating a pulse mask signal to be turned off, and setting the count value of the pulse width measurement counter at the time when the overcurrent detection signal is output as a setting value of the pulse mask generation timer, wherein the adjusted you wherein power converter to output a gate pulse signal of the logical product of the gate pulse signal and the pulse mask signal from the gate pulse signal generating unit.

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