JPS59226666A - Overload protecting device of inverter device - Google Patents

Abstract

PURPOSE:To prevent the saturation of a transformer by limiting the width of a gate pulse to be applied to an inverter in the half cycle when an overcurrent is detected and setting the gate pulse of th next half cycle to the same shape as the previous pulse. CONSTITUTION:The output of an oscillator 16 is applied though a waveform shaper 17 to one input terminal of a comparator 21. The AC output voltage of an inverter 4 detected by a detecting transformer 18 is applied to one input terminal of a comparator 20 through a rectifier 18, and compared with the output of a DC current detector 15. The output of the comparator 20 is applied to the other input terminal. A gate pulse of the output of the comparator 21 is applied through a pulse width limiter 22 to a pulse amplifier 23. The output of the limiter 22 becomes narrow in the pulse width when an overcurrent is generated. The amplifier 23 amplifies the gate pulse output of the limiter 22 and applies it to the inverter 4.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an overload protection device for an inverter device, and in particular, to suitably prevent saturation of a transformer provided on the output side of the inverter device during its protection operation. The present invention relates to a possible overload protection device.

[Background of the invention]

During overload, overcurrent occurs. However, it is not permissible to allow an overcurrent to flow through the inverter even for a moment. This is because overcurrent can cause the inverter to malfunction, or even destroy it. Therefore, in the past, a high-speed semiconductor switch (interrupter) was provided between the inverter and the load, and when an overcurrent occurred, this interrupter was instantly opened to protect the inverter from overload.

However, since interrupters are expensive, a method that does not use an interrupter (interrupter-less method) has been proposed. This method sharply reduces the output voltage of the inverter when an overcurrent occurs, thereby suppressing the load current below a certain value. However, when a transformer is installed on the output side of the inverter, the sudden drop in output voltage causes the transformer to have a maximum of 2φ1+φr (
A change in magnetic flux occurs (φ: maximum magnetic flux, φ1: residual magnetic flux). A normal transformer becomes saturated due to this change in magnetic flux. Furthermore, it is uneconomical to make the transformer a special specification in order to avoid saturation.

[Purpose of the invention]

An object of the present invention is to provide an overload protection device for an inverter device that prevents saturation of a transformer provided on the output side of an inverter.

[Summary of the invention]

The present invention limits the width of the gate pulse to be applied to the inverter in a half cycle when an overcurrent is detected,
Moreover, the gate pulse of the next half cycle has the same shape as the previous pulse.

In this way, both positive and negative output voltages of the inverter have the same waveform, and saturation of the transformer is prevented.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention. In the figure, a rectifier 2 converts alternating current input via a breaker 1 into direct current. The inverter 4 converts the direct current input via the direct current filter 3 into a desired alternating current according to the gate pulse output from the gate control circuit 10. This alternating current is transferred to transformer 5,
It is applied to the load via an AC filter 6 and a breaker 7.

The gate control circuit 10 outputs a gate pulse as follows. In the figure, the output of the oscillator 16 is given to the waveform shaping circuit 17, and the output of the waveform shaping circuit 17 is given to the comparator 21.
is applied to one input terminal of . The AC output voltage of the inverter detected by the disconnection detection transformer 18 is converted into an automatic voltage regulation (AVR,) signal by the rectifier circuit 19 and applied to one input terminal of the comparator circuit 20 . The other input terminal of this comparison circuit 20 is connected to a DC current detector (
The current detected by DCCT) 15 is provided as an automatic current regulation (ACR) signal. The output of the comparator 20 is applied to the other input terminal of the comparator 21 mentioned above. The gate pulse, which is the output of the comparator 21, is the pulse width limiting circuit 2.
2 to the pulse amplifier 23. This pulse width limiting circuit 22 inputs the current detected by the DCCT 15, narrows the pulse width when an overcurrent occurs, and does not limit the pulse width during normal times (the specific circuit will be described later). The pulse amplifier 23 amplifies the gate pulse output of the pulse width limiting circuit 22 and supplies it to the inverter 4 .

FIG. 2 is a signal waveform diagram of each part of the gate control circuit 1o. In the figure, (a) shows the output waveform of the oscillator 16, and (b) shows the output voltage waveform of the inverter.

G-9 is a signal obtained by converting (b) into a DC signal, and (b) is a DCCT output signal indicating the load state. (E) is the output of the comparator 20, and by comparing the output voltage feedback signal (A'VR signal) in (C) and the output current feedback signal (ACR signal) in (2), it is determined that the larger signal is output. ((f) is the output of the waveform shaping circuit 17, and the output signal (b) of the oscillator is made into a sawtooth wave by this circuit. This signal becomes a pattern signal for determining the inverter output voltage. (G) is a gate pulse generated by determining the width of the inverter output voltage from the cross point by comparing this pattern signal (H) and the feedback signal (E).

In other words, the wider the width, the greater the output voltage. Normally, the gate pulse waveform is as shown in (G), but when the pulse width is limited, it becomes a narrow pulse waveform as shown in (C). How to create this waveform will be described later. In Figure 2, at point fl1, when the load suddenly changes and the DC current increases, the ACR signal) becomes A V
R, signal (c) also becomes larger (to ACR signal)
increases relatively slowly, and a delay of about one cycle is inevitable. However, controlling only with this ACR signal () cannot withstand sudden load changes, so (
It is necessary to perform a sudden tightening as shown in b). In other words, the gate pulse (A) that rises at 11 has its pulse width limited at t2 when an overcurrent is detected, and in the next half cycle, as shown at ta-14 in the figure, a pulse with the same shape as the previous half cycle is generated. do. As a result, both the positive and negative output voltages have the same waveform, the magnetic fluxes in the transformer windings cancel each other out, and the transformer does not saturate.

FIG. 3 shows one embodiment of the pulse width limiting circuit 22. In the figure, 24 is a comparator that compares the ACR signal) with the reference current IR, and serves as an overcurrent detection circuit. 25
is a falling differentiation circuit for clearing other circuits, 26
, 31 and 33 are AND circuits, 27 is a flip-flop circuit that is set by an overcurrent signal and cleared by a falling signal, 28 is a counter that counts clock pulses while the gate pulse is on, and 29 is an input A memory circuit 30 includes a memory circuit 30 for storing signals according to set timing.
N011 circuit, 32 is a comparator.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to FIG. The gate pulse (T) is shown as a positive and negative signal in both Figures 2 and 3, but in order to clarify the operation, it is shown to be equivalent to the inverter output voltage (see voltage in Figure 5). In actual logic operation, the negative pulse becomes a signal in the same direction as the positive pulse, and the inverter section converts the negative pulse into a signal in the same direction as the positive pulse.
A negative switch takes place. (The same applies to the gate pulse (a).) The output voltage is determined by the pulse width T.

ACR, signal) is compared with a reference current IR, and if it is exceeded, the comparator 24 outputs an overcurrent signal (C). If this overcurrent signal (C) is during the ON period of the gate pulse (g), the AND circuit 26 outputs a set signal (d) for the flip-flop 27. The flip-flop 27 is cleared by the differentiating circuit 25 at the falling edge of the gate pulse (b).
This is done by the differential signal (f) of . The counter 28 is
A clock pulse (h) is input, a count is made while the gate pulse (g) is on, and a signal 0) is output. counter 2
8 is a 4-bit binary counter, for example, and pulse A in the figure has a 2G output, pulse B has a 21 output, and pulse C has a 22G output.
This is the output. The memory circuit 29 stores the signal (i). Then, it is set by the rise of the output signal (e) of the flip-flop 27. That is, the number of counts stored in the memory 29 is the number of clock pulses counted during the period from the rise of the gate pulse (g) to the occurrence of overcurrent, and the output signal (j) of the memory 29 is the number of clock pulses stored in the counter 2.
The state of the output (i) at the time of occurrence of overcurrent is held. In the figure, AB and C of the signal (j) are each 20 of a 4-pit binary counter similar to 28.
．． 21.22 output. To reset the memory 29, A
The comparator 32 compares the memorized signal (j) with the output signal (i) of the counter 28.Then, the output of the counter 28 is determined by the memorized count number (ω). For example, in the example shown in Fig. 4, the signal (i
) is 0X20+lX21+OX2"=2, so the state is stored in the memory 29 and becomes the output signal (j). After the overcurrent occurs, the 28 continues counting, so the output of the comparator 32 ( k)
Fi is at a high level, but the signal (i) is the gate pulse (
Since it is reset when the output (k) is turned off, the count number becomes zero and the output (k) also becomes a low level.

The NOR circuit 30 outputs a NOR output signal (4) of the signals (k) and (e). This signal (t and gate pulse (
The AND circuit 33 outputs the signal (a).

As mentioned above, the gate pulse (g) is originally a logic signal that changes only in the positive direction, but is shown as a positive/negative signal in order to correspond to the output voltage of the inverter. Therefore, the signal (A) is also the same, and the negative side pulse (A) is output by ANDing the negative side pulse of (G) and the signal (force).This signal (A) is shown in Figure 1. The signal is input to the pulse amplifier 23 and sent as the gate pulse signal of the inverter.

(9) As can be seen from the operation of this circuit, the present invention controls the output voltage when an overcurrent occurs, and even if the current decreases, the output voltage is not immediately restored to the original value, but the next half cycle is also forced. By reducing the output voltage and the output voltage and making the next half cycle the same waveform as the previous one, the positive and negative volt-seconds of the waveform applied to the inverter transformer are made the same. By operating in this manner, the inverter transformer can be made economical.

Figure 5 shows changes in the magnetic flux of the transformer.

In the figure, ■, and φ are the states of change in voltage and magnetic flux during normal operation, respectively. Vb, φb and V6°φ. This is the operation during overcurrent control. If tightening is performed during overcurrent operation such as Vb and φb, the maximum magnetic flux value becomes 2φ and 10φ, making it impossible to produce an economical transformer. The dash-dotted line in the figure shows the magnetic flux density limit of the economical transformer. On the other hand, V. ,φ. Even if the overcurrent decreases, by making the next half cycle the same waveform, the positive and negative waveforms will be the same, so the magnetic flux will not increase, and with an economical magnetic flux density (1
0) The designed inverter transformer is sufficient.

〔Effect of the invention〕

According to the present invention, in an interrupterless inverter, an economical transformer is used and it is
You can perform Nagashiborikomi.

[Brief explanation of the drawing]

Fig. 1 is an embodiment of the inverter overload protection device according to the present invention, Fig. 2 is a waveform diagram of each part of Fig. 1, Fig. 3 is an embodiment of the pulse width limiting circuit, and Fig. 4 is the embodiment of Fig. 3. The waveform diagram of each part and FIG. 5 are diagrams explaining the effects of the present invention. 2... Rectifier, 3... DC filter, 4... Inverter, 5... Transformer, 6... AC filter,
10... Gate control circuit, 15... DCCT, 16
... Oscillator circuit, 17... Waveform shaping circuit, 18...
・Transformer, 19... Rectifier port M, 20.21... Comparator, 22... Pulse (11)

Claims (1)

[Claims] 1. In an inverter device including an inverter with a transformer connected to the output side and a gate control circuit that outputs a desired gate pulse to the inverter, when an overcurrent of the inverter is detected, the pulse of the gate pulse is An overload protection device for an inverter device, comprising a pulse width limiting circuit that limits the width of the gate pulse and makes the pulse width of the next half cycle the same as the limited pulse width.