JP4677292B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply apparatus that rectifies three-phase alternating current and outputs direct current.

  In a rectifier using a three-phase alternating current as an input power supply, constant voltage characteristics are required regardless of the weight of the output load (see, for example, Patent Document 1). It is also required that the input current to the rectifier circuit for each of the three phases be balanced.

  The structure of the conventional rectifier is shown in FIG. In FIG. 1, 81-1, 81-2 and 81-3 are three-phase AC input terminals, 82-1, 82-2 and 82-3 are rectifier circuits, 83-1, 83-2 and 83-3 are respectively Constant voltage generation circuits, 84-1, 84-2 and 84-3 are output current control circuits, 85-1, 85-2 and 85-3 are error signal detection circuits, and 86-1 and 86-2 are respectively. Each is a DC output terminal.

  In FIG. 1, three-phase alternating currents input to three-phase alternating current input terminals 81-1, 81-2, and 81-3 are rectifier circuits 82-1, 82-2, and 82, respectively. -3. The input AC is rectified by the rectifier circuits 82-1, 82-2 and 82-3 to generate an intermediate DC voltage. Each intermediate DC voltage is converted into a constant voltage DC of a desired voltage by the constant voltage generation circuits 83-1, 83-2, and 83-3.

  Here, in order to balance the input currents to the rectifier circuits 82-1, 82-2 and 82-3 for each of the three phases, the output currents of the constant voltage generation circuits 83-1, 83-2 and 83-3, That is, the outputs of the constant voltage generation circuits 83-1, 83-2, and 83-3 are controlled so that the output power is balanced. The error signal detection circuits 85-1, 85-2, and 85-3 detect the output currents of the constant voltage generation circuits 83-1, 83-2, and 83-3, and output them so that each output is equally divided. Current control circuits 84-1, 84-2 and 84-3 feedback control the output currents of the constant voltage generation circuits 83-1, 83-2 and 83-3. When the load of the rectifier varies, the output current control circuits 84-1, 84-2, and 84-3 have their respective constant current voltages adjusted to the constant voltage generation circuit that outputs the maximum current. Control the generation circuit.

Japanese Patent Laid-Open No. 11-318083

  However, the output current control circuit becomes complicated to match the constant voltage generation circuit that outputs the maximum current, and there is a disadvantage that the operation becomes unstable due to control adjustment between the output current control circuits. It was.

  An object of this invention is to provide the power supply device which can balance the input current to the rectifier circuit with respect to each phase of three phases stably with a simple circuit configuration.

  In order to achieve the above object, the present invention provides an error signal in which a difference between an output voltage value of a DC converter circuit connected in parallel and a desired output reference voltage value is detected, and each DC converter circuit connected in parallel. The integrated value obtained by integrating the integrating circuit according to the amount of current flowing through the semiconductor switch that conducts / cuts off the current inside is compared, and when this integrated value exceeds the error signal value, the corresponding semiconductor switch of the DC conversion circuit It is a power supply device which adjusts output current by interrupting.

Specifically, the present invention relates to three rectifier circuits that generate intermediate DC voltages by rectifying two different phases among the three phases of three-phase AC, and intermediate DC voltages generated by the three rectifier circuits. Three DC converters, each of which is connected in parallel, outputs a DC voltage by converting the voltage by a semiconductor switch that conducts / cuts off, a transformer that transforms the voltage that is conducted / cut off, and a rectifier that rectifies the transformed voltage. An error signal detection circuit that detects a voltage value of an output connected in parallel with the circuit and the three DC conversion circuits, and outputs a difference between the voltage value and a desired output reference voltage value as an error signal; and three current detection circuit for detecting a current flowing in the number of semiconductor switches, respectively, and three integrating circuit for integrating the three current detection circuit detecting the current for each on-off cycle of each of the semiconductor switches The semiconductor switches of the DC converter of the relevant made conductive initiated every off period of the semiconductor switch, the DC converter circuit applicable when the integrated value of the three integrating circuits exceeds the value of each said error signal A power supply device comprising three current control circuits for shutting off a semiconductor switch.

  In the power supply device of the present invention, each DC conversion circuit controls the output current with respect to the difference between the output voltage value of the DC conversion circuits connected in parallel and the target output reference voltage value. Since each current control circuit independently controls the DC conversion circuit, it is not necessary to adjust the control between the current control circuits.

  Therefore, according to the present invention, it is possible to provide a power supply device that can stably balance the input current to the rectifier circuit for each of the three phases with a simple circuit configuration.

  In the power supply device of the present invention, three overcurrent protections that shut off the semiconductor switch of the corresponding DC conversion circuit when the current values detected by the three current detection circuits each exceed a predetermined overcurrent reference value It is preferable to further comprise a circuit.

  A power supply device capable of responding to an instantaneous overcurrent can be provided.

In the power supply device of the present invention, each of the three integrating circuits is connected in parallel to a capacitor charged with a current detected by the current detection circuit, and the capacitor is connected to each capacitor on and off cycles. It is preferable to include a discharge switch for discharging electric charges.

  The input current to the rectifier circuit for each of the three phases can be balanced using an integration circuit having a simple circuit configuration.

In the power supply device of the present invention, each of the three integrating circuits is connected in parallel to a capacitor charged with a current detected by the current detection circuit, and the capacitor is connected to each capacitor on and off cycles. Each of the three overcurrent protection circuits includes a resistor connected in series to the capacitor of the integrating circuit and a voltage across the resistor that exceeds a predetermined overvoltage reference value. It is preferable that the current detected by the current detection circuit is supplied to both ends of the capacitor and the resistor connected in series.

  The input current to the rectifier circuit for each of the three phases can be balanced using an integration circuit and an overcurrent protection circuit with a simple circuit configuration.

  In the power supply device of the present invention, it is preferable that the three current control circuits conduct / shut off the semiconductor switches of the corresponding DC conversion circuits by repeated signals each having a phase difference of 120 degrees.

  By providing a phase difference of 120 degrees, it is possible to reduce the ripple superimposed on the constant voltage direct current from the direct current conversion circuit. Also, smoothing is facilitated by triple the ripple frequency.

  According to the present invention, it is possible to provide a power supply device that can stably balance the input current to the rectifier circuit for each of the three phases with a simple circuit configuration.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment.

  The power supply device of the present invention conducts three rectifier circuits that generate intermediate DC voltages by rectifying two different phases among the three phases of three-phase AC and the intermediate DC voltages generated by the three rectifier circuits, respectively. A semiconductor switch that cuts off / cuts off, a transformer that transforms the voltage that is turned on / off, and a rectifier that rectifies the transformed voltage to output a DC voltage, and three DC conversion circuits that are connected in parallel An error signal detection circuit for detecting a voltage value of an output connected in parallel of the three DC conversion circuits and outputting a difference between the voltage value and a desired output reference voltage value as an error signal; Three current detection circuits for detecting currents flowing through the semiconductor switches, three integration circuits for integrating the currents detected by the three current detection circuits at regular intervals, and the corresponding DC conversion circuit. Three current controls for starting the conduction of the conductor switch at the predetermined time intervals and shutting off the semiconductor switch of the corresponding DC conversion circuit when the integration values of the three integration circuits exceed the value of the error signal, respectively. A circuit.

  An embodiment of the power supply device of the present invention is shown in FIG. In FIG. 2, 51-1, 51-2, and 51-3 are three-phase AC input terminals, respectively, 52-1, 52-2, and 52-3 are rectifier circuits that rectify AC and generate intermediate DC voltages, 53-1, 53-2 and 53-3 are semiconductor switches which conduct / shut off the intermediate DC voltage generated by the rectifier circuits 52-1, 52-2 and 52-3, respectively, and transform the conducted / shut off voltage. A DC conversion circuit that converts a voltage by a transformer and a rectifier that rectifies the transformed voltage and outputs a DC voltage, 55 detects a voltage value of an output in which each DC conversion circuit is connected in parallel, and the voltage value and a desired voltage Error signal detection circuits 57-1, 57-2, and 57-3 that output the difference from the output reference voltage value as an error signal are fed to the semiconductor switches of the DC conversion circuits 53-1, 53-2, and 53-3. Current detection circuits 58-1, 58-2, and 58-3 for detecting currents that integrate currents detected by the current detection circuits 57-1, 57-2, and 57-3, respectively, at regular intervals. The integration circuits 54-1, 54-2 and 54-3 are applicable when the integration values of the integration circuits 58-1, 58-2 and 58-3 exceed the error signal value from the error signal detection circuit 55, respectively. This is a current control circuit that shuts off the semiconductor switch of the DC conversion circuit.

  Next, the operation of the power supply device of FIG. 2 will be described. In FIG. 2, three-phase alternating current is input to the three-phase alternating current input terminals 51-1, 51-2, and 51-3, and the rectifier circuits 52-1, 52-2, and 52-3 are respectively included in the three-phase alternating current. Two different phases are rectified to generate an intermediate DC voltage. The DC conversion circuits 53-1, 53-2, and 53-3 convert the intermediate DC voltages from the rectifier circuits 52-1, 52-2, and 52-3, respectively, to generate desired constant voltage DC voltages.

  The error signal detection circuit 55 detects a DC voltage value of an output in which the DC conversion circuits 53-1, 53-2, and 53-3 are connected in parallel, and a signal obtained by subtracting a target reference voltage value from the detected voltage value. Is detected as an error signal. On the other hand, the current detection circuits 57-1, 57-2 and 57-3 detect the current flowing through the semiconductor switch which conducts / cuts off the current of the DC conversion circuits 53-1, 53-2 and 53-3. The integration circuits 58-1, 58-2 and 58-3 integrate the currents detected by the current detection circuits 57-1, 57-2 and 57-3 at regular intervals. The current control circuits 54-1, 54-2, and 54-3 are applicable when the integration values of the integration circuits 58-1, 58-2, and 58-3 are smaller than the error signal detected by the error signal detection circuit 55, respectively. When the current flowing through the semiconductor switch of the DC conversion circuit is made conductive and the integration values of the integration circuits 58-1, 58-2 and 58-3 are larger than the error signal detected by the error signal detection circuit 55, the corresponding DC conversion circuit. The current flowing through the semiconductor switch is cut off.

  As described above, in the power supply device of the present embodiment, the difference between the detected value of the output voltage of the DC converter circuit to which the error signal detection circuit 55 is connected in parallel and the target value is fed back as an error signal, and based on the error signal. Since the average current flowing through the semiconductor switches of the DC conversion circuits 53-1, 53-2 and 53-3 is controlled, the configuration of the control circuit is simplified, and the current control circuits 54-1, 54-2 and 54- Since 3 are controlled independently without adjusting each other, the circuit operation is stabilized.

  Next, a specific example of the power supply circuit will be described. FIG. 3 is a diagram illustrating the circuit configuration of the rectifier circuit 52-1. The rectifier circuits 52-2 and 52-3 have the same configuration.

  In FIG. 3, 11 is a bridge rectifier circuit, 12 is a step-up inductor, 13 is an FET switching element, 14 is a backflow prevention diode, 15 is an output smoothing capacitor, and 51-1 and 51-2 are three-phase AC input terminals.

  Two phases of the three-phase alternating current are applied between the three-phase alternating current input terminals 51-1 and 51-2, and full-wave rectified by the bridge rectifier circuit 11. The FET switching element 13 controls the conduction and interruption time so that the input current of the bridge rectifier circuit 11 becomes a sine wave in phase with the input voltage. If the input current and the input voltage are in-phase sine waves, the power factor of the rectifier circuit is improved. The output smoothing capacitor 15 is charged with a DC voltage higher than the peak voltage of the AC input by the boost inductor 12 and the backflow prevention diode 14. For example, a DC constant voltage of about 360V is possible for a three-phase AC 200V input. The output of the rectifier circuit 52-1 is input to the DC conversion circuit 53-1 as an intermediate DC voltage.

  The power supply circuit of FIG. 3 is one embodiment, and may be a rectifier circuit of another circuit type as long as AC input can be converted into DC output.

  Next, specific examples of the DC conversion circuit and the current detection circuit will be described. FIG. 4 is a diagram illustrating the circuit configuration of the DC conversion circuit 53-1 and the current detection circuit 57-1. The DC conversion circuits 53-2 and 53-3 and the current detection circuits 57-2 and 57-3 have the same configuration.

  In FIG. 4, 16 and 17 are FET switching elements as semiconductor switches, 18 and 19 are transformer reset diodes, 20 is a transformer, 21 is a rectifier diode, 22 is a flywheel diode (damper diode), 23 is a filter choke inductor, Reference numeral 24 denotes a filter capacitor, and 26 denotes a current detection transformer as a current detection circuit.

  When the intermediate DC voltage from the rectifier circuit 52-1 is input, the FET switching elements 16 and 17 convert it into a pulse signal and the voltage is reduced by the transformer 20. The FET switching elements 16 and 17 control the pulse width of the pulse signal by pulse width modulation (PWM), and increase or decrease the average output current of the transformer 20 of the DC conversion circuit 53-1. That is, when the pulse width is widened, the average output current increases, and when the pulse width is narrowed, the average output current decreases. The pulse width is controlled by a current control circuit 54-1 described later. As the semiconductor switch, a transistor switch, an IGBT (Insulated Gate Bipolar Transistor), or the like can be applied in addition to the FET switching element.

  The current detection transformer 26 detects a current Id flowing through the FET switching elements 16 and 17, and the detected current Id integrates each integration circuit at regular intervals, and as an integrated value signal, a current control circuit 54-1. And used for controlling the pulse width of the pulse signal converted by the FET switching elements 16 and 17. When the current Id flowing through the FET switching elements 16 and 17 is used to control the output voltage of the DC conversion circuit 53-1, it can be controlled in the current mode, so that a high-speed response is possible.

  The energy stored in the winding during the switch shutoff period is released through the transformer reset diodes 18 and 19 so that magnetic saturation does not occur in the transformer 20.

  The output of the transformer 20 is full-wave rectified by a rectifier diode 21 and a flywheel diode 22, smoothed by a filter choke inductor 23 and a filter capacitor 24, and becomes a constant voltage DC voltage. The output of the constant voltage DC voltage is connected in parallel with another DC conversion circuit. The output voltage of this DC conversion circuit is input to the error signal detection circuit 55.

  The DC conversion circuit 53-1 of FIG. 4 is an embodiment, and may be a DC conversion circuit of another circuit type as long as it can generate a constant voltage DC capable of current control by stepping down a high intermediate DC voltage. . The current detection circuit 57-1 is also an embodiment, and may be a current detection circuit of another circuit type as long as the current flowing through the FET switching elements 16 and 17 can be detected.

  Next, a specific example of the error signal detection circuit will be described. FIG. 5 is a diagram for explaining the circuit configuration of the error signal detection circuit 55.

  In FIG. 5, 27 and 28 are output voltage detection resistors for detecting an output voltage for dividing the output voltage value, 37 is an error signal amplifier circuit, 44 is a reference voltage, and 56-1 and 56-2 are DC outputs of the power supply device. Terminal.

  The DC conversion circuits 53-1, 53-2, and 53-3 are connected in parallel, and the DC output terminals 56-1 and 56-2 are connected to the error signal detection circuit 55. Output voltage detection resistors 27 and 28 connected in series are connected between the DC output terminals 56-1 and 56-2, and the output voltage value divided by the output voltage detection resistors 27 and 28 is detected. The detected output voltage value is input to the addition input terminal of the error signal amplifier circuit 37. A reference voltage 44 for the DC output voltage terminal 56-1 is applied to the subtraction input terminal of the error signal amplifier circuit 37. Here, the voltage division by the two output voltage detection resistors is used for the detection of the output voltage value, but the output voltage value may be detected by another element.

  The error signal amplification circuit 37 outputs a signal obtained by subtracting the input signal to the subtraction input terminal from the input signal to the addition input terminal to the current control circuits 54-1, 54-2, and 54-3 as the error signal Ve. The output of the error signal detection circuit 55 is used in common for the current control circuits 54-1, 54-2 and 54-3. The current control circuits 54-1, 54-2, and 54-3 perform control so as to eliminate the voltage difference between the addition input terminal and the subtraction input terminal of the error signal amplification circuit 37 as described later.

  The error signal detection circuit 55 of FIG. 5 is an embodiment, and may be an error signal detection circuit of another circuit type as long as the output voltage can be measured and a difference between the output voltage and the target voltage can be obtained.

  Next, specific examples of the integration circuit and the current control circuit will be described. FIG. 6 is a diagram illustrating the circuit configuration of the integrating circuit 58-1 and the current control circuit 54-1. The integration circuits 58-2 and 58-3 and the current control circuits 54-2 and 54-3 have the same configuration.

  In FIG. 6, 31 is a rectifier diode, 32 is a capacitor, 33 is a detection resistor, 34 is a discharge FET, 35 and 36 are comparators, 38 is a set-reset type flip-flop circuit, 39 is a pulse generation circuit, 40 is an inverter, 41 Is a gate reset circuit, 42 is a transformer reset diode, 43 is a transformer reset resistor, 46 is a DC reference voltage, 54-1 is a current control circuit, 58-1 is an integration circuit, and 59-1 is an overcurrent protection circuit.

  The integrating circuit 58-1 integrates the current detected by the current detecting circuit 57-1, and sends the integrated value to the current control circuit 54-1. The current control circuit 54-1 compares the error signal Ve from the error signal detection circuit 55 with the integration value of the integration circuit 58-1, and when the integration value is larger than the value of the error signal Ve, the corresponding direct current. When the pulse width of the conversion circuit is narrowed and the integral value is smaller than the value of the error signal Ve, the pulse width of the corresponding DC conversion circuit is widened, and the pulse of the FET switching element included in the corresponding DC conversion circuit Controls the pulse width for width modulation.

  That is, in the current control circuit 54-1, after the FET switching element of the DC conversion circuit 53-1 is turned on, the integration circuit 58-1 integrates the current detected by the current detection transformer as the current detection circuit, and the integrated value is When the error signal Ve from the error signal detection circuit 55 is exceeded, the FET switching elements 16 and 17 of the DC conversion circuit 53-1 are cut off to control the pulse width of the DC conversion circuit 53-1.

  A specific configuration will be described. The error signal Ve of the error signal amplification circuit 37 of the error signal detection circuit 55 is input to the addition input terminal of the comparator 35. When a monitor pulse signal from a current detection transformer 26 as a current detection circuit is input, the signal is rectified by a rectifier diode 31, integrated by a capacitor 32, and then input to the subtraction input terminal of the comparator 35 as an integration signal Vx. At this time, the drop voltage of the detection resistor 33 becomes an error of the integral value. However, if the drop voltage of the detection resistor 33 is set to be a fraction of the integration voltage, the drop voltage of the detection resistor 33 is reduced. The impact is reduced.

  Note that a magnetic flux reset circuit including a transformer reset diode 42 and a transformer reset resistor 43 is also connected to the secondary winding of the current detection transformer 26.

  On the other hand, the pulse generation circuit 39 determines the cycle and phase of the pulse subjected to the pulse width modulation of the DC conversion circuit 53-1. The output Vm from the pulse generation circuit 39 is connected to the set terminal of the set / reset type flip-flop circuit 38. When the integration signal Vx from the current detection circuit 57-1 is smaller than the error signal Ve, the output Vff of the comparator 35 becomes High. When the integration signal Vx exceeds the error signal Ve, the output Vff of the comparator 35 transitions to Low. The output Vff of the comparator 35 is connected to the reset terminal of the set / reset type flip-flop circuit 38. The output Vs of the set / reset type flip-flop circuit 38 is input to the gate circuit 41. The gate circuit 41 also receives the output Vm from the pulse generation circuit 39, and the output Vg of the gate circuit 41 determined by both inputs drives the FET switching elements 16 and 17.

  With such a configuration, the pulse width of the output Vs of the set-reset flip-flop circuit 38 is determined by the output Vm from the pulse generation circuit 39, the error signal Ve, and the integration signal Vx. In this configuration, when the conversion signal corresponding to the current flowing through the FET semiconductor switching elements 16 and 17 from the DC conversion circuit 53-1 is larger than the error signal Ve, the pulse width is narrowed, and the error signal Ve generates a signal from the DC conversion circuit. If the conversion signal corresponding to the current flowing through the FET semiconductor switching elements 16 and 17 is small, the pulse width is widened. That is, if the conversion signal corresponding to the current flowing through the FET switching elements 16 and 17 of the DC conversion circuit 53-1 is larger than the error signal Ve, the average output current of the transformer of the DC conversion circuit 53-1 is reduced, and the error signal If the conversion signal corresponding to the current flowing through the FET semiconductor switching elements 16 and 17 of the DC conversion circuit 53-1 is smaller than Ve, the average output current of the transformer of the DC conversion circuit 53-1 is increased.

  The gate circuit 41 determines the pulse width of the pulse width modulation based on the output Vm from the pulse generation circuit 39 and the output Vs from the set / reset type flip-flop circuit 38. When the output of the gate circuit 41 is in the ON state, the output current of the DC conversion circuit 53-1 is controlled so that the FET switching elements 16 and 17 of the DC conversion circuit 53-1 are conducted.

  The discharging FET 34 is turned on with the output Vm from the pulse generation circuit 39 through the inverter 40 so that the integration signal Vx is reset each time the output Vm of the pulse generation circuit 39 transitions from the off state to the on state. When the discharging FET 34 is made conductive, the charge of the capacitor 32 is discharged, and the integration signal Vx is turned off.

  The overcurrent protection circuit 59-1 will be described. A current corresponding to the current Id flowing through the FET switching elements 16 and 17 detected by the current detection transformer 26 as a current detection circuit is supplied to the detection resistor 33 and the capacitor 32 connected in series. In the normal state, the voltage of the detection resistor 33 is low. However, in an abnormal state such as a short circuit of the load, the voltage across the detection resistor 33 increases when the current Id flowing through the FET switching elements 16 and 17 increases. Since the detection resistor 33 and the capacitor 32 are connected in series, and the drop voltage of the detection resistor 33 is set lower than the integrated voltage of the capacitor 32, the drop voltage of the detection resistor 33 is a value obtained by differentiating the monitor pulse signal. That is, the voltage across the detection resistor 33 represents the rate of increase or decrease of the monitor pulse signal.

  When the voltage across the detection resistor 33 exceeds the DC reference voltage 46, the comparator 36 operates to reset the set / reset type flip-flop circuit 38, and through the gate circuit 41, the FET switching elements 16 and 17 of the DC conversion circuit 53-1. Overcurrent protection is performed to shut off the power. Since the comparator 36 detects the voltage across the detection resistor 33, it can respond instantaneously.

  In FIG. 6, the output of the comparator 36 and the output of the comparator 35 are wired-or connected. However, after both outputs are input to the OR circuit, they are connected to the reset terminal of the set-reset type flip-flop circuit 38. Also good. In FIG. 2, the overcurrent protection circuit 59-1 shown in FIG. 6 is not described, but an overcurrent protection circuit may be added to the current control circuits 54-1, 54-2, and 54-3. .

  As described above, in the power supply device of the present embodiment, the current detection transformer 26 is used to control the average output current of the transformer transformer of the DC conversion circuit and at the same time to perform instantaneous overcurrent protection. Minimizing the number of high-cost components such as current detection transformers is cost effective.

  Control of the average output current of the transformer of the DC conversion circuit will be described with reference to FIG. 7, the output Vm of the pulse generation circuit 39, the integration signal Vx, the wired OR output Vff of the comparators 35 and 36, the output Vs of the set / reset type flip-flop circuit 38, the output Vg of the gate circuit 41, and the FET switching element 16 from the upper stage. And current Id flowing through 17. Hereinafter, description will be made using the symbols described in the drawings so far.

  The pulse generation circuit 39 generates pulses at a constant cycle. In FIG. 7, the period from time t1 to t4 is a period of one pulse. When the output Vm of the pulse generation circuit 39 becomes High at time t1, the output of the inverter 40 becomes Low. When the output of the inverter 40 becomes Low, the discharging FET 34 is turned off, and the voltage of the capacitor 32 starts to be charged. Therefore, the integrated signal Vx that is an input signal to the subtracting input terminal of the comparator 35 rises. The output Vff of the comparator 35 and the comparator 36 is wired OR connected and input to the reset terminal of the set / reset type flip-flop circuit 38. Since the output signal of the comparator 36 is High when normal, the input Vff to the reset terminal of the set / reset type flip-flop circuit 38 is also High. At this time, the input Vm to the set terminal of the set-reset type flip-flop circuit 38 changes from Low to High, but the output Vs of the set-reset type flip-flop circuit 38 remains High. Since the output Vs of the set-reset flip-flop circuit 38 remains High and the output Vm of the pulse generation circuit 39 changes from Low to High, the output Vg of the gate circuit 41 changes from Low to High. Currents Id of 16 and 17 begin to flow. The current Id is detected by the secondary winding of the current detection transformer 26, and the detected current charges the capacitor 32 as the integration signal Vx.

  When the integration signal Vx exceeds the error signal Ve at time t2, the output of the comparator 35 becomes Low, so that the input Vff to the reset terminal of the set / reset flip-flop circuit 38 also changes from High to Low. At this time, the input Vm to the set terminal of the set-reset type flip-flop circuit 38 remains High, but the input Vff to the reset terminal of the set-reset type flip-flop circuit 38 also changes from High to Low. The output Vs of the type flip-flop circuit 38 changes from High to Low. Since the output Vs of the set / reset type flip-flop circuit 38 changes from High to Low while the output Vm of the pulse generation circuit 39 remains High, the output Vg of the gate circuit 41 changes from High to Low, thereby the FET switching element 16. And the current Id of 17 are cut off.

  When the output Vm of the pulse generation circuit 39 becomes low at time t3, the output of the inverter 40 becomes high. When the output of the inverter 40 becomes High, the discharging FET 34 is turned on and the voltage of the capacitor 32 is discharged. Therefore, the integration signal Vx that is an input signal to the subtracting input terminal of the comparator 35 becomes zero, and the output of the comparator 35 Becomes High. The outputs of the comparator 35 and the comparator 36 are wired or connected (Vff) and input to the reset terminal of the set-reset type flip-flop circuit 38. Since the output signal of the comparator 35 becomes High, Vff also becomes High. At this time, since the input Vm to the set terminal of the set-reset flip-flop circuit 38 has become Low, the output Vs of the set-reset flip-flop circuit 38 changes from Low to High. Even if the output Vs of the set-reset flip-flop circuit 38 becomes High, the output Vg of the gate circuit 41 does not change because the output Vm of the pulse generation circuit 39 becomes Low.

  By such an operation, the average output current of the transformer transformer of the DC conversion circuit is controlled to be a predetermined value. That is, when the current Id of the FET switching elements 16 and 17 is large, the integration signal Vx rises quickly, and the current Id of the FET switching elements 16 and 17 is cut off early. Conversely, when the current Id of the FET switching elements 16 and 17 is small, the integration signal Vx rises slowly and interrupts the current Id of the FET switching elements 16 and 17 later. Therefore, constant voltage control of the DC conversion circuit 53 is performed.

  When the error signal Ve is small, the integration signal Vx quickly exceeds the error signal Ve, and the current Id of the FET switching elements 16 and 17 is cut off early. Conversely, when the error signal Ve is large, the integration signal Vx slowly exceeds the error signal Ve, and the current Id of the FET switching elements 16 and 17 is cut off later. Accordingly, the average output current of the transformer transformer of each DC conversion circuit is adjusted independently.

  Here, the pulse generation circuit 39 is shared by the output current control circuits 54-1, 54-2 and 54-3, and one reference oscillator oscillates at a frequency three times the period of the above-described pulse to divide by three. Thus, it is desirable that each pulse having a phase difference of 120 degrees is the pulse Vm.

  When the output side of each DC conversion circuit is connected in parallel, the ripple will be about one third of that of the pulse Vm having no phase difference. Further, since the ripple frequency is also tripled, it is easy to reduce the ripple in the smoothing circuit.

  As described above, in the power supply device of this embodiment, since the average output current of the transformer transformer of each DC conversion circuit can be balanced, the current values of the three-phase AC input can also be balanced. Further, since the DC conversion circuit is controlled in the current mode, a high-speed control response is possible. Furthermore, since the current detection transformer is used for output current balancing and instantaneous overcurrent protection, it is advantageous in terms of cost.

  The power supply device according to the present invention can be used as a device that converts three-phase alternating current into direct current.

It is a figure which shows the structure of the conventional rectifier. It is a figure which shows the structure of the power supply device of this invention. It is a figure explaining the circuit structure of the rectifier circuit of the power supply device which concerns on this invention. It is a figure explaining the circuit structure of the direct current | flow conversion circuit and current detection circuit of the power supply device which concerns on this invention. It is a figure explaining the circuit structure of the error signal detection circuit of the power supply device which concerns on this invention. It is a figure explaining the circuit structure of the integration circuit of the power supply device which concerns on this invention, and a current control circuit. It is a figure explaining operation | movement of the power supply device which concerns on this invention.

Explanation of symbols

11: Bridge rectifier circuit 12: Boost inductor 13: FET switching element 14: Backflow prevention diode 15: Output smoothing capacitors 16 and 17: FET switching elements 18 and 19: Transformer reset diode 20: Transformer transformer 21: Rectifier diode 22: Flywheel Diode (damper diode)
23: filter choke inductor 24: filter capacitor 26: current detection transformers 27 and 28: output voltage detection resistor 31: rectifier diode 32: capacitor 33: detection resistor 34: discharge FET
35 and 36: Comparator 37: Error signal amplification circuit 38: Set / reset type flip-flop circuit 39: Pulse generation circuit 40: Inverter 41: Gate circuit 42: Transformer reset diode 43: Transformer reset resistor 44: Reference voltage 46: Reference of direct current Voltages 51-1, 51-2, 51-3, 81-1, 81-2 and 81-3: three-phase AC input terminals 52-1, 52-2, 52-3, 82-1, 82-2 and 82-3: Rectifier circuits 53-1, 53-2 and 53-3: DC conversion circuits 54-1, 54-2 and 54-3: Current control circuit 55: Error signal detection circuits 56-1 and 56-2: DC output terminals 57-1, 57-2, 57-3 of the power supply device: current detection circuits 58-1, 58-2, 58-3: integration circuit 59-1: overcurrent protection circuits 83-1, 83-2 And 83 3: constant voltage generating circuit 84-1 and 84-2 and 84-3: output current control circuit 85-1 and 85-2, and 85-3: error signal detection circuit 86-1,86-2: DC output terminals

Claims (2)

Three rectifier circuits that rectify different two phases of the three phases of the three-phase AC to generate an intermediate DC voltage;
Voltage conversion is performed by a semiconductor switch that conducts / cuts off the intermediate DC voltage generated by the three rectifier circuits, a transformer that transforms the conducted / cut off voltage, and a rectifier that rectifies the transformed voltage, and outputs a DC voltage. A diode for resetting the transformer is turned on during the shut-off period of the semiconductor switch, and three DC conversion circuits in which the output is connected in parallel;
An error signal detection circuit that detects a voltage value of an output connected in parallel of the three DC conversion circuits and outputs a difference between the voltage value and a desired output reference voltage value as an error signal;
Three current detection circuits for respectively detecting currents flowing through the three semiconductor switches;
Three integration circuits for integrating the currents detected by the three current detection circuits for each on / off period of the semiconductor switch;
The conduction of the semiconductor switch of the corresponding DC conversion circuit is started every ON / OFF cycle of the semiconductor switch, and when the integration values of the three integration circuits exceed the value of the error signal, the corresponding DC conversion circuit Three current control circuits that shut off the semiconductor switch;
Three overcurrent protection circuits that shut off the semiconductor switch of the DC conversion circuit when each of the current values detected by the three current detection circuits exceeds a predetermined overcurrent reference value ;
Each of the three integrating circuits includes a capacitor that is charged with a current detected by the current detection circuit, and a discharge switch that is connected in parallel to the capacitor and discharges the charge of the capacitor every on / off period of the semiconductor switch. Including
Each of the three overcurrent protection circuits includes a resistor connected in series to the capacitor of the integration circuit, and a semiconductor of the corresponding DC conversion circuit when a voltage across the resistor exceeds a predetermined overvoltage reference value. Includes a comparison circuit that shuts off the switch,
The power supply device, wherein the current detected by the current detection circuit is passed through both ends of the capacitor and the resistor connected in series . 2. The power supply device according to claim 1, wherein the three current control circuits conduct / shut off the semiconductor switch of the corresponding DC conversion circuit by a repetitive signal having a phase difference of 120 degrees. .

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