JPH11113256A - Three-phase power factor improved converter - Google Patents

Three-phase power factor improved converter

Info

Publication number
JPH11113256A
JPH11113256A JP28786797A JP28786797A JPH11113256A JP H11113256 A JPH11113256 A JP H11113256A JP 28786797 A JP28786797 A JP 28786797A JP 28786797 A JP28786797 A JP 28786797A JP H11113256 A JPH11113256 A JP H11113256A
Authority
JP
Japan
Prior art keywords
phase
current
converter
converters
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28786797A
Other languages
Japanese (ja)
Other versions
JP3530359B2 (en
Inventor
Yoshiaki Matsumoto
義明 松本
Yasuyuki Nukui
靖之 貫井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP28786797A priority Critical patent/JP3530359B2/en
Publication of JPH11113256A publication Critical patent/JPH11113256A/en
Application granted granted Critical
Publication of JP3530359B2 publication Critical patent/JP3530359B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a three-phase power factor improved converter which can suppress the occurrence of ripple currents and higher harmonics and can accomplish current balance in each phase, by connecting three sets of single- phase converters having higher harmonic suppressing function among the phases of a three-phase three-wire AC power source. SOLUTION: In a three-phase power factor improved converter in which three sets of single-phase converters having higher harmonic suppressing functions are connected among the phases of a three-phase three-wire AC power source, high harmonic suppressing circuits 1, 17, and 18 and insulated DC-DC converters 8, 19, and 20 are respectively connected to the single-phase converters. The circuits 1, 17, and 18 are respectively composed of rectifier circuits and boosting chopper circuits which boost the outputs of the rectifier circuits to high DC voltages. The outputs of the insulated DC-DC converters 8, 19, and 20 which input the outputs of the boosting chopper circuits are connected in parallel with each other. Each insulated DC-DC converter 8, 19, and 20 has a current mode control circuit 23 composed of an output voltage detecting error amplifier 22 which outputs control signals commonly to the converters 8, 19, and 19.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は,3相3線式交流給電に
おける高調波電流抑制機能を備えた3相力率改善形コン
バータに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-phase power factor improving converter having a harmonic current suppressing function in a three-phase three-wire AC power supply.

【0002】[0002]

【従来の技術】3相3線式交流給電において,単相の高
調波抑制機能を有する入出力絶縁型コンバータ3台を各
相間に接続し,その各出力を並列に接続して,電源回路
を構成する方法が知られている。
2. Description of the Related Art In a three-phase three-wire AC power supply, three input / output insulated converters each having a single-phase harmonic suppression function are connected between each phase, and their outputs are connected in parallel to form a power supply circuit. Methods of construction are known.

【0003】この回路構成で各コンバータに制御回路を
個別に持たせた場合,各相の電流バランス,すなわち,
各コンバータが分担する負荷電流は必ずしも同一になら
ない。したがって電流バランスをとる機能が必要とな
る。 (2) 各相のDC−DCコンバータの主スイッチを同一の制御
信号で駆動し,昇圧チョッパの出力電圧のレギュレーシ
ョンにより各相の電流をバランスさせることが特願平9
−120358で提案されている。
When each converter is provided with a control circuit individually in this circuit configuration, the current balance of each phase, that is,
The load current shared by each converter is not always the same. Therefore, a function for balancing current is required. (2) The main switch of the DC-DC converter of each phase is driven by the same control signal, and the current of each phase is balanced by regulating the output voltage of the step-up chopper.
−1120358.

【0004】図4はこの回路例を示すものである。図4
で1,17,18は昇圧型の高調波抑制回路で入力は各
々3相3線式の各相間に接続される。出力は各々絶縁型
DC−DCコンバータの入力に接続されている。各DC
−DCコンバータ8,19,20の出力は並列に接続さ
れ負荷16に直流電力を供給する。高調波抑制回路部
1,17,18は各々整流ダイオードブリッジ2,チョ
ークコイル3,スイッチング素子4,ダイオード5,平
滑用コンデンサ6,及び制御回路7で構成さる昇圧型高
調波抑制回路である。
FIG. 4 shows an example of this circuit. FIG.
Numerals 1, 17, and 18 denote step-up type harmonic suppression circuits whose inputs are connected between the respective phases of a three-phase three-wire system. The outputs are each connected to the input of an isolated DC-DC converter. Each DC
The outputs of the DC converters 8, 19 and 20 are connected in parallel to supply DC power to the load 16; The harmonic suppression circuit sections 1, 17, and 18 are step-up harmonic suppression circuits each including a rectifier diode bridge 2, a choke coil 3, a switching element 4, a diode 5, a smoothing capacitor 6, and a control circuit 7.

【0005】DC−DCコンバータ部8,19,20は
それぞれ同時にオンオフする主スイッチ9と10,変圧
器11,整流ダイオード12,フライホイールダイオー
ド13,平滑用チョークコイル14,平滑用コンデンサ
15で構成されるフォワードコンバータである。22は
出力電圧検出誤差増幅器で出力電圧を基準値と比較しそ
の誤差を増幅する。22の出力信号は幅制御回路25に
送られ,出力電圧を一定に保つために必要なコンバータ
のパルス幅を決める。また変流器でスイッチング電流を
検出しパルス幅を制御し過電流保護を行う。
The DC-DC converters 8, 19 and 20 are respectively composed of main switches 9 and 10, which are simultaneously turned on and off, a transformer 11, a rectifier diode 12, a flywheel diode 13, a smoothing choke coil 14, and a smoothing capacitor 15. Forward converter. An output voltage detection error amplifier 22 compares the output voltage with a reference value and amplifies the error. The output signal of 22 is sent to the width control circuit 25 and determines the pulse width of the converter necessary to keep the output voltage constant. The current transformer detects the switching current and controls the pulse width to provide overcurrent protection.

【0006】3個のDC−DCコンバータ8,19,2
0は同一のパルスで駆動されるため,DC−DCコンバ
ータの入力電圧,すなわち高調波抑制回路の出力電圧が
一定で,各部品の特性が同じであれば,各DC−DCコ
ンバータ8,19,20の電流はバランスし,これらの
入力電源である高調波抑制回路1,17,18の電流も
バランスする。 (3)
The three DC-DC converters 8, 19, 2
Since 0 is driven by the same pulse, if the input voltage of the DC-DC converter, that is, the output voltage of the harmonic suppression circuit is constant and the characteristics of each component are the same, each DC-DC converter 8, 19, The current of 20 is balanced, and the currents of the harmonic suppression circuits 1, 17, and 18 as input power sources are also balanced. (3)

【0007】実際には各部品の特性はばらついている
が,高調波抑制回路の出力電圧は出力電流に対してマイ
ナスの変動特性を持っているため,電流が増加するとD
C−DCコンバータの入力電圧が下がり電流を減らす作
用をするためバランスを保つように作用する。このよう
に,この方式によれば非常に簡単な回路で各相の入力の
高調波電流の抑制と電流バランスを満足させることがで
きる。
Actually, the characteristics of the components vary, but the output voltage of the harmonic suppression circuit has a negative fluctuation characteristic with respect to the output current.
The input voltage of the C-DC converter decreases to reduce the current, and thus acts to maintain the balance. As described above, according to this method, it is possible to suppress the harmonic current at the input of each phase and satisfy the current balance with a very simple circuit.

【0008】しかし,このような従来技術では次のよう
な問題点がある。全波整流された入力電流は平滑用コン
デンサ6で平滑されるが,入力電流とコンデンサの容
量,特性で決まるリップル電圧が発生する。昇圧チョッ
パの出力,すなわち,DC−DCコンバータの入力は商
用電源の1周期の平均値は各相間で同じでも,リップル
電圧は各相のAC入力電圧の位相差に対応しているの
で,瞬時を考えると,各相間で位相に対応した差があ
る。
However, such a conventional technique has the following problems. The input current that has been subjected to full-wave rectification is smoothed by the smoothing capacitor 6, but a ripple voltage is generated which is determined by the input current, the capacitance and characteristics of the capacitor. Although the output of the step-up chopper, that is, the input of the DC-DC converter, has the same average value in one cycle of the commercial power supply in each phase, the ripple voltage corresponds to the phase difference of the AC input voltage of each phase. Considering this, there is a difference corresponding to the phase between each phase.

【0009】したがって,各相のDC−DCコンバータ
の主スイッチを同一の制御信号で駆動した場合,各相の
DC−DCコンバータの電流は入力電圧と正の関係で変
化するので,前記リップル電圧と同位相のリップル電流
が重畳される。
Therefore, when the main switch of the DC-DC converter of each phase is driven by the same control signal, the current of the DC-DC converter of each phase changes in a positive relationship with the input voltage. In-phase ripple currents are superimposed.

【0010】このリップル電流によりDC−DCコンバ
ータの各部の電流の実効値が増加するため,電力損失が
大きくなる。また,このリップル電流を減らそうとする
と,高調波抑制回路の出力平滑用コンデンサ6の容量を
大きくする必要があるため,装置の外形寸法が大きくな
る等の欠点がある。
[0010] The ripple current increases the effective value of the current in each part of the DC-DC converter, resulting in a large power loss. Further, in order to reduce the ripple current, it is necessary to increase the capacity of the output smoothing capacitor 6 of the harmonic suppression circuit.

【0011】また,3相力率改善形コンバータの出力電
流(3台のDC−DCコンバータの並列接続点から見た
負荷電流)を検出し,電流分担装置より電流指令を昇圧
チョッパまたはDC−DCコンバータに与え,各相の電
流をバランスさせる方式も提案されている。 (4)
Also, the output current of the three-phase power factor correction type converter (load current as viewed from the parallel connection point of the three DC-DC converters) is detected, and a current command is sent from the current sharing device to the boost chopper or the DC-DC converter. A method has also been proposed in which a current is supplied to a converter to balance the current of each phase. (4)

【0012】図5はこの方式の一例を示すもので,同一
符号は図4と同じ回路部,部品を示す。28は直流電流
の検出器で,27は分担信号発生器で電流検出器の電圧
を増幅し分担電流の指令電圧を発生する。26は電流制
御部であり,変流器21からユニットの電流を検出し,
27の信号との誤差がなくすように,出力電圧制御用の
基準電圧を制御しパルス幅制御部25に送出する。25
ではこの基準電圧と出力電圧検出誤差増幅器22の出力
を比較しパルス幅を決定する。
FIG. 5 shows an example of this method. The same reference numerals indicate the same circuit parts and components as those in FIG. Reference numeral 28 denotes a DC current detector, and reference numeral 27 denotes a shared signal generator, which amplifies the voltage of the current detector and generates a command voltage of the shared current. 26 is a current control unit which detects the current of the unit from the current transformer 21 and
The reference voltage for controlling the output voltage is controlled and sent to the pulse width control unit 25 so as to eliminate the error from the signal 27. 25
Then, the reference voltage is compared with the output of the output voltage detection error amplifier 22 to determine the pulse width.

【0013】ドライブ回路24はこのパルス幅で主スイ
ッチを駆動する。したがってDC−DCコンバータの電
流は常にバランスがとれ,これを負荷とする高調波抑制
回路の電流もバランスする。また,前記のリップル電流
も抑制できる。しかしながら,回路構成と各制御部2
8,27,26は複雑でありコストアップは避けられな
い。また部品増加により実装スペースがより必要となり
小型化の障害となっている。このように,従来技術にお
いては,リップル電流により各部の電流実効値が大きく
なり,電力損失が大きくなる欠点があった。このリップ
ル電流を抑制しようとする場合は,平滑用コンデンサで
対応すると大容量の電解コンデンサが必要となり,ま
た,電子回路で対応すると電流検出器,負荷分担制御装
置が必要でコストが高く,外形寸法が大きくなる欠点が
あった。
The drive circuit 24 drives the main switch with this pulse width. Therefore, the current of the DC-DC converter is always balanced, and the current of the harmonic suppression circuit using this as a load is also balanced. Further, the ripple current can be suppressed. However, the circuit configuration and each control unit 2
8, 27 and 26 are complicated and cost increase is inevitable. In addition, an increase in the number of components requires more mounting space, which is an obstacle to miniaturization. As described above, the conventional technology has a drawback that the ripple current causes the effective current value of each part to increase, and the power loss to increase. To suppress this ripple current, a large-capacity electrolytic capacitor is required if a smoothing capacitor is used, and a current detector and a load-sharing control device are required if an electronic circuit is used. Had the disadvantage of becoming larger.

【0014】[0014]

【発明が解決しようとする課題】本発明はDC−DCコ
ンバータの制御に電流モード制御回路を使用することに
より,簡単な回路構成でリップル電流を抑制し,かつ高
調波抑制,各相の電流バランスを達成するものである。 (5)
SUMMARY OF THE INVENTION The present invention uses a current mode control circuit to control a DC-DC converter, thereby suppressing ripple current with a simple circuit configuration, suppressing harmonics, and balancing the current of each phase. Is to achieve. (5)

【0015】[0015]

【課題を解決しようとする手段】3相3線式交流電源各
相間に,高調波抑制機能を有した単相コンバータ3組を
接続した3相力率改善形コンバータにおいて,各単相コ
ンバータは高調波抑制回路と絶縁型DC−DCコンバー
タが各々1個づつ接続される。高調波抑制回路は整流回
路と前記整流回路の出力を直流高電圧に昇圧する昇圧チ
ョッパ回路からなる,昇圧チョッパ回路の出力を入力と
した絶縁型DC−DCコンバータの各出力は並列接続さ
れる。前記絶縁型DC−DCコンバータは電流モード制
御回路を持ち,前記絶縁型DC−DCコンバータは出力
電圧検出誤差増幅器の出力で共通に制御されている。
SUMMARY OF THE INVENTION In a three-phase power factor correction type converter in which three sets of single-phase converters having a harmonic suppression function are connected between each phase of a three-phase three-wire AC power supply, each single-phase converter has a The wave suppression circuit and the isolated DC-DC converter are connected one by one. The harmonic suppression circuit includes a rectifier circuit and a boost chopper circuit that boosts the output of the rectifier circuit to a high DC voltage. The outputs of the isolated DC-DC converter that receives the output of the boost chopper circuit as inputs are connected in parallel. The insulated DC-DC converter has a current mode control circuit, and the insulated DC-DC converter is commonly controlled by an output of an output voltage detection error amplifier.

【0016】[0016]

【実施例】図1は本発明の一実施例を示すもので,図
4,5と同一符号の回路部,部品は同一内容を示す。図
2は電流モード制御のブロック図で図1と同一符号は同
一内容を示す。また,図3は図2の動作を示すもので,
波形の符号は図2の各部を示す符号と対応する。
FIG. 1 shows an embodiment of the present invention, in which circuit portions and components having the same reference numerals as those in FIGS. FIG. 2 is a block diagram of the current mode control, and the same reference numerals as those in FIG. FIG. 3 shows the operation of FIG.
The signs of the waveforms correspond to the signs indicating the respective parts in FIG.

【0017】はじめに,図2,図3にて電流モード制御
について説明する。図2で,23は電流モード制御回路
の1例を示すブロック図である。クロックパルス発生器
53のクロックパルス(図3のD)でフリップフロップ
54はセットされる。フリップフロップ54はセットさ
れるとリセットされるまで,駆動回路24に主スイッチ
がオンする信号(図3のE)を送出し,主スイッチ9,
10を同時にオンさせる。主スイッチ9,10がオンす
るとトランス11の一次コイルNpにDC−DCコンバー
タの入力電圧(コンデンサ6の電圧)Vcが印加される。
トランス11の二次コイルNsに電圧Vc×Ns/Npが
発生し、ダイオード12がオンし,チョークコイル1
4,コンデンサ15を介して直流電力を出力する。主ト
ランジスタ9,10がオンの期間チョークコイル14に
はトランス二次電圧と出力電圧の差が印加され,次の式
にて決定される電流傾斜でチョーク電流は増 (6) 加する。 di/dt=(Vc×Ns/Np−Vo)/L ・・(1) ここでLはチョークコイル14のインダクタンスであ
る。
First, the current mode control will be described with reference to FIGS. In FIG. 2, reference numeral 23 is a block diagram showing an example of the current mode control circuit. The flip-flop 54 is set by the clock pulse (D in FIG. 3) of the clock pulse generator 53. When set, the flip-flop 54 sends a signal (E in FIG. 3) for turning on the main switch to the drive circuit 24 until the flip-flop 54 is reset.
10 are turned on simultaneously. When the main switches 9 and 10 are turned on, the input voltage (voltage of the capacitor 6) Vc of the DC-DC converter is applied to the primary coil Np of the transformer 11.
The voltage Vc × Ns / Np is generated in the secondary coil Ns of the transformer 11, the diode 12 turns on, and the choke coil 1
4. The DC power is output via the capacitor 15. While the main transistors 9 and 10 are on, the difference between the transformer secondary voltage and the output voltage is applied to the choke coil 14, and the choke current increases with the current gradient determined by the following equation (6). di / dt = (Vc × Ns / Np−Vo) / L (1) where L is the inductance of the choke coil 14.

【0018】主スイッチ9,10がオンの期間はチョー
ク14の電流波形とトランス二次電流波形は同じであ
り,トランス一次電流波形は相似である。トランス一次
電流波形をCT21で検出し,電流波形検出器52で電
圧波形に変換している。電流波形検出器52の信号(図
3のB)と出力電圧誤差増幅器の出力(図3のA)を比
較器51で比較しB>Aのときフリップフロップ54の
リセット信号(図3のC)を発生する。
While the main switches 9 and 10 are on, the current waveform of the choke 14 and the transformer secondary current waveform are the same, and the transformer primary current waveform is similar. The transformer primary current waveform is detected by the CT 21 and converted into a voltage waveform by the current waveform detector 52. The signal (B in FIG. 3) of the current waveform detector 52 and the output (A in FIG. 3) of the output voltage error amplifier are compared by the comparator 51. When B> A, the reset signal of the flip-flop 54 (C in FIG. 3). Occurs.

【0019】フリップフロップ54はリセットされてか
ら再びセットされるまで,主スイッチ9,10がオフと
なるように信号Eを駆動回路24に送出する。主スイッ
チ9,10がオフの期間チョークコイル14の電流は減
少する。クロックパルス発生器53の次のクロックパル
スでフリップフロップ54がセットされ次のサイクルに
はいる。
The flip-flop 54 sends a signal E to the drive circuit 24 so that the main switches 9 and 10 are turned off until the flip-flop 54 is reset and set again. While the main switches 9 and 10 are off, the current of the choke coil 14 decreases. The flip-flop 54 is set by the next clock pulse of the clock pulse generator 53, and enters the next cycle.

【0020】このようにして,出力電圧誤差増幅器の出
力よってパルス幅が制御され,出力は定電圧に制御され
る。ここで重要なことはパルス幅が制御される過程で,
電流波形検出器52の信号(図3のB)と出力電圧誤差
増幅器の出力(図3のA)を比較器51で比較しB>A
のときフリップフロップ54のリセット信号(図3の
C)を発生し,主スイッチ9,10をターンオフしてい
ることである。
Thus, the pulse width is controlled by the output of the output voltage error amplifier, and the output is controlled to a constant voltage. What is important here is the process of controlling the pulse width.
The signal (B in FIG. 3) of the current waveform detector 52 and the output (A in FIG. 3) of the output voltage error amplifier are compared by the comparator 51, and B> A
At this time, the reset signal (C in FIG. 3) of the flip-flop 54 is generated, and the main switches 9 and 10 are turned off.

【0021】つまり,出力電圧誤差増幅器の出力でDC
−DCコンバータの電流が制御されることである。図3
は負荷が変化した場合に,出力電圧を一定にとである。
図3は負荷が変化した場合に、出力電圧を一定にするよ
うに出力電圧検出誤差増幅器の出力Aの変化に対応して
パルス電流が変化する様子を図示している。 (7) 負荷電流が大きい時は,電流波形のピーク値が高くなる
ように誤差増幅器22の出力信号Aの電圧は高く,オン
パルス(図3のE)の幅は広くなる。負荷電流が少ない
時は,電流波形のピーク値が低くなるように誤差増幅器
22の出力信号Aの電圧は低く,オンパルス(図3の
E)の幅は狭くなる。
That is, when the output of the output voltage error amplifier is DC
The current of the DC converter is controlled. FIG.
Means that the output voltage is kept constant when the load changes.
FIG. 3 shows how the pulse current changes in response to a change in the output A of the output voltage detection error amplifier so that the output voltage becomes constant when the load changes. (7) When the load current is large, the voltage of the output signal A of the error amplifier 22 is high so that the peak value of the current waveform is high, and the width of the on-pulse (E in FIG. 3) is wide. When the load current is small, the voltage of the output signal A of the error amplifier 22 is low so that the peak value of the current waveform is low, and the width of the on-pulse (E in FIG. 3) is narrow.

【0022】このように,電流波形検出器52の出力波
形のピーク値は出力電圧検出誤差増幅器22の出力信号
Aの電圧と同じとなるように制御される。電流波形検出
器52の出力波形はパルス電流波形と相似であるので,
パルス電流波形のピーク値はAと比例する。信号Aは各
DC−DCコンバータに共通に送られるため各DC−D
Cコンバータのパルス電流波形のピーク値は同じとな
る。ここで n:D/Dのトランス11の巻数比,T:D/Dの発振
周期 Ip:D/D出力平滑チョークの電流ピーク値 Vp:PFC出力電圧,Wp:PFCの出力電力 ΔI:平滑チョークのリップル電流のp−p値 (D/DはDC−DCコンバータ,PFCは高調波抑制
回路を示す。)とすると,Id:D/Dの出力電流は簡易
的に(2)式で示される。 Id≒Ip−(ΔI/2)×(Vo+ΔVo/(n×(Vp+ΔVp)))・・・(2) これよりDC−DCコンバータの出力電流IdはIpから
(2)式の第二項を差し引いた値となる。ΔVo,ΔVpは
ダイオードの順方向電圧等各部のドロップ電圧の合計で
ある。これらがばらついても第二項の変化はIpに比べ十
分小さい。またIpはパルス電流のピーク値とほぼ比例関
係にあるので,出力電流Idは信号Aの電圧にほぼ比例す
ることになる。 Wi:入力電力,Vi:入力電圧,Ii:入力電流とすると
(3)式となる。 Wi=Vi×Ii≒Wp=Vo×Id・・・(3) (8) (2),(3)式よりIiも信号Aの電圧に比例すること
になり,各相の入力電流はバランスする。また(2)式
でVpがPFC出力のリップル電圧で変化してもIdの変化
は十分小さい。例えばリップル電圧がVpの10%,ΔI
がIpの20%とすると(2)式の第二項はIpの2%とな
り,PFCの出力のリップル電圧によるDC−DCコン
バータのリップル電流は十分低減される。
As described above, the peak value of the output waveform of the current waveform detector 52 is controlled to be the same as the voltage of the output signal A of the output voltage detection error amplifier 22. Since the output waveform of the current waveform detector 52 is similar to the pulse current waveform,
The peak value of the pulse current waveform is proportional to A. Since the signal A is sent to each DC-DC converter in common, each DC-D
The peak value of the pulse current waveform of the C converter is the same. Here, n: turns ratio of the D / D transformer 11, T: oscillation cycle of D / D Ip: current peak value of D / D output smoothing choke Vp: PFC output voltage, Wp: output power of PFC ΔI: smoothing choke (Where D / D is a DC-DC converter and PFC is a harmonic suppression circuit), the output current of Id: D / D is simply expressed by equation (2). . Id ≒ Ip− (ΔI / 2) × (Vo + ΔVo / (n × (Vp + ΔVp))) (2) From this, the output current Id of the DC-DC converter is obtained by subtracting the second term of the expression (2) from Ip. Value. ΔVo and ΔVp are the sum of the drop voltage of each part such as the forward voltage of the diode. Even if they vary, the change in the second term is sufficiently smaller than Ip. Further, since Ip is substantially proportional to the peak value of the pulse current, the output current Id is substantially proportional to the voltage of the signal A. If Wi: input power, Vi: input voltage, and Ii: input current, equation (3) is obtained. Wi = Vi × Ii ≒ Wp = Vo × Id (3) (8) From the equations (2) and (3), Ii is also proportional to the voltage of the signal A, and the input current of each phase is balanced. . Further, even if Vp changes with the ripple voltage of the PFC output in the equation (2), the change of Id is sufficiently small. For example, the ripple voltage is 10% of Vp, ΔI
Is 20% of Ip, the second term of the expression (2) becomes 2% of Ip, and the ripple current of the DC-DC converter due to the ripple voltage of the output of the PFC is sufficiently reduced.

【0023】以上より,共通の出力電圧誤差増幅器の出
力で各相の電流バランスがとれ,かつ各DC−DCコン
バータのリップル電流も軽減されることが明らかであ
る。
From the above, it is apparent that the current of each phase can be balanced by the output of the common output voltage error amplifier, and the ripple current of each DC-DC converter can be reduced.

【0024】[0024]

【発明の効果】このように本発明によれば,単相の高調
波抑制機能を有する入出力絶縁型コンバータ3台を各相
間に接続し,その各出力を並列に接続して構成される3
相力率改善形コンバータにおいて,簡単な制御で入力電
流の相間バランスをとることができるとともに,高調波
抑制回路の出力のリップル電圧によるDC―DCコンバ
ータのリップル電流を十分低減でき,電力損失の低減が
はかれる。その結果,3相力率改善形コンバータを低コ
スト,小型で実現できるため,通信機用電源装置,大型
コンピュータ用電源装置などに使用すれば,低コスト,
小型化に有効である。
As described above, according to the present invention, three input / output insulated converters each having a single-phase harmonic suppression function are connected between each phase, and their outputs are connected in parallel.
In a phase power factor improved converter, the input current can be balanced between the phases by simple control, and the ripple current of the DC-DC converter due to the ripple voltage of the output of the harmonic suppression circuit can be sufficiently reduced, reducing the power loss. Is peeled off. As a result, a three-phase power factor correction type converter can be realized at low cost and small size.
It is effective for miniaturization.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施例を示す。FIG. 1 shows an embodiment of the present invention.

【図2】 電流モード制御のブロック図である。FIG. 2 is a block diagram of current mode control.

【図3】 図2の動作説明図である。FIG. 3 is an operation explanatory diagram of FIG. 2;

【図4】 従来の方式説明図である。FIG. 4 is an explanatory diagram of a conventional method.

【図5】 従来の方式説明図である。 (9)FIG. 5 is an explanatory diagram of a conventional system. (9)

【符号の説明】[Explanation of symbols]

1, 17,18は昇圧型の高調波抑制回路 2は整流ダイオードブリッジ 3はチョークコイル 4はスイッチング素子 5はダイオード 6は平滑用コンデンサ 7は制御回路 8, 19,20はDC−DCコンバータ 9と10は主スイッチ 11は変圧器 12は整流ダイオード 13はフライホイールダイオード 14は平滑用チョークコイル 15は平滑用コンデンサ 16は負荷 21は変流器 22は出力電圧検出誤差増幅器 23は電流モード制御回路 24は駆動回路 25はパルス幅制御部 26は電流制御部 27は分担信号発生器 28は直流電流の検出器 51は比較器 (10) 52は電流波形検出器 53はクロックパルス発生器 54はフリップフロップ 1, 17 and 18 are boost type harmonic suppression circuits 2 are rectifier diode bridges 3 are choke coils 4 are switching elements 5 are diodes 6 are smoothing capacitors 7 are control circuits 8, 19 and 20 are DC-DC converters 9 10 is a main switch 11 is a transformer 12 is a rectifier diode 13 is a flywheel diode 14 is a smoothing choke coil 15 is a smoothing capacitor 16 is a load 21 is a current transformer 22 is an output voltage detection error amplifier 23 is a current mode control circuit 24 Is a drive circuit 25 is a pulse width control unit 26 is a current control unit 27 is a shared signal generator 28 is a DC current detector 51 is a comparator (10) 52 is a current waveform detector 53 is a clock pulse generator 54 is a flip-flop

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 3相3線式交流電源各相間に,高調波抑
制機能を有した単相コンバータ3組を接続した3相力率
改善形コンバータにおいて,前記各相間の単相入力電源
に整流回路と前記整流回路の出力を直流高電圧に昇圧す
る昇圧チョッパ回路と,前記昇圧チョッパ回路の出力を
入力とした絶縁型DC−DCコンバータとを各々接続
し,前記絶縁型DC−DCコンバータの各出力を並列接
続し,かつ前記絶縁型DC−DCコンバータは共通の出
力電圧検出誤差信号により制御されることを特徴とする
3相力率改善形コンバータ。
1. A three-phase three-wire AC power supply, wherein three sets of single-phase converters having a function of suppressing harmonics are connected between each phase. A boost chopper circuit that boosts the output of the rectifier circuit to a DC high voltage, and an isolated DC-DC converter that receives the output of the boost chopper circuit as an input, and connects each of the isolated DC-DC converters. A three-phase power factor improving converter, wherein outputs are connected in parallel, and the isolated DC-DC converter is controlled by a common output voltage detection error signal.
【請求項2】 前記絶縁型DC−DCコンバータは,前
記出力電圧検出誤差信号によりスイッチング電流波形の
ピーク値が制御される電流モード制御回路を備えたフォ
ワード形コンバータであることを特徴とする請求項1記
載の3相力率改善形コンバータ。
2. The isolated DC-DC converter is a forward converter having a current mode control circuit in which a peak value of a switching current waveform is controlled by the output voltage detection error signal. 3. The three-phase power factor improving converter according to 1.
JP28786797A 1997-10-03 1997-10-03 Three-phase power factor improving converter Expired - Lifetime JP3530359B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28786797A JP3530359B2 (en) 1997-10-03 1997-10-03 Three-phase power factor improving converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28786797A JP3530359B2 (en) 1997-10-03 1997-10-03 Three-phase power factor improving converter

Publications (2)

Publication Number Publication Date
JPH11113256A true JPH11113256A (en) 1999-04-23
JP3530359B2 JP3530359B2 (en) 2004-05-24

Family

ID=17722786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28786797A Expired - Lifetime JP3530359B2 (en) 1997-10-03 1997-10-03 Three-phase power factor improving converter

Country Status (1)

Country Link
JP (1) JP3530359B2 (en)

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Publication number Priority date Publication date Assignee Title
KR100408453B1 (en) * 2001-10-29 2003-12-06 주식회사 동한피앤에스 Free voltage rectifier for both single and three-phase inputs
JP2005223978A (en) * 2004-02-04 2005-08-18 Fuji Electric Fa Components & Systems Co Ltd Motor drive
JP2006353048A (en) * 2005-06-20 2006-12-28 Origin Electric Co Ltd Power supply
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JP2008182870A (en) * 2007-03-28 2008-08-07 Kaga Electronics Co Ltd Power system
JP2012010507A (en) * 2010-06-25 2012-01-12 Mitsubishi Electric Corp Dc power supply device
JP2013058477A (en) * 2011-09-07 2013-03-28 Tai-Her Yang Lighting apparatus
JP2013074763A (en) * 2011-09-29 2013-04-22 Origin Electric Co Ltd Power conversion device and control method thereof
KR101280900B1 (en) * 2011-10-17 2013-07-02 조향숙 Device for optimizing energy usage in multiphase ac power source
JP2016185017A (en) * 2015-03-26 2016-10-20 新電元工業株式会社 Power supply device and power supply control method
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