JP5112111B2 - DC power supply and grid-connected inverter system using this DC power supply - Google Patents

Description

  The present invention relates to a DC power supply device that outputs an output voltage of a DC power supply that is boosted or reduced by a plurality of DC / DC converter circuits connected in parallel to each other, and a grid-connected inverter system using the DC power supply device.

  2. Description of the Related Art Conventionally, a direct current power supply device has been developed in which a plurality of DC / DC converter circuits are connected in parallel with each other, and a direct current voltage output from a direct current power supply is stepped up or stepped down by each DC / DC converter circuit. In the case of such a DC power supply device, the load applied to each DC / DC converter circuit can be suppressed by distributing the flowing current. However, since the characteristics of the elements (reactor, capacitor, IGBT, etc.) constituting each DC / DC converter circuit do not match, the internal impedances are different, and the currents flowing through the DC / DC converter circuits do not match. In this case, if the current is biased and flows in a large amount in one DC / DC converter circuit, the elements constituting the DC / DC converter circuit are destroyed or deteriorated.

  In order to suppress this, a method (hereinafter referred to as “balance control”) for controlling the current flowing through each DC / DC converter circuit to be equal has been developed. For example, in Japanese Patent No. 3419443, each DC / DC converter circuit is detected by detecting an imbalance in output current of each DC / DC converter circuit and adjusting a PWM signal input to each DC / DC converter circuit. A DC power supply device is described that controls the flowing currents to be equal.

  FIG. 10 is a diagram for explaining such a conventional DC power supply device. FIG. 1A is a block diagram showing a basic configuration of a conventional DC power supply device. FIG. 2B is a block diagram showing a basic configuration of a PWM signal generation circuit of a conventional DC power supply device.

  The DC power supply device B ′ has, as a basic configuration, a DC power supply 110 constituted by a fuel cell, a solar battery, and the like, and a plurality of boost DC / DC converter circuits 120a, 120b, 120c (hereinafter referred to as boosted output voltages from the DC power supply 110). , “Converters 120a, 120b, 120c”), PWM (Pulse Width Modulation) signal generation circuit 150 for controlling the boosting operation of each converter 120a, 120b, 120c, and output current of each converter 120a, 120b, 120c is detected. Current detection circuits 160a, 160b, and 160c, and an output voltage detection circuit 170 that detects an output voltage to the load 130.

  The DC power supply B ′ is configured to boost the DC voltage output from the DC power supply 110 to a predetermined voltage by a plurality of converters 120 a, 120 b, 120 c and to supply the voltage to the load 130.

  As shown in FIG. 11, the converter 120a (120b, 120c) includes an inductor L1 (L2, L3), transistors Q1 (Q2, Q3) as semiconductor switch elements, diodes D1 (D2, D3), and capacitors C1 (C2, C2). C3) is a known boost converter circuit. In addition, a field effect transistor, IGBT, etc. can also be used as a semiconductor switch element.

  The boost control of each converter 120a, 120b, 120c is performed by the PWM signal generated by the PWM signal generation circuit 150. As shown in FIG. 10B, the PWM signal generation circuit 150 includes a reference voltage unit 151, a command value signal generation unit 152, an average value calculation unit 154, correction value signal generation units 155a, 155b and 155c, a correction unit 157a, 157b and 157c, and PWM signal generation means 158a, 158b and 158c.

  Each of the correction value signal generation means 155a, 155b, and 155c outputs a correction value signal that is a difference between each output current signal detected by the current detection circuits 160a, 160b, and 160c and the average value signal calculated by the average value calculation means 154. Generate each. The command value signal generation unit 152 generates a command value signal that is the difference between the reference voltage signal output from the reference voltage unit 151 and the output voltage signal detected by the output voltage detection circuit 170. This command value signal is corrected based on each correction value signal in each correction means 157a, 157b, 157c, and input to each PWM signal generation means 158a, 158b, 158c. Each PWM signal generation means 158a, 158b, 158c generates a PWM signal based on the corrected command value signal and outputs it to each converter 120a, 120b, 120c.

  Each converter 120a, 120b, 120c receives the corrected PWM signal generated by each PWM signal generation means 158a, 158b, 158c, thereby adjusting the unbalance of the output current and performing balance control.

Japanese Patent No. 3419443

  However, when DC power supply B 'is applied to a grid-connected inverter system, switching of the inverter circuit affects the output current of each converter 120a, 120b, 120c, and balance control is not performed correctly.

  FIG. 12 shows output currents of the converters 120a, 120b, 120c and correction value signal generation means 155a, 155b, 155c when the DC power supply B ′ is applied to a three-phase full bridge type grid-connected inverter system. It is a figure for demonstrating the relationship with the correction value signal which outputs. In the figure, Ia ', Ib', and Ic 'indicate the output currents of the converters 120a, 120b, and 120c detected by the current detection circuits 160a, 160b, and 160c, respectively. Due to the switching effect of the inverter circuit connected as a load, the waveforms of the output currents Ia ′, Ib ′, and Ic ′ are rectangular waves. In the drawing, the current value of the output current Ia ′ is larger than the current value of the output current Ib ′, and the current value of the output current Ic ′ is smaller than the current value of the output current Ib ′. Sa ′, Sb ′, and Sc ′ represent correction value signals output from the correction value signal generation units 155a, 155b, and 155c, respectively.

  The correction value signals Sa ', Sb', Sc 'are generated based on the current values of the output currents Ia', Ib ', Ic' sampled at predetermined timings t1, t2, t3, .... When the sampling timing overlaps with the timing at which the current values of the output currents Ia ′, Ib ′, and Ic ′ become zero, the correction value signals Sa ′, Sb ′, and Sc ′ are expressed as shown in FIG. It becomes zero. Since the waveforms of the output currents Ia ′, Ib ′, and Ic ′ change depending on the output of the inverter circuit, it is difficult to always match the sampling timing with the timing at which the current value of each output current does not become zero.

  When the correction value signals Sa ′, Sb ′, and Sc ′ become zero, the PWM signals generated by the PWM signal generation units 158a, 158b, and 158c become the same, and the output currents of the converters 120a, 120b, and 120c are unbalanced. No adjustment is made and the unbalanced state continues.

  Further, in the DC power supply device B ′, when a collective smoothing capacitor is arranged at the output end of the DC power supply device B ′ instead of the capacitor C1 (C2, C3) at the output end of each converter 120a, 120b, 120c, Switching of converters 120a, 120b, and 120c affects the output current of each converter 120a, 120b, and 120c. Also in this case, similarly to the above, the output currents of the converters 120a, 120b, and 120c are rectangular waves, and the current value becomes zero depending on the sampling timing, and the output current unbalance is not adjusted.

  In order to reduce the ripple current of the output current of the DC power supply 110, a method of shifting the phase of the PWM signal for controlling each converter 120a, 120b, 120c by 120 ° has been developed.

  In FIG. 13, instead of the capacitor C1 at the output end of each converter 120a, 120b, 120c, a smoothing capacitor (see C0 indicated by the dotted line in FIG. 10A) is arranged at the output end of the DC power supply B ′. When the phase of the PWM signal for controlling each converter 120a, 120b, 120c is shifted by 120 °, the output current of each converter 120a, 120b, 120c and the correction value signal generation means 155a, 155b, 155c are output. It is a figure for demonstrating the relationship with the correction value signal to perform. In the figure, Ia ', Ib', and Ic 'indicate output currents of the converters 120a, 120b, and 120c detected by the current detection circuits 160a, 160b, and 160c, respectively. Due to the switching effect of each converter 120a, 120b, 120c, the waveform of each output current Ia ', Ib', Ic 'is a rectangular wave. Further, the phases of the output currents Ia ′, Ib ′, and Ic ′ are shifted by 120 °. In the figure, the output currents Ia ', Ib', and Ic 'are in a balanced state. Sa ′, Sb ′, and Sc ′ represent correction value signals output from the correction value signal generation units 155a, 155b, and 155c, respectively.

  The correction value signals Sa ', Sb', Sc 'are generated based on the current values of the output currents Ia', Ib ', Ic' sampled at predetermined timings t1, t2, t3, .... At the sampling timing shown in the figure, the current value of the output current Ia 'is zero, and the current values of the output currents Ib' and Ic 'are large. Accordingly, the correction value signal Sa ′ is at a level lower than 0, and the correction value signals Sb ′ and Sc ′ are at a level higher than 0. Thus, the PWM signal corrected to increase the output current is input to converter 120a, and the PWM signal corrected to decrease the output current is input to converters 120b and 120c. That is, although the output currents of the converters 120a, 120b, and 120c are in a balanced state, they are controlled to change the output current.

  The present invention has been conceived under the circumstances described above, and suppresses erroneous detection in detection of imbalance of current flowing in a plurality of DC / DC converter circuits connected in parallel to each other, and DC / DC An object of the present invention is to provide a DC power supply device that is controlled so that the currents flowing through the converter circuit are equal.

  In order to solve the above problems, the present invention takes the following technical means.

The DC power supply device provided by the first aspect of the present invention includes a DC power supply that supplies DC power, a voltage detection circuit that detects an input voltage from the DC power supply, and is connected in parallel to each other and connected to the DC power supply. A plurality of DC / DC converter circuits, a plurality of current detection circuits for detecting currents input to the DC / DC converter circuits, and a reference voltage in which an input voltage detected by the voltage detection circuit is set in advance. And a PWM signal generation circuit that generates a PWM signal for controlling each DC / DC converter circuit so that each input current detected by each current detection circuit is equalized.

  According to this configuration, the current detection circuit detects an input current that is not easily influenced by the DC / DC converter circuit or a connected load. Therefore, erroneous detection in detection of imbalance of current flowing through the DC / DC converter circuit is suppressed. Thereby, the precision of balance control improves.

In a preferred embodiment of the present invention, before Symbol PWM signal generating circuit includes a command value signal generating means for generating a command value signal and a detected voltage signal with a predetermined reference voltage signal by the voltage detecting circuit Average value calculation means for generating an average value signal by calculating an average value from each input current signal detected by each current detection circuit; and a correction value generated from the input current signal and the average value signal Correction means for correcting the command value signal by a signal, and PWM signal generation means for generating a PWM signal from the correction command value signal corrected by the correction means.

  According to this configuration, since the command value signal is corrected by a correction value signal generated from the input current signal and the average value signal, the PWM signal generated based on the corrected command value signal is Each DC / DC converter circuit is controlled so that each input current becomes equal. Thereby, the unbalance of each said input current is suppressed.

In a preferred embodiment of the present invention, the direct current power source includes a solar cell .

In a preferred embodiment of the present invention, the correction value signal is a PI control signal of a deviation signal between the input current signal and the average value signal .

  The grid-connected inverter system provided by the second aspect of the present invention includes any one of the DC power supply devices provided by the first aspect of the present invention and the DC power output from the DC power supply device. And an inverter circuit for converting to

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining an example of a grid-connected inverter system including a first embodiment of a DC power supply device according to the present invention. FIG. 1A is a block diagram showing the basic configuration of the entire grid-connected inverter system. The grid interconnection inverter system A1 includes a DC power supply device B1, an inverter circuit 30, and a commercial power system 40. FIG. 2B is a block diagram showing the basic configuration of the PWM signal generation circuit of the DC power supply device B1.

  The grid-connected inverter system A1 shown in FIG. 1A uses a solar battery as a DC power source, and converts the DC power output from the DC power supply device B1 into AC power by the inverter circuit 30 to commercial power system. 40 is output.

  The inverter circuit 30 is configured by a voltage-controlled self-excited inverter circuit including a bridge circuit including a plurality of switching elements such as a bipolar transistor, a field effect transistor, or a thyristor, and by turning each switching element on and off, DC power input from step-up DC / DC converter circuits 20a, 20b, and 20c described later is converted into AC power. The inverter circuit 30 is provided with a low-pass filter for removing switching noise at the subsequent stage of the bridge circuit, and a sinusoidal AC voltage is output from the low-pass filter to the commercial power system 40. A control block that controls the power conversion operation of the inverter circuit 30 is omitted.

  The direct-current power supply B1 outputs direct-current power. As shown in FIG. 5A, the direct-current power supply 10 that supplies direct-current power and a plurality of boost DC / DCs that boost the output voltage from the direct-current power supply 10 are provided. Converter circuits 20a, 20b, and 20c (hereinafter referred to as "converters 20a, 20b, and 20c"), a PWM signal generation circuit 50 that controls the boost operation of the converters 20a, 20b, and 20c, and inputs to the converters 20a, 20b, and 20c. Current detecting circuits 60a, 60b, 60c for detecting the current to be output, an output voltage detecting circuit 70 for detecting an output voltage to the inverter circuit 30, and a smoothing capacitor 80.

  The DC power supply 10, the converter 20a, the output voltage detection circuit 70, the inverter circuit 30, and the commercial power system 40 are connected in series in this order. Converters 20b and 20c are connected in parallel to converter 20a. A PWM signal generation circuit 50 is connected to each converter 20a, 20b, 20c. Current detection circuits 60a, 60b, and 60c are connected in series to the input sides of converters 20a, 20b, and 20c, respectively. The grid-connected inverter system A1 boosts the DC voltage output from the DC power supply 10 to a predetermined voltage by the converters 20a, 20b, and 20c, and then converts the DC power output from the converters 20a, 20b, and 20c into the inverter circuit 30. Thus, the power is converted into AC power and supplied to the commercial power system 40.

  The DC power supply 10 generates DC power and includes a solar cell that converts sunlight energy into electrical energy.

  Converters 20a, 20b, and 20c are formed of the well-known step-up DC / DC converter circuit shown in FIG. In the converter 20a (20b, 20c), the transistor Q1 (Q2, Q3) is turned on / off by the PWM signal from the PWM signal generation circuit 50. During the on period of the transistor Q1 (Q2, Q3), the power supplied from the DC power supply 10 is accumulated in the inductor L1 (L2, L3). During the off period of the transistor Q1 (Q2, Q3), the power stored in the inductor L1 (L2, L3) is discharged through the diode D1 (D2, D3). Accumulation of power supplied from the DC power supply 10 to the inductor L1 (L2, L3) and discharge of power stored in the inductor L1 (L2, L3) are alternately repeated, so that DC power from the DC power supply 10 is generated. Once stored in the smoothing capacitor 80. A voltage boosted from the smoothing capacitor 80 is supplied to the inverter circuit 30.

  The current detection circuits 60a, 60b, and 60c detect currents input to the converters 20a, 20b, and 20c, respectively, and output the detected input current signals to the PWM signal generation circuit 50. The output voltage detection circuit 70 detects an output voltage output to the inverter circuit 30, and outputs the detected output voltage signal to the PWM signal generation circuit 50. Smoothing capacitor 80 temporarily accumulates the electric power discharged from converters 20 a, 20 b, and 20 c and supplies it to inverter circuit 30.

  The PWM signal generation circuit 50 generates a PWM signal for controlling the on / off operation of the transistor Q1 (Q2, Q3) of the converter 20a (20b, 20c). As shown in FIG. 1B, the PWM signal generation circuit 50 includes a reference voltage means 51, a command value signal generation means 52, an average value calculation means 54, correction value signal generation means 55a, 55b, 55c, correction means 57a, 57b, 57c, and PWM signal generation means 58a, 58b, 58c.

The reference voltage means 51 sets a target value V _C for the output voltage output to the inverter circuit 30. Converters 20a, 20b, and 20c are controlled so that output voltage V _OUT output to inverter circuit 30 becomes this target value V _C.

The command value signal generation means 52 calculates a deviation ΔV (= V _OUT −V _C ) between the output voltage target value Vc set by the reference voltage means 51 and the output voltage V _OUT detected by the output voltage detection circuit 70. Then, 1/3 (= 1 / converter parallel number) is output to each of the correction means 57a, 57b, 57c as a command value signal. A PI control means is provided after the command value signal generation means 52 to calculate a PI control value of the deviation ΔV, and the PI control value is used as a command value signal for each of the correction means 57a, 57b, 57c. You may make it output one by one.

  The average value calculating means 54 calculates the average value of the input current from the input current signal input from each of the current detection circuits 60a, 60b, 60c. That is, assuming that the input currents detected by the current detection circuits 60a, 60b, and 60c are Ia, Ib, and Ic, average values Iave = (Ia + Ib + Ic) / 3 (= (Ia + Ib + Ic) / converter parallel number) are calculated. The average value calculation means 54 generates an average value signal from the calculated average value and outputs it to the correction value signal generation means 55a, 55b, 55c.

  The correction value signal generation means 55a, 55b, and 55c calculate deviations from the input current signals input from the current detection circuits 60a, 60b, and 60c and the average value signal input from the average value calculation means 54, respectively. The correction value signals Sa (= Iave-Ia), Sb (= Iave-Ib), and Sc (= Iave-Ic) are output to the correction means 57a, 57b, and 57c, respectively. A PI control means is provided in the subsequent stage of each correction value signal generation means 55a, 55b, 55c, and a PI control value of a deviation calculated from the input current signal and the average value signal is calculated. You may make it output to each correction means 57a, 57b, 57c as correction value signal Sa, Sb, Sc.

  The correction means 57a, 57b and 57c receive the command value signal 1 / 3ΔV input from the command value signal generation means 52 and the correction value signals Sa, Sb and Sc input from the correction value signal generation means 55a, 55b and 55c, respectively. Are added to generate correction command value signals ΔVa (= 1 / 3ΔV + Sa), ΔVb (= 1 / 3ΔV + Sb), ΔVc (= 1 / 3ΔV + Sc). That is, by adding the deviation between each input current and its average value as a correction value, the common command value signal is corrected to a correction command value signal corresponding to the input current of each converter 20a, 20b, 20c. The correction means 57a, 57b, and 57c output the generated correction command value signals to the PWM signal generation means 58a, 58b, and 58c, respectively.

  The PWM signal generation means 58a, 58b, 58c compares the carrier signal, which is a triangular wave signal generated by a carrier signal generation circuit (not shown), with the correction command value signals input from the correction means 57a, 57b, 57c, respectively. When the correction command value signal ≧ the carrier signal, a high level signal is generated, and when the correction command value signal <the carrier signal, a low level signal is generated. The PWM signal generation means 58a, 58b, 58c corrects the high level signal and the low level signal by a limiter circuit or the like to generate a pulse signal, and outputs it as a PWM signal to each converter 20a, 20b, 20c.

  Each converter 20a, 20b, 20c performs switching of the transistors Q1, Q2, Q3, respectively, according to the input PWM signal. That is, the transistor Q1 (Q2, Q3) is turned on when the PWM signal is at a high level, stores DC power input from the DC power supply 10 in the inductor L1 (L2, L3), and is turned off when the PWM signal is at a low level. The DC power stored in the inductor L1 (L2, L3) is discharged to the smoothing capacitor 80 via the diode D1 (D2, D3).

  For example, when the input currents of the converters 20a, 20b, and 20c are in a state of Ia <Ib <Ic, Ia <Iave {= (Ia + Ib + Ic) / 3}, so that the correction value signal Sa (= Iave−Ia)> 0. Therefore, the correction command value signal ΔVa (= 1 / 3ΔV + Sa) becomes large, and the high level state of the PWM signal becomes long. As a result, the on-time of the transistor Q1 of the converter 20a becomes longer and the flowing current increases. That is, converter 20a is controlled such that Ia increases. Since Ic> Iave, the correction value signal Sc (= Iave−Ic) <0. Therefore, the correction command value signal ΔVc (= 1 / 3ΔV + Sc) becomes small, and the high level state of the PWM signal becomes short. This shortens the on-operation time of transistor Q3 of converter 20c and reduces the flowing current. That is, converter 20c is controlled so that Ic decreases. As described above, each converter 20a, 20b, 20c is controlled such that each input current Ia, Ib, Ic approaches an average value.

  Next, the operation of the DC power supply device B1 will be described.

  Input currents Ia, Ib, and Ic are detected by current detection circuits 60a, 60b, and 60c provided between converters 20a, 20b, and 20c and DC power supply 10, respectively. Therefore, the input currents Ia, Ib, and Ic are obtained by superimposing ripple currents generated by switching of the converters 20a, 20b, and 20c on a constant current. If this ripple current is reduced, each input current Ia, Ib, Ic is detected as a substantially constant current regardless of the sampling timing. Thereby, since each correction value signal Sa, Sb, Sc is correctly calculated, the PWM signal correct | amended correctly is produced | generated. Switching of the converters 20a, 20b, and 20c is controlled by the corrected PWM signal, and the input currents Ia, Ib, and Ic are controlled to be equal.

  FIG. 3 illustrates the relationship between the input current of each converter 20a, 20b, 20c and the correction value signal output from each correction value signal generation means 55a, 55b, 55c in the grid-connected inverter system A1 shown in FIG. It is a figure for doing. In the figure, Ia, Ib, and Ic indicate the input currents of the converters 20a, 20b, and 20c detected by the current detection circuits 60a, 60b, and 60c, respectively. Due to the switching effect of each converter 20a, 20b, 20c, the waveform of each input current Ia, Ib, Ic is a sawtooth wave with a ripple current superimposed thereon. Further, since the phase of the PWM signal for controlling each converter 20a, 20b, 20c is shifted by 120 °, the phase of each input current Ia, Ib, Ic is also shifted by 120 °. In the figure, the input currents Ia, Ib, and Ic are in a balanced state. Sa, Sb, and Sc indicate correction value signals output from the correction value signal generation means 55a, 55b, and 55c, respectively.

  The correction value signals Sa, Sb, Sc are generated based on the current values of the input currents Ia, Ib, Ic sampled at predetermined timings t1, t2, t3,. In the figure, the current values of the sampled input currents Ia, Ib, and Ic are in a relationship of Ia <Ib <Ic due to the influence of the ripple current. However, since the ripple current is reduced and there is no significant difference in the current values of the input currents Ia, Ib, and Ic, the difference from the average value Iave calculated by the average value calculating means 54 is also small. Accordingly, the correction value signals Sa, Sb, Sc output from the correction value signal generation means 55a, 55b, 55c are also constant values close to zero.

  Although the correction value signals Sa, Sb, Sc are not completely zero due to the ripple current, the correction value signals Sa ′, Sb ′, Sc ′ (see FIG. 13) in the conventional DC power supply B ′ Compared to this, it is greatly improved.

  4 and 5 are diagrams for explaining the balance control simulation.

FIG. 4 is a simulation result of balance control in the grid interconnection inverter system A1 shown in FIG. The inductances of the inductors L1, L2, and L3 (see FIG. 2) of the converters 20a, 20b, and 20c are 2.5 mH, 1.5 mH, and 2 so that the currents flowing through the converters 20a, 20b, and 20c are unbalanced. 0.0 mH. Further, the carrier frequency of the PWM signal input to each converter 20a, 20b, 20c and the sampling frequency for calculating the correction value signal were set to 5 kHz. In the figure, V and I are the output voltage and output current of the DC power supply 10. Ia, Ib, and Ic are input currents of the converters 20a, 20b, and 20c, and Ia ′, Ib ′, and Ic ′ are output currents of the converters 20a, 20b, and 20c. Ia _AVE , Ib _AVE , and Ic _AVE are average values of the input current.

  FIG. 5 shows the results of a simulation performed for comparison. In this comparative simulation, the same conditions as in the simulation of FIG. 4 were used except that the current input to the PWM signal generation circuit was not the input current of each converter 20a, 20b, 20c but the output current (conventional method).

Compared with the comparison simulation result shown in FIG. 5, in the simulation result shown in FIG. 4, the difference between the average values Ia _AVE , Ib _AVE , and Ic _AVE of each input current is reduced, and balance control functions correctly. Represents.

  In the first embodiment, the correction value signal is calculated at every predetermined sampling timing. However, the correction value signal may be calculated continuously by analog processing.

  FIG. 6 is a diagram for explaining the relationship between the input current and the correction value signal when the correction value signal is calculated from the input current of each converter 20a, 20b, and 20c by analog processing. As in FIG. 3, Ia, Ib, and Ic in FIG. 6 indicate the input currents of the converters 20a, 20b, and 20c detected by the current detection circuits 60a, 60b, and 60c, respectively. In the figure, the input currents Ia, Ib, and Ic are in a balanced state. Sa, Sb, and Sc indicate correction value signals output from the correction value signal generation means 55a, 55b, and 55c, respectively.

  FIG. 7 is for comparison with FIG. 6, and shows the output current when the correction value signal is calculated by analog processing from the output current of each converter 120a, 120b, 120c of the conventional DC power supply device B ′. It is a figure for demonstrating the relationship with a correction value signal. In FIG. 7, Ia ′, Ib ′, and Ic ′ indicate output currents of the converters 120a, 120b, and 120c detected by the current detection circuits 160a, 160b, and 160c, respectively. In the figure, the output currents Ia ', Ib', and Ic 'are in a balanced state. Sa ′, Sb ′, and Sc ′ represent correction value signals output from the correction value signal generation units 155a, 155b, and 155c, respectively.

  In FIG. 7, the correction value signals Sa ′, Sb ′, and Sc ′ fluctuate drastically even though the output currents Ia ′, Ib ′, and Ic ′ are balanced. On the other hand, in FIG. 6, each of the correction value signals Sa, Sb, Sc is a sawtooth wave due to the influence of the ripple current, but has a stable value close to zero. Thus, the DC power supply device B1 is greatly improved over the conventional DC power supply device B 'even when the correction value signal is continuously calculated by analog processing.

FIG. 8 is a diagram for explaining an example of a grid-connected inverter system including the second embodiment of the DC power supply device according to the present invention. FIG. 4A is a block diagram showing the basic configuration of the entire grid-connected inverter system A2 , and FIG. 4B shows the basic configuration of the PWM signal generation circuit of the DC power supply device B2 provided in the grid-connected inverter system A2. It is a block diagram which shows a structure. In the figure, the same or similar elements as those in the first embodiment are denoted by the same reference numerals. The grid interconnection inverter system A2 is different from the grid interconnection inverter system A1 in that the PWM signal generation circuit 50 is provided with averaging processing means 59a, 59b, 59c for averaging the input current signals. Averaging processing means 59a, 59b, 59c are means for averaging input signals, and for example, a low-pass filter, FIR filter, or means for calculating a moving average is used.

  According to the present embodiment, the input current signals of the converters 20a, 20b, and 20c detected by the current detection circuits 60a, 60b, and 60c are averaged to obtain a signal having a constant current value without ripples, and the correction value. Used for signal calculation. Therefore, the responsiveness of balance control deteriorates in proportion to the time constant of the averaging process, but the accuracy of balance control is further improved.

  The averaging processing means 59a, 59b, 59c may be provided between the correction value signal generation means 55a, 55b, 55c and the correction means 57a, 57b, 57c, respectively. In this case as well, as in the second embodiment, improvement in balance control accuracy can be expected.

FIG. 9 is a diagram for explaining an example of a grid-connected inverter system including the third embodiment of the DC power supply device according to the present invention. FIG. 4A is a block diagram showing the basic configuration of the entire grid-connected inverter system A3 , and FIG. 4B is the basic configuration of the PWM signal generation circuit of the DC power supply device B3 provided in the grid-connected inverter system A3. It is a block diagram which shows a structure. In the figure, the same or similar elements as those in the first embodiment are denoted by the same reference numerals. The grid-connected inverter system A3 includes a current detection circuit 90 provided between the input side connection point P of the converters 20a, 20b, and 20c connected in parallel to the DC power supply 10, and the current detection circuit 90. Is different from the grid-connected inverter system A1 in that the current signal output by is input to the average value calculation means 54 ′.

  The current detection circuit 90 detects the output current of the DC power supply 10 and outputs the detected output current signal to the PWM signal generation circuit 50. The average value calculation means 54 ′ calculates the average value of the input currents input to the converters 20 a, 20 b, 20 c from the output current signal input from the current detection circuit 90. That is, since the sum of the input currents input to the converters 20a, 20b, and 20c is equal to the output current of the DC power supply 10, by dividing the output current of the DC power supply 10 by 3 (= the number of converters in parallel), The average value is calculated. In this embodiment, the same effect as that of the first embodiment can be obtained.

  In the first to third embodiments described above, three converters connected in parallel are used. However, the present invention is not limited to this, and two converters or four or more converters may be used. Moreover, although each converter 20a, 20b, 20c was demonstrated as a step-up chopper system, it is not restricted to this, A step-down chopper system and other systems may be used. Moreover, although the capacitor | condenser was not provided in each converter 20a, 20b, 20c, and the DC power supply device provided with the smoothing capacitor 80 collectively was demonstrated, it is not restricted to this. Instead of the collective smoothing capacitor 80, a capacitor may be provided at the output end of each converter 20a, 20b, 20c.

Further, the case where the PWM signal generation circuit 50 generates the PWM signal using the output voltage V _OUT detected by the output voltage detection circuit 70 has been described. However, when each converter 20a, 20b, 20c controls the input voltage. Needs to be configured to generate a PWM signal using an input voltage.

In the embodiment described above, a case has been described in which dc power supply is used for system interconnection inverter system is not limited thereto. The DC power supply device according to the present invention can be used for other systems, and can perform accurate balance control.

  The DC power supply device and the grid-connected inverter system according to the present invention are not limited to the above-described embodiments. The specific configuration of each part of the DC power supply device and the grid-connected inverter system according to the present invention can be varied in design in various ways.

It is a block diagram for demonstrating an example of the grid connection inverter system provided with 1st Embodiment of the DC power supply device which concerns on this invention. It is a figure which shows the basic circuit structure of the step-up converter circuit in a grid connection inverter system. It is a figure for demonstrating the relationship between the input current of each converter, and the correction value signal which each correction value signal generation means outputs. It is a simulation result of the balance control in the grid connection inverter system shown in FIG. It is the simulation result performed for the comparison. It is a figure for demonstrating the relationship between the input current of each converter, and the correction value signal by which the analog process was carried out. It is a figure for demonstrating the relationship between the output current of each converter, and the correction value signal by which the analog process was carried out. It is a block diagram for demonstrating an example of the grid connection inverter system provided with 2nd Embodiment of the DC power supply device which concerns on this invention. It is a block diagram for demonstrating an example of the grid connection inverter system provided with 3rd Embodiment of the DC power supply device which concerns on this invention. It is a block diagram which shows the basic composition of the conventional DC power supply device. It is a figure which shows the basic circuit structure of the step-up converter circuit in a grid connection inverter system. It is a figure for demonstrating the relationship between the output current of each converter, and the correction value signal which each correction value signal generation means outputs. It is a figure for demonstrating the relationship between the output current of each converter, and the correction value signal which each correction value signal generation means outputs.

Explanation of symbols

A1 to A3 grid-connected inverter system
B1 to B3 DC power supply 10 DC power supply 20a, 20b, 20c Step-up DC / DC converter circuit 30 Inverter circuit 40 Commercial power system 50 PWM signal generation circuit 51 Reference voltage means 52 Command value signal generation means 54, 54 ′ Average value calculation means 55a, 55b, 55c Correction value signal generation means 57a, 57b, 57c Correction means 58a, 58b, 58c PWM signal generation means 59a, 59b, 59c Averaging processing means 60a, 60b, 60c Current detection circuit 70 Output voltage detection circuit 80 Smoothing Capacitor 90 Current detection circuit

Claims (5)

A DC power supply for supplying DC power;
A voltage detection circuit for detecting an input voltage from the DC power supply;
A plurality of DC / DC converter circuits connected in parallel to each other and connected to the DC power supply;
A plurality of current detection circuits for respectively detecting currents input to the DC / DC converter circuit;
Each DC / DC converter circuit is set so that the input voltage detected by the voltage detection circuit becomes a preset reference voltage, and the input currents detected by the current detection circuits are equalized. A PWM signal generation circuit for generating each PWM signal to be controlled;
DC power supply device comprising: Before Symbol PWM signal generating circuit,
Command value signal generating means for generating a command value signal from a voltage signal detected by the voltage detection circuit and a preset reference voltage signal;
Average value calculating means for generating an average value signal by calculating an average value from each input current signal detected by each current detection circuit;
Correction means for correcting the command value signal by a correction value signal generated from the input current signal and the average value signal;
PWM signal generation means for generating a PWM signal from the correction command value signal corrected by the correction means,
The DC power supply device according to claim 1. The DC power supply device according to claim 2, wherein the DC power supply includes a solar battery . The correction value signal is a PI control signal of a deviation signal between the input current signal and the average value signal.
The DC power supply device according to claim 2 or 3 . DC power supply device according to any one of claims 1 to 4,
An inverter circuit for converting DC power output from the DC power supply device into AC power;
A grid-connected inverter system.

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