JP6352864B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device, and more particularly, to a power conversion device including a self-excited converter connected to an AC power system via a transformer.

  In a power converter having a self-excited converter connected to an AC power system via a transformer, if the DC component is included in the voltage of the AC power system or the output voltage of the self-excited converter, the transformer An excitation current containing a direct current component flows through the transformer, and the direct current component of the excitation current biases the transformer.

  In order to avoid biasing the transformer, the self-excited converter operates to generate a voltage that cancels the DC component contained in the voltage of the AC power system or the output voltage of the self-excited converter. On the other hand, when an accident occurs in the AC power system and the self-excited converter is gate-blocked, the residual magnetic flux remains in the transformer when the gate is deblocked thereafter. Superposed to demagnetize the transformer core. When the exciting current increases, the self-excited converter may reach an overcurrent, which may damage the switching elements constituting the converter.

  In Japanese Patent Laid-Open No. 10-171543 (Patent Document 1), by calculating the timing from gate blocking to gate deblocking using a gate timing arithmetic circuit, the transformer is biased when gate deblocking. A technique for preventing magnetism is disclosed.

Japanese Patent Laid-Open No. 10-171543

  According to the technique described in Patent Document 1, gate deblocking is performed at the same voltage phase as the voltage phase when gate blocking is performed. Therefore, depending on the power factor at the timing when the gate is blocked, the phase of the voltage is not always zero at the timing when the gate is deblocked, and there is a possibility of further increasing the amount of magnetic bias of the transformer at the time of gate deblocking. There is. As a result, the iron core of the transformer is greatly demagnetized and the excitation current increases, so that the self-excited converter may become overcurrent.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a gate deblocking in a power conversion device including a power converter connected to an AC power system via a transformer. It is to prevent the amount of magnetic bias of the transformer from increasing.

  The power conversion device according to an aspect of the present invention includes a self-excited converter having an AC output side connected to a three-phase AC power source via a transformer, a DC capacitor connected to a DC input side of the self-excited converter, And a control device for controlling the self-excited converter. The control device includes: a gate block command for gate-blocking the self-excited converter; a command generation unit for generating a gate deblock command for gate-deblocking the self-excited converter; and a primary side current of the transformer. When receiving the gate deblock command from the current detector to be detected and the command generator, the self-excited converter is gated based on the primary current detected by the current detector after the self-excited converter is gate-blocked. And a timing adjusting unit that adjusts the deblocking timing. The timing adjustment unit determines whether or not a DC charging mode for charging the DC capacitor is generated based on the primary side current detected by the current detector after the self-excited converter is gate-blocked. If it is determined that the DC charging mode has occurred, the timing adjustment unit turns the self-excited converter into the gate deblocking when the DC charging mode is stopped after receiving the gate deblocking command. To do.

  According to the present invention, in the power conversion device including the power converter connected to the AC power system via the transformer, it is possible to prevent the amount of magnetic bias of the transformer due to gate deblocking from increasing.

1 is an overall configuration diagram of a power conversion device according to an embodiment of the present invention. It is a circuit diagram which shows the structural example of the self-excited converter shown in FIG. It is a figure for demonstrating direct-current charge mode. It is a block diagram which shows the structure of the control apparatus shown in FIG. It is a wave form diagram for demonstrating adjustment of the timing which performs gate deblocking of a self-excited converter. It is a block diagram which shows the structural example of a timing adjustment part.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

(Configuration of power converter)
FIG. 1 is an overall configuration diagram of a power conversion device according to an embodiment of the present invention. As an example of the power converter according to the present invention, a self-excited reactive power compensator used in a three-phase AC power system will be described. However, the power converter according to the present invention is not limited to the self-excited reactive power compensator as long as it includes a self-excited converter that is electrically connected to a three-phase AC power source via a transformer. .

  Referring to FIG. 1, power conversion device 100 includes a self-excited converter 10, a DC capacitor C <b> 1, and a control device 20.

  Self-excited converter 10 is electrically connected to AC power system 1 having a U phase, a V phase, and a W phase via transformer 2. The self-excited converter 10 includes a self-extinguishing type switching element. Self-excited converter 10 outputs reactive power to AC power system 1 based on the voltage smoothed by DC capacitor C1.

  The transformer 2 transforms the voltage output from the self-excited converter 10 and outputs it to the AC power system 1. The AC power system 1 side of the transformer 2 is the primary side, and the self-excited converter 10 side of the transformer 2 is the secondary side. The U-phase coil, the V-phase coil, and the W-phase coil that form the primary side winding of the transformer 2 are Y-connected. The U-phase coil, the V-phase coil, and the W-phase coil that form the secondary winding of the transformer 2 are Y-connected. The AC power system 1 corresponds to an example of the “three-phase AC power source” in the present invention.

FIG. 2 is a circuit diagram showing a configuration example of the self-excited converter 10 shown in FIG.
2, self-excited converter 10 includes switching elements Q11 to Q22 and diodes D11 to D22. Switching elements Q11 to Q22 are, for example, GTO (Gate Turn Off thyristor), but are not limited to this as long as they are self-extinguishing type switching elements. Diodes D11-D22 are connected in antiparallel to switching elements Q11-Q22, respectively.

  In the case of three phases, six power conversion circuits (for example, one power conversion circuit is configured by Q11, Q12, D11, and D12) are connected in parallel to the DC capacitor C1. Of these, three AC output terminals 11 are connected to one end of each phase secondary winding of the transformer 2, and the remaining three AC output terminals 12 are the other of the phase secondary windings of the transformer 2. Connected to the end. That is, the AC output terminal of the power conversion circuit is connected to both ends of each phase secondary winding, and an AC voltage is output to the secondary winding by the two power conversion circuits.

  A gate drive signal (gate pulse signal GP) is supplied from the control device 20 to the switching elements Q11 to Q22. Switching elements Q11-Q22 perform a switching operation in accordance with gate pulse signal GP, thereby converting the voltage smoothed by DC capacitor C1, that is, a DC voltage, into an AC voltage and supplying it to AC power system 1. Note that the output phase voltage of the self-excited converter 10 of FIG. 2 is two levels.

  Referring to FIG. 1 again, voltage detector 16 detects the voltage (system voltage) of AC power system 1. The system voltage includes a U-phase voltage VGU, a V-phase voltage VGV, and a W-phase voltage VGW. The system voltage detected by the voltage detector 16 is given to the control device 20.

  The current detector 18 detects the primary current of the transformer 2. The primary side current includes a U-phase current IU, a V-phase current IV, and a W-phase current IW. The primary side current detected by the current detector 18 is given to the control device 20.

  The voltage detector 14 detects the voltage Vdc between the terminals of the DC capacitor C1. The inter-terminal voltage Vdc of the DC capacitor C1 detected by the voltage detector 14 is given to the control device 20.

  Based on the voltages VGU, VGV, VGW detected by the voltage detector 16, the currents IU, IV, IW detected by the current detector 18, and the voltage Vdc detected by the voltage detector 14, the control device 20 The power output from the self-excited converter 10 to the AC power system 1 is controlled by controlling the switching element (FIG. 2) of the self-excited converter 10.

  Control device 20 further receives a gate block command (GB command) and a gate deblock command (DEB command) issued from a host device (not shown). The gate block command is a command for stopping (all off) the switching operation of all the switching elements constituting the self-excited converter 10. The gate block command is issued, for example, when an abnormality occurs in the AC power system 1. Control device 20 outputs gate block signal GB to self-excited converter 10 in response to the gate block command. The switching elements Q11 to Q22 are fixed in the OFF state upon receiving the gate block signal GB, so that the self-excited converter 10 is stopped (gate block state).

  On the other hand, the gate deblock command is a command for switching the switching element of the self-excited converter 10 in the gate block state again. The gate deblocking command is issued when the abnormality of the AC power system 1 is resolved after the self-excited converter 10 is gate-blocked. Control device 20 outputs gate deblock signal DEB to self-excited converter 10 in response to the gate deblock command. When the switching elements Q11 to Q22 start the switching operation again in response to the gate deblocking signal DEB, the self-excited converter 10 resumes the AC output synchronized with the voltage of the AC power system 1.

  Here, when the gate block of the self-excited converter 10 is performed, the transformer 2 may be demagnetized due to the residual magnetic flux in the gate block. When magnetism occurs in the transformer 2 in a state where the self-excited converter 10 is gate-blocked, in the transformer 2, the magnitude of excitation impedance is generated between three-phase coils (U-phase coil, V-phase coil, W-phase coil). . As a result, the voltage sharing among the three-phase coils can be biased, and a mode in which the DC capacitor C1 is charged via the self-excited converter 10 in a phase where a relatively high voltage is applied (hereinafter referred to as “DC charging mode”). May also occur).

  FIG. 3 is a diagram for explaining the DC charging mode. In FIG. 3, it is assumed that the U-phase coil has a larger amount of magnetization than the V-phase coil and the W-phase coil as one aspect of the magnetization of the transformer 2.

  In this case, the excitation impedance of the U-phase coil is smaller than the excitation impedance of the V-phase coil and the W-phase coil. Therefore, as the voltage sharing of the U-phase to W-phase voltage on the transformer primary side, the voltage applied to the W-phase coil having a large excitation impedance is higher than the voltage applied to the U-phase coil having a small excitation impedance. Get higher.

  When the W-phase secondary voltage exceeds the voltage Vdc of the DC capacitor C1 due to an increase in the voltage applied to the W-phase coil, as shown in FIG. A current path is formed through the antiparallel diode of the self-excited converter 10 to the DC capacitor C1. In this way, during the period in which the W-phase secondary voltage exceeds the voltage Vdc of the DC capacitor C1, the DC charging mode is established and the DC capacitor C1 is charged.

  When the gate deblocking of the self-excited converter 10 is performed during the DC charging mode, the voltage for exciting the W-phase coil of the transformer 2 is further increased by the voltage output from the self-excited converter 10. As a result, the amount of magnetization of the transformer 2 at the timing when the gate deblocking is further increased, and as a result, the self-excited converter 10 stops protection due to an increase in the excitation current leading to an overcurrent. become. In the worst case, the elements constituting the self-excited converter 10 may be destroyed.

  As described above, in a state where the self-excited converter 10 is gate-blocked, the DC charging mode can occur when the phase having the largest amount of bias between the three phases of the transformer 2 is excited. Then, there is a possibility that the amount of magnetic bias of the transformer 2 is further increased by gate-deblocking the self-excited converter 10 during the generation of the DC charging mode.

  Therefore, if the gate deblocking of the self-excited converter 10 can be executed at the timing when the DC charging mode does not occur, in other words, the timing at which the amount of magnetic bias of the transformer 2 becomes small, the transformer 2 can be driven by the gate deblocking. It is possible to prevent the amount of magnetic demagnetization from increasing.

  Therefore, in the power conversion device according to the present embodiment, it is determined based on the primary current of transformer 2 detected by current detector 18 whether or not DC charging mode is occurring in transformer 2. When it is determined that the DC charging mode is generated in the transformer 2, the self-excited converter 10 is gated when the DC charging mode is stopped after receiving the gate deblocking command. Deblock.

Hereinafter, the control configuration of the power conversion device according to the present embodiment will be described.
(Control configuration of power converter)
FIG. 4 is a block diagram showing a configuration of the control device 20 shown in FIG.

  Referring to FIG. 4, control device 20 includes a voltage command generation unit 22, a gate pulse generation unit 24, a GB / DEB command unit 28, and a timing adjustment unit 30.

  The voltage command generator 22 includes the system voltages VGU, VGV, VGW detected by the voltage detector 16, the primary currents IU, IV, IW detected by the current detector 18, and the voltage Vdc detected by the voltage detector 14. Based on the DC voltage command value Vdc *, output voltage command values Vu *, Vv *, and Vw * that are voltages output from the self-excited converter 10 are calculated.

  The gate pulse generator 24 generates a gate pulse signal GP for the self-excited converter 10 to output a voltage corresponding to the output voltage command values Vu *, Vv *, and Vw * by, for example, PWM (Pulse Width Modulation) control. To do. The gate pulse generation unit 24 outputs the generated gate pulse signal GP to the switching elements Q11 to Q22 (FIG. 2) constituting the self-excited converter 10.

  The GB / DEB command unit 28 receives a gate block command and a gate deblock command from a host device (not shown). The GB / DEB command unit 28 outputs a gate block signal GB to the self-excited converter 10 in response to the gate block command. By receiving gate block signal GB and switching elements Q11-Q22 being fixed in the off state, self-excited converter 10 enters the gate block state.

  The GB / DEB command unit 28 further generates a gate deblock signal DEB in response to the gate deblock command and outputs it to the timing adjustment unit 30.

  The timing adjustment unit 30 gate-deblocks the self-excited converter 10 based on the primary currents IU, IV, and IW of the transformer 2 detected by the current detector 18 after the self-excited converter 10 is gate-blocked. Adjust timing.

  Hereinafter, a detailed configuration of the timing adjustment unit 30 will be described with reference to FIGS. 4 and 5.

(Adjustment of gate deblock timing)
FIG. 5 is a waveform diagram for explaining the adjustment of the timing of gate deblocking of the self-excited converter 10. In FIG. 5, it is assumed that the gate block of self-excited converter 10 is performed before time t0.

  When the gate block of the self-excited converter 10 is performed, the timing adjustment unit 30 obtains the absolute values | IU |, | IV |, | IW | of the primary side currents IU, IV, IW detected by the current detector 18. to add. In the following description, the total value of the absolute values | IU |, | IV |, | IW | of the primary side current is also simply referred to as “primary side current total value”. FIG. 5 shows temporal changes in the primary-side current total value after time t0.

  As shown in FIG. 5, a temporary increase in the current value appears in the primary side current total value. This increase in current value is due to the bias of the transformer 2, and the DC charging mode (FIG. 3) is generated by exciting the phase with the largest amount of bias between the three phases of the transformer 2. It shows that. As described in FIG. 3, during the generation of the DC charging mode, a current flows from any phase of the transformer 2 toward the DC capacitor C <b> 1 via the antiparallel diode of the self-excited converter 10. Therefore, the current value of any of the primary side currents IU, IV, IW of the transformer 2 increases according to the magnitude of the amount of magnetization between the three phases, and as a result, the primary side current total value also increases.

  When receiving the gate deblocking command at time t1 after time t0, the timing adjustment unit 30 compares the primary current total value with a preset threshold value Ith. When the primary side current value exceeds the threshold value Ith, the timing adjustment unit 30 determines that the DC charging mode has occurred.

  When it is determined that the DC charging mode is occurring, the timing adjustment unit 30 waits for the DC charging mode to stop and executes gate deblocking of the self-excited converter 10. Specifically, when it is determined that the primary-side current total value exceeds the threshold value Ith at time t2, the timing adjustment unit 30 detects the timing at which the primary-side current total value has decreased again to the threshold value Ith. When it is determined that the primary side total current value has decreased to the threshold value Ith at time t3 after time t2, the timing adjustment unit 30 is time t4 when the predetermined time Tb [second] has elapsed from time t3. Then, the gate deblocking of the self-excited converter 10 is executed.

  Here, the predetermined time Tb [seconds] is set to a time required for the primary side current total value to be sufficiently smaller than the threshold value Ith after the primary side current total value is decreased to the threshold value Ith. The predetermined time Tb [seconds] is longer than the time interval from when the primary-side current total value exceeds the threshold value Ith after the self-excited converter 10 is gate-blocked until the next primary-side current total value exceeds the threshold value Ith. It is set to be shorter. With such a configuration, the gate deblocking of the self-excited converter 10 can be performed in a state where the DC charging mode is stopped, so that the amount of magnetic bias of the transformer 2 increases with the gate deblocking. Never do.

  Since gate deblocking is performed at time t4, self-excited converter 10 resumes AC output synchronized with the voltage of AC power system 1 after time t4. After gate deblocking, the transformer 2 is excited with the output voltage of the self-excited converter 10. The control device 20 corrects the output voltage command values Vu *, Vv *, and Vw * so as to reduce the amount of magnetic bias, so that the primary side current total value is less than the threshold value Ith as indicated by the solid line k1 in the figure. Is suppressed.

  Note that, as indicated by a broken line k2 in the figure, there may occur a case where the primary-side current total value does not decrease below the threshold value Ith again after it is determined that the primary-side current total value exceeds the threshold value Ith at time t2. is there. In this case, the timing adjustment unit 30 performs gate deblocking of the self-excited converter 10 at time t5, which is the timing when the predetermined time Ta [seconds] has elapsed from time t1. After the gate deblocking, the transformer 2 is excited by the output voltage of the self-excited converter 10, but if the amount of magnetic bias of the transformer 2 is not reduced, the self-excited converter 10 may be gate-blocked again. There is.

  Although illustration is omitted, if the state where the primary side current total value is equal to or lower than the threshold value Ith is continued after time t1, the timing adjustment unit 30 indicates that the transformer 2 is not demagnetized. As a result, gate deblocking of the self-excited converter 10 is executed at time t5, which is the timing when the predetermined time Ta [second] has elapsed from time t1.

(Configuration example of timing adjustment unit)
Next, a configuration example of the timing adjustment unit 30 for realizing the adjustment of the gate deblock timing shown in FIG. 5 will be described with reference to FIG.

  Referring to FIG. 6, timing adjustment unit 30 includes absolute value calculation units 40U, 40V, and 40W, an adder 42, a comparator 44, logical product (AND) circuits 46, 50, and 68, and a reset priority type. SR flip-flops 48, 54, 62, inverting (NOT) circuits 52, 66, a logical sum (OR) circuit 58, a minimum ON circuit 60, and on-delay circuits 56, 64.

  The absolute value calculator 40U calculates the absolute value | IU | of the U-phase primary current IU detected by the current detector 18 (FIGS. 1 and 4). The absolute value calculator 40V calculates the absolute value | IV | of the V-phase primary side current IV detected by the current detector 18. The absolute value calculator 40W calculates the absolute value | IW | of the W-phase primary side current IW detected by the current detector 18.

  The adder 42 calculates the primary current total value by adding the absolute values | IU |, | IV |, | IW | of the primary currents of the respective phases.

  In the comparator 44, the primary side total current value is input to the non-inverting input terminal (+ terminal), and the threshold value Ith is input to the inverting input terminal (− terminal). When the primary side total current value is larger than the threshold value Ith, the comparator 44 outputs an H (logic high) level signal. When the primary side total current value is equal to or less than the threshold value Ith, the comparator 44 outputs an L (logic low) level signal. The output signal of the comparator 44 is given to one input of the AND circuit 46. The output signal of the comparator 44 is further supplied to the inverting circuit 52. The inverting circuit 52 outputs an inverted signal of the output signal from the comparator 44. The output signal of the inverting circuit 52 (the inverted signal of the output of the comparator 44) is given to one input of the AND circuit 50.

  The SR flip-flop 62 receives a gate deblock command from the GB / DEB command unit 28 (FIG. 4) at the set terminal (S), and a gate deblock signal DEB output from the minimum ON circuit 60 at the reset terminal (R). Receive. The gate deblock signal DEB is a signal supplied from the timing adjustment unit 30 to the self-excited converter 10. The SR flip-flop 62 outputs an H level signal from the output terminal when the gate deblock command is at the activation level of H level, and outputs an L level signal from the output terminal when the gate deblock signal DEB is at the H level. To do. Since the SR flip-flop 62 is a reset priority type, when the gate deblocking command and the gate deblocking signal DEB are both at the H level, an L level signal is output from the output terminal. The output of the SR flip-flop 62 is input to the other input of the AND circuit 46 and to the on-delay circuit 64.

  When the output signal of the SR flip-flop 62 changes from L level to H level, the on-delay circuit 64 outputs a signal obtained by delaying the change by a predetermined time Ta [second]. The output signal of the on-delay circuit 64 is input to one input of the AND circuit 68.

  The logical product circuit 46 calculates the logical product of the output signal of the comparator 44 and the output signal of the SR flip-flop 62. The SR flip-flop 48 receives the output signal of the AND circuit 46 at the set terminal (S) and the gate deblock signal DEB at the reset terminal (R). The SR flip-flop 48 outputs an H level signal from the output terminal when the output signal of the comparator 44 is at the H level, and outputs an L level signal from the output terminal when the gate deblock signal DEB is at the H level. Since the SR flip-flop 48 is a reset priority type, when the output signal of the AND circuit 46 and the gate deblock signal DEB are both at the H level, an L level signal is output from the output terminal. The output of the SR flip-flop 48 is input to the other input of the AND circuit 50.

  The logical product circuit 50 calculates the logical product of the output signal of the inverting circuit 52 (the inverted signal of the output of the comparator 44) and the output signal of the SR flip-flop 48. The SR flip-flop 54 receives the output signal of the AND circuit 50 at the set terminal (S) and the gate deblock signal DEB at the reset terminal (R). The SR flip-flop 54 outputs an H level signal from the output terminal when the output signal of the AND circuit 50 is at the H level, and outputs an L level signal from the output terminal when the gate deblock signal DEB is at the H level. . Since the SR flip-flop 54 is a reset priority type, when the output signal of the AND circuit 50 and the gate deblock signal DEB are both at the H level, an L level signal is output from the output terminal. The output of the SR flip-flop 48 is input to the on-delay circuit 56 and the inverting circuit 66.

  The inverting circuit 66 outputs an inverted signal of the output signal of the SR flip-flop 54. The output signal of inverting circuit 66 (the inverted signal of the output of SR flip-flop 54) is applied to the other input of AND circuit 68.

  The logical product circuit 68 calculates the logical product of the output signal of the on-delay circuit 64 and the output signal of the inverting circuit 66. The output signal of the logical product circuit 68 is given to one input of the logical sum circuit 58.

  When the output signal of the SR flip-flop 54 changes from the L level to the H level, the on-delay circuit 56 outputs a signal obtained by delaying the change by a predetermined time Tb [second]. The output signal of the on-delay circuit 56 is given to the other input of the OR circuit 58.

  The logical sum circuit 58 calculates the logical sum of the output signal of the logical product circuit 68 and the output signal of the on-delay circuit 56. The output signal of the OR circuit 58 is input to the minimum ON circuit 60.

  The minimum ON circuit 60 is a circuit for continuously setting the output signal of the OR circuit 58 to the H level over a preset minimum ON time. The minimum ON circuit 60 outputs the output signal of the OR circuit 58 to the self-excited converter 10 as the gate deblock signal DEB. When the gate deblocking signal DEB is activated from the L level to the H level, the gate deblocking of the self-excited converter 10 is executed.

  In the timing adjustment unit 30 having the above configuration, first, when an L level gate deblock command is given from the GB / DEB command unit 28, a gate deblock signal DEB deactivated to the L level is generated. To the self-excited converter 10.

  Next, when a gate deblocking command activated to H level is given from the GB / DEB command unit 28, the gate deblocking signal DEB is activated from L level to H level based on the output signal of the comparator 44. Is done. Specifically, at the timing when the output signal of the comparator 44 is switched from the L level to the H level, that is, the timing when the primary side current total value exceeds the threshold value Ith, the output signal of the SR flip-flop 54 is at the L level. In addition, since the output signal of the on-delay circuit 64 is L level, the output signal of the OR circuit 58 becomes L level. As a result, the gate deblock signal DEB remains at the L level.

  When the primary side current total value decreases again to the threshold value Ith after the timing when the primary side current total value exceeds the threshold value Ith, the output signal of the comparator 44 is switched from the H level to the L level. As a result, the output signal of the SR flip-flop 54 is switched from the L level to the H level. The on-delay circuit 56 delays the H-level output signal from the SR flip-flop 54 by a predetermined time Tb [second] and outputs the delayed signal to the OR circuit 58. As a result, the gate deblock signal DEB is activated from the L level to the H level at a timing when a predetermined time Tb [second] has elapsed from the timing when the primary side total current value has decreased to the threshold value Ith. Thereby, the gate deblocking of the self-excited converter 10 is performed.

  On the other hand, if the primary side current total value does not drop below the threshold value Ith after the timing when the primary side current total value exceeds the threshold value Ith, the output signal of the SR flip-flop 54 remains at the L level. . In this case, when the predetermined time Ta [seconds] has elapsed from the timing when the gate deblocking command is activated to the H level, the on-delay circuit 64 outputs an H level signal, so that the gate deblocking signal DEB becomes L Activated from level to H level.

  Further, even when the state where the primary side current total value is equal to or lower than the threshold value Ith continues, the output signal of the SR flip-flop 54 remains at the L level. Therefore, when the predetermined time Ta [seconds] has elapsed from the timing when the gate deblocking command is activated to the H level, the on-delay circuit 64 outputs an H level signal, so that the gate deblocking signal DEB is at the L level. To H level.

  As described above, according to the power conversion device according to the present embodiment, whether or not the DC charging mode is generated in transformer 2 is determined based on the primary current of transformer 2 detected by current detector 18. Thus, it can be determined whether or not the amount of magnetic bias of the transformer 2 is large. As a result, when it is determined that the DC charging mode is occurring in the transformer 2, the DC charging mode is stopped after receiving the gate deblocking command, that is, the transformer 2 is biased. The gate deblocking of the self-excited converter 10 can be executed at the timing when the magnetic quantity becomes small. As a result, it is possible to prevent the amount of magnetic bias of the transformer 2 from increasing due to gate deblocking.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 AC power system, 2 transformer, 10 self-excited converter, 11, 12 AC output terminal, 14, 16 voltage detector, 18 current detector, 20 controller, 22 voltage command generator, 24 gate pulse generator, 28 GB / DEB command section, 30 timing adjustment section, 40 U, 40 V, 40 W absolute value calculation section, 42 adder, 44 comparator, 46, 50, 68 logical product circuit, 48, 54, 62 SR flip-flop, 52, 66 Inversion circuit, 56, 64 On-delay circuit, 58 OR circuit, 60 Minimum ON circuit, 100 Power converter, Q11 to Q22 switching element, D11 to D22 diode, C1 DC capacitor.

Claims (3)

A self-excited converter whose AC output side is connected to a three-phase AC power source via a transformer;
A DC capacitor connected to the DC input side of the self-excited converter;
A control device for controlling the self-excited converter,
The controller is
A command generation unit for generating a gate block command for gate-blocking the self-excited converter, and a gate deblocking command for gate-deblocking the self-excited converter;
A current detector for detecting a primary side current of the transformer;
When receiving the gate deblocking command from the command generator, the self-excited converter is gated based on the primary current detected by the current detector after the self-excited converter is gate-blocked. And a timing adjustment unit that adjusts the timing to block,
The timing adjustment unit
Based on the primary current detected by the current detector after gate blocking the self-excited converter, determining whether a DC charging mode for charging the DC capacitor has occurred, and
When it is determined that the DC charging mode is occurring, the self-excited converter is gate-deblocked when the DC charging mode is stopped after receiving the gate deblocking command. , Power conversion device. The timing adjustment unit
A calculation unit for calculating a total value of absolute values of respective phase currents of the primary current detected by the current detector;
When the total value exceeds a threshold value after the self-excited converter is gate-blocked, it is determined that the DC charging mode has occurred, and again after the total value exceeds the threshold value, the threshold value again falls below the threshold value. The power converter of Claim 1 containing the execution part comprised so that the said self-excited converter may be gate-deblocked in the state which has fallen to the point. The execution unit is configured to gate deblock the self-excited converter when a predetermined time elapses from the time when the total value decreases to the threshold again after the total value exceeds the threshold. ,
The predetermined time is set to be shorter than a time interval from when the total value exceeds the threshold after the self-excited converter is gate-blocked to when the total value exceeds the threshold. Item 3. The power conversion device according to Item 2.

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