JP2013191670A - Semiconductor light-emitting element and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element that allows preventing a leakage current flowing into threading dislocations through pits due to crystal defects of a semiconductor layer located at the outermost surface of a semiconductor structure layer, and to provide a method of manufacturing the same.SOLUTION: A method of manufacturing a semiconductor light-emitting element includes: a growth step of stacking a first semiconductor layer having a first conductivity type, an active layer, a second semiconductor layer having a second conductivity type, and a third semiconductor layer having the second conductivity type on a growth substrate in this order to form a semiconductor structure layer; a wet etching step of performing wet etching for selectively etching the third semiconductor layer and forming bottom surfaces of pits at the interface between the third semiconductor layer and the second semiconductor layer by extending the pits due to crystal defects of the third semiconductor layer; and a filling step of filling an insulating material in the pits extended by the wet etching step.

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  In the manufacture of a semiconductor light emitting device, in general, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer, which are semiconductor crystal layers, are sequentially stacked on a growth substrate such as sapphire using a MOCVD (metal organic chemical vapor deposition) method. Thus, an epitaxial layer as a semiconductor structure layer is formed. After the formation of the epitaxial layer, an electrode layer is formed on the P semiconductor layer by, for example, a vacuum deposition method.

  In forming the epitaxial layer, the outermost p-type semiconductor layer has poor crystallinity because the temperature at the time of crystal growth is lower than, for example, 900 ° C. compared to the other crystal layers, and therefore the p-type semiconductor layer It is known that a pit having a V-shaped cross section appears. These pits are generated starting from crystal defects. A crystal defect is a threading dislocation caused by a difference in lattice constant (lattice misfit) between a growth substrate and a semiconductor layer. The threading dislocation occurs in the crystal layer on the growth substrate side from the p-type semiconductor layer, and the tip of the pit is directly connected to the threading dislocation. When the electrode layer is formed on the surface where many pits are exposed as described above, there is a problem in that the electrode material enters the pits and causes defects in the semiconductor light emitting device itself such as leakage or short circuit. .

  Therefore, conventionally, a manufacturing method has been proposed in which an insulating material is filled in the pits of the p-type semiconductor layer and the electrode material is prevented from entering the pits during the subsequent formation of the electrode layer (see Patent Document 1).

JP 2007-88404 A

  However, as in Patent Document 1, even if an insulating material is filled in the pits of the semiconductor layer on the outermost surface of the semiconductor structure layer formed on the growth substrate, the leakage current to the threading dislocations directly connected to the pits is completely eliminated. Cannot be eliminated and some leakage current is generated.

  Accordingly, an object of the present invention is made in view of such a point, and it is possible to prevent a leakage current flowing through threading dislocations through pits based on crystal defects of a semiconductor layer located on the outermost surface of the semiconductor structure layer. It is to provide a semiconductor light emitting device and a method for manufacturing the same.

  According to the method for manufacturing a semiconductor light emitting device of the present invention, a first semiconductor layer having a first conductivity type, an active layer, a second semiconductor layer having a second conductivity type, and the second conductivity type are formed on a growth substrate. A third step of stacking the third semiconductor layers in that order to form a semiconductor structure layer, and wet etching for selectively etching the third semiconductor layer, and based on crystal defects in the third semiconductor layer A wet etching step of extending a pit to form a bottom surface of the pit at the interface between the third semiconductor layer and the second semiconductor layer, and filling the pit expanded in the wet etching step with an insulating material And a filling step.

  The semiconductor light emitting device of the present invention includes a first semiconductor layer having a first conductivity type, an active layer, a second semiconductor layer having a second conductivity type, and a third semiconductor layer having the second conductivity type. Is a semiconductor light emitting device having a semiconductor structure layer stacked in that order, wherein a pit having a bottom surface is formed at the interface with the second semiconductor layer in the third semiconductor layer, and an insulating material is filled in the pit It is characterized by being.

  According to the method for manufacturing a semiconductor light emitting device of the present invention, since the pits based on the crystal defects of the third semiconductor layer are expanded by the wet etching process, a bottom surface is formed at the boundary between the pits and the second semiconductor layer. The surface of the second semiconductor layer is located between the inner wall surface and the threading dislocation. Therefore, in the second semiconductor layer, the resistance is large in the direction perpendicular to the stacking direction, and almost no current flows. Therefore, the leakage current flows through the inner wall surface of the pit and the threading dislocation due to the existence of the bottom surface with the large resistance. It is prevented. In addition, since the expanded pit is filled with an insulating material, the electrode material and the electrode pad are prevented from entering the pit when the electrode layer and the electrode pad are formed on the third semiconductor layer thereafter, and the semiconductor light emission Causes of defects such as leaks and shorts in the element itself can be eliminated.

  According to the semiconductor light emitting device of the present invention, a pit having a bottom surface is formed at the interface with the second semiconductor layer in the third semiconductor layer, and the second semiconductor is interposed between the inner wall surface of the pit and the threading dislocation. Since the surface of the layer is located and the insulating material is filled in the pit, leakage current is prevented from flowing through the inner wall surface of the pit and the threading dislocation, and the semiconductor light emitting device itself is leaked or shorted. Such a cause of failure can be eliminated.

It is sectional drawing which shows the manufacturing method of Example 1 of this invention. It is a figure which shows the position of the threading dislocation with respect to the pit by the presence or absence of a wet etching process. It is sectional drawing which shows the manufacturing method of Example 2 of this invention. FIG. 4 is a cross-sectional view showing a continued portion of the manufacturing method of FIG. 3.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  1A to 1H show a manufacturing method of a face-up type nitride semiconductor light emitting device as Example 1 of the present invention. The manufacturing method of Example 1 corresponds to the reference numerals (a) to (h) in FIG. 1, and (a) an epitaxial layer growth step, (b) a wet etching step, (c) an insulating material application step, (d ) Insulating material polishing step, (e) dry etching step, (f) p-type electrode formation step, (g) n-type electrode formation step, and (h) p-electrode pad formation step, which are executed in that order .

  In the epitaxial layer growth step, a growth substrate 11 made of sapphire is prepared, and an epitaxial layer made of a nitride-based semiconductor is formed on the growth substrate 11 using MOCVD. From the growth substrate 11 side, the epitaxial layer is formed from the low temperature buffer layer 12, the undoped GaN layer 13, the n-type GaN layer 14 (first semiconductor layer), the InGaN / GaN layer 15 (active layer), and the p-type AlInGaN layer 16 (first layer). 2 semiconductor layer) and a p-type GaN layer 17 (third semiconductor layer) are stacked in that order.

As a specific method of forming the epitaxial layer, first, the growth substrate 11 is carried into a MOCVD apparatus and subjected to a heat treatment for about 10 minutes in a hydrogen atmosphere at 1000 ° C. Subsequently, the ambient temperature is adjusted to about 500 ° C., and TMG (trimethyl gallium) (flow rate: 10.4 μmol / min) and NH ₃ (flow rate: 3.3 LM) are supplied for about 3 minutes. It is formed. Thereafter, the ambient temperature is raised to about 1000 ° C., and this state is maintained for about 30 seconds, whereby the low-temperature buffer layer 12 is crystallized. Subsequently, TMG (flow rate: 45 μmol / min) and NH ₃ (flow rate: 4.4 LM) are supplied for about 20 minutes while the ambient temperature is maintained at about 1000 ° C., so that the film thickness is about 1 μm. A base GaN layer 13 is formed. Next, when the ambient temperature is about 1000 ° C., TMG (flow rate: 45 μmol / min), NH ₃ (flow rate: 4.4 LM) and SiH ₄ (flow rate: 2.7 × 10 ⁻⁹ mol / min) as the dopant gas are about By supplying for 100 minutes, the n-type GaN layer 14 having a film thickness of about 5 μm is formed.

Subsequently, an InGaN / GaN layer 15 having a multiple quantum well structure as an active layer is formed on the n-type GaN layer 14. The InGaN / GaN layer 15 is grown for 5 periods with InGaN / GaN as one period. Specifically, TMG (flow rate: 3.6 μmol / min), TMI (trimethylindium) (flow rate: 10 μmol / min), and NH ₃ (flow rate 4.4 LM) are supplied for about 33 seconds in an ambient temperature of about 700 ° C. As a result, an InGaN well layer having a thickness of about 2.2 nm is formed. Subsequently, TMG (flow rate: 3.6 μmol / min) and NH ₃ (flow rate: 4.4LM) are supplied for about 320 seconds, thereby forming a GaN barrier layer having a thickness of about 15 nm. By repeating this process for five cycles, the InGaN / GaN layer 15 is formed.

Next, the ambient temperature was raised to about 800 ° C., TMG (flow rate: 8.1 μmol / min), TMA (trimethylaluminum) (flow rate: 7.5 μmol / min), NH ₃ (flow rate: 4.4 LM) and Cp as a dopant. ₂ By supplying Mg (bis-cyclopentadienyl Mg) (flow rate: 2.9 × 10 ⁻⁷ μmol / min) for about 5 minutes, a p-type AlInGaN layer 16 (cladding layer) having a thickness of about 40 nm is supplied. ) Is formed. Subsequently, while maintaining the ambient temperature at about 800 ° C., TMG (flow rate: 18 μmol / min), NH ₃ (flow rate: 4.4 LM) and Cp ₂ Mg as a dopant (flow rate: 2.9 × 10 ⁻⁷ μmol / min) min) is supplied for about 7 minutes to form a p-type GaN layer 17 having a thickness of about 150 nm.

  It is assumed that a plurality of pits 20 having a V-shaped cross section are generated in the p-type GaN layer 17 based on crystal defects in the epitaxial layer growth step as shown in FIG.

  In the wet etching process, the growth substrate 11 on which the epitaxial layer is formed is immersed in an etching solution (not shown). By this wet etching, the pits 20 are expanded in a direction (lateral direction) perpendicular to the stacking direction as shown in FIG. As an etching solution, an alkaline aqueous solution such as KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide) is used. When the etching solution is TMAH, for example, the concentration of the aqueous solution is 5 to 50%, and the temperature is 50 to 100 ° C. Although the C + plane (the surface of the p-type GaN layer 17) is chemically stable, it is not etched, but the etching solution penetrates into the inner wall surface of the pit 20 on the C− plane, and etching occurs from the inner wall surface of the pit 20. The upper part of the threading dislocation directly connected to the pit 20 is very small in size as compared to the pit 20, so that the etching solution is difficult to penetrate. Further, the AlInGaN layer 16 located adjacent to the p-type GaN layer 17 contains an Al component, and therefore is less likely to be etched than the p-type GaN layer 17. For this reason, the inner wall surface of the pit 20 is etched, but the AlInGaN layer 16 and the threading dislocations below it are hardly etched. Therefore, the bottom surface 20a of the pit 20 is formed flat at the interface between the p-type GaN layer 17 and the p-type AlInGaN layer 16 (that is, the boundary between threading dislocations and the pit 20).

When it is desired to promote this etching, a PEC (photoelectrochemical) etching method can be used. When the p-type GaN layer 17 is etched with an aqueous KOH solution using the PEC etching method, UV (Ultra Violet) light (ultraviolet light) shorter than the wavelength (365 nm) corresponding to the band gap of GaN is irradiated. As a result, electron-hole pairs are generated in the p-type GaN layer 17, electrons are extracted by bias application, and the remaining holes move to the inner wall surface side of the pit 20 of the p-type GaN layer 17. Then, the inner wall surface of the pit 20 is etched while repeating the oxidation and dissolution of the inner wall surface of the GaN by the reaction with the OH ⁻ ions of the KOH aqueous solution.

  As the size of the bottom surface 20a of the pit 20, a resistance value that does not cause a leakage current described later is obtained in a direction perpendicular to the stacking direction of the p-type semiconductor layer (from the inner wall surface of the pit 20 to the threading dislocation). It must be large enough.

  In the insulating material application step, an insulating material is applied on the p-type GaN layer 17. By applying the insulating material, the insulating material is infiltrated into the expanded pit 20, and an uncured insulating layer 21 is formed on the p-type GaN layer 17 together with the pit 20 as shown in FIG. The uncured insulating layer 21 is cured by heating and ultraviolet irradiation treatment.

The insulating material is a resin that has insulating properties and adheres closely to the GaN layer. Further, a curable resin that can be cured by heat or ultraviolet light is desirable, and a transparent resin is preferable. As an insulating material having such conditions, for example, a silicone resin such as MOMENTIVE (registered trademark), Shin-Etsu Silicone (registered trademark), Permeate (registered trademark), or an ultraviolet resistant epoxy resin can be used. SiO ₂ can also be used.

  In order to embed the insulating material in the pit 20, a method of natural penetration by potting on the p-type GaN layer 17, after potting on the p-type GaN layer 17, the insulating material is poured into the pit 20 by covering with glass or the like. A method of engraving, a method of sealing the surface other than the surface of the p-type GaN layer 17 and immersing the surface of the p-type GaN layer 17 in a solution of an insulating material to infiltrate the insulating material into the pit 20, under a reduced pressure or vacuum environment, Use a method of applying an insulating material to the surface of the p-type GaN layer 17 (for example, spraying, immersion liquid, spin coating, scraper coating, etc.), a method of forming a film using vapor deposition, chemical vapor deposition, or the like. Can do.

  In the insulating material polishing step, the insulating layer 21 on the p-type GaN layer 17 is removed by lapping and polishing. Specifically, chemical mechanical polishing is performed on the insulating layer 21 on the p-type GaN layer 17. Lapping and polishing must be performed so as not to physically damage the p-type GaN layer 17. When the insulating layer 21 on the p-type GaN layer 17 is removed, only the insulating layer 21 in the pit 20 remains as shown in FIG.

  The insulating material application process and the insulating material polishing process are filling processes for filling the pits 20 expanded by the wet etching process.

  In the dry etching step, the p-type GaN layer 17 is masked by using a photolithography method, and the p-type GaN layer 17, the AlInGaN layer 16, the InGaN layer 15, and the n-type GaN layer 14 are etched by dry etching to form an n-type. The step portion 25 is formed by partially exposing the GaN layer 14 as shown in FIG.

  In the p-type electrode formation step, an ITO electrode 22 (electrode layer) is formed on the p-type GaN layer 17 by vapor deposition or sputtering as shown in FIG. At this time, an electrode pattern (not shown) is formed on the ITO electrode 22 by wet etching or lift-off using photolithography. In addition, the ITO electrode 22 is annealed in a heat treatment furnace, whereby the ITO electrode 22 is further transparentized.

  In the n-type electrode forming step, a TiAl electrode 23 is formed on the n-type GaN layer 14 exposed as the stepped portion 25 in the dry etching step as shown in FIG. 1G by vapor deposition or sputtering.

  In the p electrode pad forming step, an electrode pad 24 made of, for example, gold is formed on the ITO electrode 22 as shown in FIG. The electrode pad 24 is formed in contact with the p-type GaN layer 17. By forming the electrode pad 24 in the p-electrode pad forming step, a face-up type light emitting element is completed.

  Here, the reason why the pits 20 are generated in the p-type GaN layer 17 will be described.

The p-type GaN layer 17 and the p-type AlInGaN layer 16 are doped with Mg to form a p-type semiconductor, but the impurity level of Mg in the nitride semiconductor is as deep as about 100 meV, and the activation rate is as low as about 1 to several percent. . Therefore, in order to obtain a carrier concentration of 5 × 10 ¹⁷ to 1 × 10 ¹⁸ , 50 to 100 times the impurity doping is required. When impurities of the above concentration are doped in the mother crystal, the crystal quality is liable to deteriorate, the surface morphology may become uneven, and pits may be generated.

  On the other hand, since the InGaN used for the InGaN layer 15 is difficult to stably maintain a mixed crystal at a high temperature, the growth temperature of the p-type GaN layer 17 is lower than that of the n-type GaN layer 14. Further, when a light emitting device having a long wavelength is manufactured using a nitride semiconductor, it is necessary to take in a large amount of In into the active layer. When the p-type GaN layer 17 is grown at a high temperature, the In layer of the active layer is aggregated. Further low temperature growth is required to cause adverse effects. Therefore, when the p-type GaN layer 17 grows at a low temperature, the crystallinity of the p-type GaN layer 17 drops, so that the pits penetrate the p-type GaN layer 17 in the stacking direction.

  When the pit 20 is generated based on the crystal defect of the p-type GaN layer 17, when the ITO electrode 22 and the electrode pad 24 are formed, the electrode materials reach the pit 20 to the inside. Occur. Further, during use, the electrode material may migrate to the pits 20 due to migration and cause a short circuit failure. In order to cope with this, an insulating material is applied in the pit 20 and the insulating layer 21 is formed as described above.

  FIG. 2A shows the positions of threading dislocations 32 with respect to the pits 20 when the insulating layer 31 is formed in the pits 20 of the p-type GaN layer 17 without providing the above-described wet etching process at the manufacturing stage of the light emitting device. FIG. 2B shows the position of the threading dislocation 33 with respect to the pit 20 when the insulating layer 21 is formed in the pit 20 expanded in the lateral direction in the wet etching process in the manufacturing stage. In FIG. 2B, the threading dislocation 33 is located in the bottom surface of the expanded pit 20 and is discontinuous with the inner wall of the pit 20.

  In the case of FIG. 2 (a), when power is supplied between the electrodes 22 and 23, the inner wall surface of the pit 20 is directly connected to the threading dislocation 32 at the end. 2A flows through the threading dislocation 32.

  On the other hand, in the case of FIG. 2B, since the bottom surface 20a is formed at the boundary of the pit 20, the p-type semiconductor layer (the p-type AlInGaN layer 16 of the p-type AlInGaN layer 16) is formed between the inner wall surface of the pit 20 and the threading dislocation 33. The surface) is located. In the p-type semiconductor layer, current flows in the stacking direction, but resistance is large in the direction perpendicular to the p-type semiconductor layer, and almost no current flows. Therefore, even if power is supplied between the electrodes 22 and 23, leakage current is prevented from flowing through the inner wall surface of the pit 20 and the threading dislocation 32 due to the presence of the bottom surface 20 a having a large resistance. Further, since the insulating layer 21 is also formed in the expanded pit 20, the electrode material is prevented from entering the pit 20 during the subsequent formation of the ITO electrode 22 and the electrode pad 24. As a result, it is possible to eliminate the cause of defects such as leakage or short circuit in the semiconductor light emitting device itself.

  In Embodiment 1 described above, the pits 20 are present in the p-type GaN layer 17 before wet etching. However, the present invention can be performed by wet etching the p-type GaN layer 17 having no pits. This includes the case where pits appear in crystal defects. Also in this case, the pit that appears has a bottom surface and is filled with an insulating material, so that leakage current can be prevented from flowing through the inner wall surface of the pit.

  FIGS. 3A to 3H and FIGS. 4A to 4F show a method for manufacturing a face-down type nitride semiconductor light emitting device as Example 2 of the present invention. The manufacturing method of Example 2 corresponds to the reference numerals (a) to (h) in FIG. 3, and (a) an epitaxial layer growth process, (b) a wet etching process, (c) an insulating material application process, and (d) an insulation. 4. Material polishing step, (e) dry etching step, (f) p-type electrode forming step, (g) n-type electrode forming step, and (h) passivation film forming step, and symbols (a) to (f) in FIG. (A) Passivation film etching step, (b) Bonding layer formation step, (c) Support substrate preparation step, (d) Support substrate bonding step, (e) Growth substrate peeling step, and (f) Surface roughening It has steps and is executed in that order.

  The epitaxial layer growth process, wet etching process, insulating material application process, and insulating material polishing process in FIGS. 3A to 3D are the same as those in FIGS. The description here is omitted.

  In the dry etching process after the insulating material polishing process, the p-type GaN layer 17 is masked by photolithography, and the p-type GaN layer 17, the AlInGaN layer 16, The InGaN layer 15 and the n-type GaN layer 14 are etched to form a recess 41 as shown in FIG. 3E to partially expose the n-type GaN layer 14. The cross-sectional width of the recess 41 in the lateral direction (direction perpendicular to the stacking direction) is gradually narrowed from the upper surface of the p-type GaN layer 17 toward the n-type GaN layer 14.

  In the p-type electrode forming step, a mask is formed on the p-type GaN layer 17 by using a photolithography method, an ohmic highly reflective film made of Pt having a thickness of 1 nm and Ag having a thickness of 200 nm is formed, and further made of TiPtAu. A diffusion prevention layer is formed, and then the portion remaining after lift-off is used as a p-type electrode 42 as shown in FIG. It should be noted that other materials such as Ni, Rh, and ITO may be used as the adhesive material for the ohmic high reflection film instead of Pt.

  In the n-type electrode formation step, a mask is formed on the n-type semiconductor layer 14 exposed in the concave portion 41 using a photolithography method, an ohmic electrode made of TiAl is formed, and the n-electrode 43 is formed by lift-off. The Thereafter, for example, heat treatment is performed at about 500 ° C. As shown in FIG. 3G, the n-electrode 43 contacts the n-type semiconductor layer 14 in the recess 41 and reaches the surface of the p-type GaN layer 17 through the inclined inner wall surface of the recess 41.

In the passivation film forming step, an insulating material such as SiO ₂ is applied on the p-type GaN layer 17 including the recess 41, the p-type electrode 42, and the n-electrode 43, and as a result, as shown in FIG. A passivation film 44 is formed.

  In the passivation film etching step, a mask having openings on the p-electrode 42 and the n-electrode 43 is formed on the passivation film 44 using a photolithography method, and the passivation film 44 exposed in the openings is etched with BHF. As shown in FIG. 4A, the p-electrode 42 and the n-electrode 43 are exposed.

  In the bonding layer forming step, a mask is formed by patterning on the passivation film 44 including the p-type electrode 42 and the n-electrode 43 exposed by photolithography, and a bonding layer made of TiAuPtAu is formed and lifted off. A first bonding layer 45 is formed on the upper surfaces of the exposed p-type electrode 42 and n-electrode 43 as shown in FIG. 4B.

  In the support substrate preparation step, as shown in FIG. 4C, a support substrate 50 made of Si or the like on which the second bonding layer 51 is formed is prepared. The second bonding layer 51 on one main surface of the support substrate 50 is connected to a circuit pattern 53 formed on the other main surface of the support substrate 50 through a conduction path 52 in the support substrate 50.

  In the support substrate bonding step, the first adhesive layer 45 and the second adhesive layer 51 are brought into contact with each other, for example, heated to 300 ° C. while being pressurized at a pressure of 3 MPa, held for 10 minutes, and then cooled to room temperature. Fusion bonding is performed, and the light emitting element structure (the structure shown in FIG. 4B) is disposed on the support substrate 50 as shown in FIG. In this bonding step, bonding is actually performed in units of one wafer in which a plurality of light emitting elements are formed, not in units of one light emitting element.

  In the growth substrate peeling step, UV excimer laser light is irradiated from the back side of the growth substrate 11, and the interface between the growth substrate 11 and the low-temperature buffer layer 12 is thermally decomposed to grow as shown in FIG. The substrate 11 is peeled off.

  In the surface roughening process, Ga droplets are removed from the peeled surface of the low-temperature buffer layer 12 with hot water or dilute hydrochloric acid, and planarized using a polishing process or the like. Further, by etching these with an etching solution, a fine uneven surface 55 is formed on the surface of the n-type GaN layer 14 as shown in FIG. Thereafter, although not shown, the elements are separated by dicing to complete a face-down light emitting element as one chip.

  Also in this face-down type light emitting element, the bottom surface 20a is formed at the boundary of the pit 20 as in the case of the face-up type light emitting element shown in FIG. A p-type semiconductor layer is located between the threading dislocations and the p-type semiconductor layer has a current flowing in the stacking direction, but has a large resistance in the direction perpendicular to it and hardly flows a current. Therefore, the leakage current does not flow through the inner wall surface of the pit 20 and the threading dislocation due to the presence of the bottom surface 20a having a large resistance.

  In each of the above-described embodiments, the low temperature buffer layer 12, the undoped GaN layer 13, the n-type GaN layer 14, the InGaN / GaN layer 15, the p-type AlInGaN layer 16, and the p-type GaN layer 17 are arranged from the growth substrate 11 side. Although the GaN-based semiconductor structure layers are sequentially stacked, the present invention is not limited to the GaN-based semiconductor structure layers, and may be applied to other crystal-based semiconductor structure layers such as GaAs-based semiconductor structure layers. be able to. In each of the above-described embodiments, the first conductivity type is n-type, and the second conductivity type opposite to the first conductivity type is p-type. However, the present invention sets the first conductivity type to p-type. It can be applied to a semiconductor structure layer having a n-type second conductivity type. That is, in the present invention, on the growth substrate, the first semiconductor layer having the first conductivity type, the active layer, the second semiconductor layer having the second conductivity type, and the third semiconductor layer having the second conductivity type. Any semiconductor structure layer may be formed by stacking the semiconductor layers in that order. In such a semiconductor structure layer, the semiconductor layer flows to threading dislocations through pits based on crystal defects in the third semiconductor layer on the outermost surface. Leakage current can be prevented.

11 Growth substrate 12 Low-temperature buffer layer 13 Undoped GaN layer 14 n-type GaN layer 15 InGaN / GaN layer 16 p-type AlInGaN layer 17 p-type GaN layer 20 Pit 21 Insulating layer 21a Bottom surface

Claims (13)

On the growth substrate, a first semiconductor layer having a first conductivity type, an active layer, a second semiconductor layer having a second conductivity type, and a third semiconductor layer having the second conductivity type are stacked in that order. A growth process for forming a semiconductor structure layer;
Wet etching for selectively etching the third semiconductor layer is performed, and pits based on crystal defects of the third semiconductor layer are expanded to form an interface between the third semiconductor layer and the second semiconductor layer. A wet etching step for forming the bottom surface of the pit;
And a filling step of filling the pits expanded in the wet etching step with an insulating material. The semiconductor structure layer is a GaN (gallium nitride) based semiconductor structure layer,
The manufacturing method according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The manufacturing method according to claim 1, wherein the second semiconductor layer contains aluminum. The filling step includes applying an insulating material on the third semiconductor layer including the inside of the pit;
An insulating material polishing step of polishing the insulating material applied in the insulating material application step to remove the insulating material on the third semiconductor layer. 2. The production method according to claim 1.   5. The manufacturing method according to claim 1, wherein an alkaline aqueous solution is used as an etching solution in the wet etching step.   6. The manufacturing method according to claim 1, wherein the insulating material is made of a silicone resin, an epoxy resin, or silicon dioxide.   The manufacturing method according to claim 1, further comprising a step of forming an electrode layer on the third semiconductor layer after the filling step.   The pit expanded in the wet etching step includes a pit that appears based on a crystal defect of the third semiconductor layer in the wet etching step. The manufacturing method as described. A first semiconductor layer having a first conductivity type, an active layer, a second semiconductor layer having a second conductivity type, and a third semiconductor layer having the second conductivity type are sequentially stacked to have a semiconductor structure layer A semiconductor light emitting device,
A pit having a bottom surface at the interface with the second semiconductor layer is formed in the third semiconductor layer, and the pit is filled with an insulating material. The semiconductor structure layer is a GaN (gallium nitride) based semiconductor structure layer,
10. The semiconductor light emitting device according to claim 9, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The semiconductor light emitting element according to claim 9, wherein the second semiconductor layer contains aluminum.   12. The semiconductor light emitting device according to claim 9, wherein the insulating material is made of silicone resin, epoxy resin, or silicon dioxide.   The semiconductor light emitting device according to claim 9, wherein an electrode layer is mounted on the third semiconductor layer.

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