JP2010141084A - Method of manufacturing semiconductor light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor light-emitting element of which light extraction efficiency and heat dissipation are improved and prevents cracking on a surface of a growth layer during peeling of a substrate for growth to improve the yield. <P>SOLUTION: The method of manufacturing the semiconductor light-emitting element comprises: forming a plurality of separation grooves demarcating semiconductor light-emitting device regions on the surface of the substrate for growth; forming the growth layer on the substrate for growth; forming a first electrode on the growth layer; separating the growth layer to form insulating films separated inside and outside the separation grooves; forming pad electrodes separated inside and outside the separation grooves; forming a metal layer covering the pad electrodes, outside the separation grooves; and peeling the substrate for growth from the growth layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly, to a method for manufacturing a semiconductor light emitting device having a peeling step for separating a growth substrate and a laminated structure formed of a plurality of semiconductor layers formed on the growth substrate.

  Light emitting diodes (hereinafter referred to as LEDs) are mainly used for tail lamps of automobiles, various display devices, and backlights of mobile devices such as mobile phones. In the future, demand for automobile headlights, liquid crystal display backlights, general lighting, etc. is expected to increase significantly. As a material for such an LED, for example, a nitride semiconductor is used. Nitride semiconductors are difficult to produce bulk single crystals, so growth layers such as GaN are grown on different substrates such as sapphire or SiC by metal organic chemical vapor deposition (MOCVD). Has been done. A sapphire substrate has been particularly used as a growth substrate because of its excellent stability in a high-temperature ammonia atmosphere in an epitaxial growth process.

  For example, in Patent Document 1, a sapphire substrate is used as a growth substrate, a support is bonded to an epitaxially grown growth layer, and the sapphire substrate is peeled off from the epitaxially grown growth layer by a laser lift off (LLO) method. A technique for manufacturing a semiconductor light emitting device using a growth layer from which a sapphire substrate is peeled is disclosed.

Here, the laser lift-off method refers to irradiating a YAG laser beam or excimer laser beam from the sapphire substrate side to a wafer having a growth layer such as GaN formed on the sapphire substrate, and the energy of the laser beam is sapphire substrate. The GaN layer formed on the sapphire substrate is decomposed into metal Ga and N ₂ gas by the energy absorbed between the substrate and the growth layer and further converted into heat. It is a peeling method.

  On the other hand, the luminous efficiency of current LEDs is about 50 lm / W (lumen / watt), but a luminous efficiency of 100 lm / W or more is required for use in backlights, lighting, and the like. The luminous efficiency of the LED is determined by the product of the internal quantum efficiency during light emission in the light emitting layer and the efficiency for extracting the light to the outside (light extraction efficiency). So far, the internal quantum efficiency has been improved to 80% or more, but there is room for improvement in light extraction efficiency. Further, since the heat generated with light emission increases when the light emission efficiency is improved, it is necessary to efficiently dissipate the generated heat to the outside of the semiconductor light emitting element from the viewpoint of the reliability of the semiconductor light emitting element.

For example, Patent Document 2 discloses that semiconductor growth is performed by etching a growth layer epitaxially grown on a sapphire substrate so that the side surface of the growth layer is inclined with respect to the sapphire substrate and a reflective film is formed on the inclined side surface. A technique for improving the light extraction efficiency of an element is disclosed. Also disclosed is a technique for improving the heat dissipation of a semiconductor light emitting device by embedding a metal in a trench region formed by the etching.
JP2007-134415A JP 2006-135321 A

Patent Document 1 discloses a method for manufacturing a semiconductor light emitting element, in which a separation groove for releasing N ₂ gas generated at the time of laser lift-off to the outside of a wafer is formed by two etchings. Since the N ₂ gas generated at the time of laser lift-off is released from the separation groove, it is possible to prevent cracks generated on the separation surface of the growth layer due to the pressure of the N ₂ gas.

  However, in the method for manufacturing a semiconductor light emitting device disclosed in Patent Document 1, it is impossible to embed a metal in the separation groove described above for the purpose of using the separation groove. Therefore, the semiconductor light emitting device disclosed in Patent Document 1 cannot secure sufficient heat dissipation and cannot obtain excellent reliability. Further, in the method for manufacturing a semiconductor light emitting device disclosed in Patent Document 1, it is possible to cover the side surface of the active layer with a protective insulating film, but it is difficult to cover the side surface of the n-type semiconductor layer with the protective insulating film. It is. Therefore, the semiconductor light emitting device disclosed in Patent Document 1 has light leakage from the side surface of the n-type semiconductor layer, and cannot sufficiently improve the light extraction efficiency.

  On the other hand, in the method for manufacturing a semiconductor light emitting device disclosed in Patent Document 2, the heat dissipation of the semiconductor light emitting device can be improved by embedding a metal in a trench formed by etching.

However, since the trench is filled with metal, N ₂ gas generated at the time of laser lift-off cannot be released, and there is a problem that cracks are generated on the peeling surface of the growth layer due to the pressure of N ₂ gas.

  The present invention has been made in view of the circumstances as described above, and improves the light extraction efficiency and heat dissipation of the semiconductor light-emitting element, and prevents the generation of cracks on the surface of the growth layer when the growth substrate is peeled off. It is an object of the present invention to provide a method for manufacturing a semiconductor light emitting device capable of improving the yield.

In order to solve the above-described problems, a method for manufacturing a semiconductor light-emitting device according to the present invention includes a groove forming step for forming a plurality of separation grooves for defining a semiconductor light-emitting device region on the surface of a growth substrate, and formation of the separation grooves. On the growth substrate, having the first conductivity type and Al _x In _y Ga _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) A first semiconductor layer, an active layer, and a second conductivity type, and Al _x In _y Ga _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = A growth step in which a second semiconductor layer comprising 1) is sequentially stacked to form a growth layer; a separation step in which the separation groove portion is etched to separate the growth layer; and a growth layer formed in the semiconductor light emitting device region An insulating film forming step of forming an insulating film on the exposed surface and the bottom of the isolation groove, a pad electrode forming step of forming a pad electrode on the exposed portion of the first electrode and the insulating film, and a metal covering the pad electrode Minutes layer A metal layer forming step formed outside the separation groove, and a separation step of separating the growth substrate from the growth layer by a laser lift-off method to expose the growth layer. The internal insulating film and the insulating film outside the separation groove are formed apart from each other, and the pad electrode forming step includes forming the pad electrode inside the separation groove and the pad electrode outside the separation groove apart from each other. Features.

  According to the method for manufacturing a semiconductor light emitting device of the present invention, a plurality of separation grooves for defining a semiconductor light emitting device region are formed on the surface of the growth substrate, a growth layer is formed on the growth substrate, and the first layer is formed on the growth layer. 1 is formed, the growth layer is separated, an insulating film separated from the inside and outside of the separation groove is formed, a pad electrode separated from the inside and outside of the separation groove is formed, and the pad electrode is covered By forming the layer outside the separation groove and separating the growth substrate from the growth layer, a void surrounded by the growth substrate, the growth layer, the insulating film, the pad electrode, and the metal layer can be formed. Since the gas generated when the growth substrate is peeled is released to the outside through the gap, it is possible to prevent generation of cracks on the surface of the growth layer when the growth substrate is peeled. Further, according to the method for manufacturing a semiconductor light emitting device, the side surface of the growth layer is covered with the insulating film, and further, the insulating film is covered with the pad electrode and the metal layer, so that the light extraction efficiency and the heat dissipation of the semiconductor light emitting device can be improved. Can be planned.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  A method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention will be described in detail with reference to FIGS. 1, 5, 6, and 8 are cross-sectional views for each manufacturing process of the semiconductor light emitting device. 2 and 3 are plan views of the wafer in FIG. 4 is an enlarged view of a region surrounded by a broken line 4 in FIG. 1C, and FIG. 7 is an enlarged view of a region surrounded by a broken line 6 in FIG. 6B.

(Growth substrate preparation process)
In the present embodiment, a metal organic chemical vapor deposition method (MOCVD: Metal Organic Chemical Vapor Deposition ) by _{Al x In y Ga z N (} 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, x + A C-plane sapphire substrate 11 (hereinafter simply referred to as sapphire substrate 11) is prepared as a substrate (growth substrate) on which a growth layer of y + z = 1) can be formed (FIG. 1A). The growth substrate is not limited to the C-plane sapphire substrate of this embodiment, and a-plane sapphire, ZnO, MgO, MgAl ₂ O _4, AlN, or the like may be used.

(Groove formation process)
Next, a resist is applied on the prepared sapphire substrate 11. Subsequently, the resist is patterned by photolithography. Further, dry etching is performed on the surface of the sapphire substrate 11 using the patterned resist as a mask, and separation grooves (concave portions) 12 are formed on the surface of the sapphire substrate 11 (FIG. 1B). By forming the separation groove 12, an uneven shape is formed on the sapphire substrate 11. Here, an element forming region (semiconductor light emitting element region) of the semiconductor light emitting element is demarcated by the separation groove 12, and the convex portion 13 becomes a semiconductor light emitting element forming region (chip forming region). As shown in FIG. 2A, for example, the separation grooves 12 are formed in a lattice shape on the surface of the sapphire substrate 11. The convex portion 13 which is a region surrounded by the separation grooves 12 formed in a lattice shape is a formation region of the semiconductor light emitting element. The separation groove 12 is formed up to the end of the sapphire substrate 11. That is, the separation groove 12 communicates with the outside of the sapphire substrate 11. The depth of the separation groove 12 needs to be deeper than the total film thickness of the insulating film and the pad electrode formed on the convex portion 13 in a process described later. The reason for this is that the insulating film and pad electrode formed on the bottom of the separation groove 12 do not contact the insulating film and pad electrode formed on the convex portion 13, that is, in a separated state (hereinafter referred to as step breakage). (Referred to as a state). For example, the depth of the separation groove 12 is about 2 μm (micrometer) and the width is about 50 μm.

  The separation grooves 12 are not limited to being formed in a lattice shape. For example, as shown in FIG. 2B, a plurality of separation grooves 12 are arranged in parallel on the sapphire substrate 11. It may be formed. Even when the separation groove 12 is formed as shown in FIG. 2B, the separation groove 12 is formed up to the end of the sapphire substrate 11.

  Further, as shown in FIG. 3A, the separation grooves 12 may be formed such that each of the chip formation regions 31 is surrounded by one independent separation groove 12. Further, each of the separation grooves 12 shown in FIG. 3A may communicate with another adjacent separation groove 12.

(Growth layer formation process)
In this embodiment, a metal organic chemical vapor deposition method (MOCVD: Metal Organic Chemical Vapor Deposition ) by _{Al x In y Ga z N (} 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, x + y A growth layer 14 of + z = 1) is formed. Each semiconductor layer constituting the growth layer 14 is stacked on the sapphire substrate 11 along the C-axis direction of the wurtzite crystal structure by MOCVD. In this embodiment, the sapphire substrate 11 is adjusted by adjusting the growth gas V / III ratio and growth rate.
The film is grown under conditions that promote growth in a direction parallel to the surface of the film (lateral direction). Specifically, the growth layer 14 is formed through the following processing.

First, thermal cleaning is performed on the prepared sapphire substrate 11. Specifically, the sapphire substrate 11 is carried into an MOCVD apparatus, and is subjected to heat treatment for about 10 minutes in a hydrogen atmosphere at about 1000 degrees Celsius (1000 ° C.). Subsequently, the ambient temperature is adjusted to about 500 ° C., and TMG (trimethyl gallium) (flow rate: 10.4 μmol / min) and NH ₃ (flow rate: 3.3 LM) are supplied for about 3 minutes. A buffer layer 14A is formed. Thereafter, the ambient temperature is raised to about 1000 ° C., and this state is maintained for about 30 seconds, whereby the low temperature buffer layer 14A is crystallized. Subsequently, TMG (flow rate: 45 μmol / min) and NH ₃ (flow rate: 4.4 LM) are supplied for about 20 minutes while the ambient temperature is maintained at about 1000 ° C., so that the film thickness is about 1 μm. A base GaN layer 14B is formed. Next, when the ambient temperature is about 1000 ° C., TMG (flow rate: 45 μmol / min), NH ₃ (flow rate: 4.4 LM) and SiH ₄ (flow rate: 2.7 × 10 ⁻⁹ mol / min) as the dopant gas are about By supplying for 100 minutes, an n-type semiconductor layer 14C made of an n-type GaN layer having a thickness of about 5 μm is formed.

Subsequently, an active layer 14D is formed on the n-type semiconductor layer 14C. In this embodiment, a multi-quantum well structure made of InGaN / GaN is applied to the active layer 14D, and five cycles of growth are performed with one cycle of InGaN / GaN. Specifically, TMG (flow rate: 3.6 μmol / min), TMI (trimethylindium) (flow rate: 10 μmol / min), and NH ₃ (flow rate 4.4 LM) are supplied for about 33 seconds in an ambient temperature of about 700 ° C. As a result, an InGaN well layer having a thickness of about 2.2 nm is formed. Subsequently, TMG (flow rate: 3.6 μmol / min) and NH ₃ (flow rate: 4.4LM) are supplied for about 320 seconds, thereby forming a GaN barrier layer having a thickness of about 15 nm. By repeating this process for five cycles, the active layer 14D is formed.

Next, the ambient temperature was raised to about 870 ° C., TMG (flow rate: 8.1 μmol / min), TMA (trimethylaluminum) (flow rate: 7.5 μmol / min), NH ₃ (flow rate: 4.4 LM), and CP2Mg as a dopant. By supplying (bis-cyclopentadienyl magnesium) (flow rate: 2.9 × 10 ⁻⁷ μmol / min) for about 5 minutes, a p-type AlGaN cladding layer 14E having a film thickness of about 40 nm is formed. . Subsequently, TMG (flow rate: 18 μmol / min), NH ₃ (flow rate: 4.4 LM) and CP2Mg as a dopant (flow rate: 2.9 × 10 ⁻⁷ μmol / min) while maintaining the ambient temperature at about 870 ° C. Is supplied for about 7 minutes to form a p-type semiconductor layer 14F made of a p-type GaN layer having a thickness of about 150 nm.

  By performing the above processing, the low-temperature buffer layer 14A, the underlying GaN layer 14B, the n-type semiconductor layer 14C, the active layer 14D, the p-type AlGaN cladding layer 14E, and the p-type semiconductor layer 14F are sequentially stacked. A certain growth layer 14 is formed. A cross-sectional view when the formation of the growth layer 14 is completed is shown in FIGS. Since the epitaxial growth in this step is a condition for promoting the lateral direction, the cross section of the growth layer 14 grown on the separation groove 12 and the convex portion 13 has a substantially trapezoidal shape. Further, the growth layer 14 formed inside the separation groove 12 and the growth layer 14 formed on the convex portion 13 are connected at the upper part of the separation groove 12.

  In the present embodiment, a hexagonal sapphire substrate 11 is used as the growth substrate. Therefore, the growth layer 14 grown on the sapphire substrate 11 is a group III nitride semiconductor crystal having a wurtzite (hexagonal) crystal structure.

(P electrode formation process)
After the growth layer 14 is grown, a resist is applied on the growth layer 14. Subsequently, the resist is patterned by photolithography. A p-electrode 15 is formed on the patterned opening of the resist by electron beam evaporation (FIG. 1D). For example, the p electrode 15 is a multilayer film made of Ag / Ti / Pt / Au. Here, the thicknesses of Ag are 200 nm, Ti is 100 nm, Pt is 150 nm, and Au is 1000 nm. The p-electrode 15 may be formed by resistance heating vapor deposition or electron beam vapor deposition. After the formation of the p-electrode 15, the patterned resist is removed.

(Element isolation process)
After the p-electrode 15 is formed, a resist 16 is applied on the growth layer 14 and the p-electrode 15. Subsequently, the resist 16 is patterned by photolithography so as to cover the convex portions 13 (FIG. 1F). Dry etching is performed using the patterned resist 16 as a mask, the growth layer 14 formed on the separation groove 12 is removed, and then the resist 16 is removed. Thus, the growth layer 14 is separated for each chip (FIG. 5A). Here, the side surface of the growth layer 14 separated for each chip is inclined by about 70 degrees from the bottom surface of the separation groove 12. By forming such an inclined side surface, an insulating film can be easily formed on the side surface of the growth layer 14 in a process described later. The inclination angle can be changed depending on the shape of the resist 16. The inclination angle can be changed within a range of about 60 to 80 degrees from the viewpoint of easy formation of the insulating film and securing of the light emitting surface. The reason for setting the tilt angle within such a range is that if the tilt angle is 60 degrees or less, the light emitting surface becomes small, and if the tilt angle is 80 degrees or more, it is difficult to form an insulating film.

(Insulating film formation process)
After the growth layer 14 is separated for each chip, the insulating film 17a is formed by a known film formation technique such as a vacuum evaporation method or a sputtering method so as to cover the growth layer 13 and the p electrode 15 formed on the convex portion 13. It is formed. In addition, an insulating film 17b is formed on the bottom surface of the isolation groove 12, but since the depth of the isolation groove 12 is deeper than the film formation amount of the insulating film 17b, the insulating film formed on the side surface of the growth layer 14 17a and the insulating film 17b formed on the bottom surface of the separation groove 12 are separated (stepped). That is, the insulating film 17b inside the separation groove 12 and the insulating film 17a outside the separation groove 12 are separated. As a material of the insulating films 17a and 17b, a material capable of reflecting light emitted from the active layer 14D constituting the growth layer 14 is desirable, and for example, SiO ₂ can be used.

  Next, a resist is applied on the insulating film 17a. Subsequently, the resist is patterned by photolithography. Further, the insulating film 17a is dry-etched using the patterned resist as a mask, and an opening 18 is formed in the insulating film 17a. By forming the opening 18, the p-electrode 15 is exposed. A cross-sectional view of the state in which the opening 18 is formed is shown in FIG. Since the insulating film 17a is formed not only on the side surface of the growth layer 14 but also around the p electrode 15, the light emitted from the active layer 14D constituting the growth layer 14 is efficiently reflected. Become.

(Pad electrode formation process)
Next, a pad electrode 19a is formed by a known film forming technique such as a vacuum deposition method so as to cover the growth layer 14, the p electrode 15 and the insulating film 17a formed on the convex portion 13. The pad electrode 19b is also formed on the insulating film 17b formed on the bottom surface of the isolation groove 12, but the depth of the isolation groove 12 is deeper than the film formation amounts of the insulating film 17b and the pad electrode 19b. The pad electrode 19a formed on the side surface of the growth layer 14 and the pad electrode 19b formed on the bottom surface portion of the separation groove 12 are separated (stepped) (FIG. 5C). That is, the pad electrode 19b inside the separation groove 12 and the pad electrode 19a outside the separation groove 12 are separated. The pad electrodes 19a and 19b can have a laminated structure of Ti / Au, for example.

(Metal layer forming process)
Next, the metal layer 20 is formed on the pad electrode 19a by electroplating. The metal layer 20 is formed so as to fill the space 21 between the pad electrodes 19a formed adjacent to each other (FIG. 5D). Here, since the pad electrode 19b formed inside the separation groove 12 and the pad electrode 19a formed on the p-electrode 15 and the insulating film 17a are in a stepped state, the pad electrode 19b is formed inside the separation groove 12. The metal layer 20 is hardly formed on the pad electrode 19b. This is because almost no current flows between the pad electrode 19b formed inside the separation groove 12 by the electroplating method and the plating metal. For example, the metal layer 20 is a metal such as Cu or Au.

  Note that a resist (not shown) is stacked on the pad electrode 19b formed inside the separation groove 12, and a power supply metal film (not shown) is formed on the resist and the pad electrode 19a by vapor deposition or the like. The The power supply metal film is also formed between the adjacent semiconductor light emitting element regions covering the semiconductor light emitting element region. Therefore, the metal layer 20 is collectively formed on all the semiconductor light emitting element regions on the wafer by the electroplating method using the power supply metal film. Even in such a method, since the disconnection between the pad electrode 19a and the pad electrode 19b is maintained, a growth substrate (e.g., a resist removal step using a solvent is easily added in the growth substrate peeling step described later). The sapphire substrate 11) will be peeled off. In addition, the efficiency of plating can be increased by patterning the power supply metal film so as to cover only the semiconductor light emitting element region that functions as a semiconductor light emitting element after the dicing process.

  Further, when the separation groove 12 is formed so as to surround each of the semiconductor light emitting element regions (for example, in the case of FIGS. 3A and 3B), the separation groove 12 is formed at the end of the growth substrate. The growth layer 14 can be formed evenly as compared with the case where it is formed (for example, in the case of FIGS. 2A and 2B). In the vapor phase growth, since a film is formed by flowing a growth gas from the outside toward the center through a circular growth substrate, when the separation groove 12 is formed up to the end of the wafer, the growth gas is used. It is considered that the separation gas 12 at the edge of the substrate disturbs the flow of the growth gas, and the uniformity of the film formation is lowered. That is, when the separation groove 12 does not reach the end of the growth substrate, it is possible to suppress the disturbance of the flow of the growth gas and to suppress the deterioration of the film formation uniformity.

  Note that the metal layer 20 may be formed by a method other than the electroplating method, but in such a case as well, it is desirable to fill the inside of the separation groove 12 with a resist. As a result, the metal layer 20 is not formed inside the separation groove 12, and the pad electrode 19 b inside the separation groove 12 and the pad electrode 19 a formed on the insulating film 17 a are electrically connected via the metal layer 20. This is because the connection is not made. Further, after the metal layer 20 is formed on the resist, the resist is removed.

  As described above, since the metal layer 20 is not formed inside the separation groove 12, a short circuit between the p-type semiconductor layer 14F and the n-type semiconductor layer 14C forming the growth layer 14 can be prevented.

(Conductive support bonding process)
After the metal layer 20 is formed, the wafer obtained in the above process and the prepared conductive support 22 are bonded together. Specifically, first, a conductive support 22 made of silicon to which boron is added is prepared. After depositing a Pt electrode (not shown) by sputtering on the surface of the conductive support 22 that is bonded to the wafer obtained in the above step (hereinafter referred to as the first main surface), A bonding layer (not shown) laminated in the order of Ni, Au, and AuSn is formed by vapor deposition. Further, a metal multilayer film (not shown) made of Pt is formed by sputtering on a surface (hereinafter referred to as a second main surface) facing the first main surface of the conductive support 22. ing. Note that the bonding layer and the metal multilayer film may be formed by electron beam evaporation.

Next, the bonding layer of the conductive support 22 and the metal layer 20 formed on the sapphire substrate 11 are in close contact with each other. Thereafter, the closely bonded sapphire substrate 11 and conductive support 22 are thermocompression bonded in a nitrogen atmosphere. The thermocompression bonding conditions are, for example, a pressure of about 300 to 500 N / cm ² , a temperature of about 320 ° C., and a pressure bonding time of about 10 minutes. By this thermocompression bonding, AuSn is melted and dissolved in AuSn in which Au and Ni are melted. Furthermore, Au and Sn diffuse and are absorbed by Ni. Subsequently, the molten AuSn is solidified, whereby the wafer obtained from the metal layer forming step and the conductive support 22 are bonded together (FIG. 6A).

  In the present embodiment, the bonding layer is formed only on the conductive support 22 side, but the bonding layer may also be formed on the metal layer 20 formed on the sapphire substrate 11.

(Growth substrate peeling process)
After completion of the conductive support bonding process, the sapphire substrate 11 is peeled from the growth layer 14. For peeling off the sapphire substrate 11, a known method such as laser lift-off (LLO) can be used. In laser lift-off, the laser beam is irradiated from the sapphire substrate 11 side (FIG. 6B), so that the energy of the laser beam is absorbed by the growth layer 14 near the interface with the sapphire substrate 11. Further, the absorbed energy is converted into heat, whereby the GaN layer formed on the sapphire substrate 11 is decomposed into metal Ga and N ₂ gas. For example, a YAG laser or an excimer laser can be used as a laser used in laser lift-off.

FIG. 7 is an enlarged view of a region 7 surrounded by a broken line in FIG. As shown in FIG. 7, the N ₂ gas generated near the interface between the sapphire substrate 11 and the growth layer 14 by the irradiation of the laser light is generated from the sapphire substrate 11 and the growth layer 14 and from the vicinity of the interface. 14 flows into the separation groove 12 which is a gap with the gap 14. Here, since the separation groove 12 communicates with the outside of the sapphire substrate 11, the N ₂ gas flowing into the separation groove 12 is released from the separation groove 12 to the outside of the wafer. As a result, the N ₂ gas generated by the laser light irradiation does not stay near the interface between the sapphire substrate 11 and the growth layer 14, and damage to the growth layer 14 due to the pressure of the N ₂ gas can be prevented.

In addition, when the separation groove 12 is formed as shown in FIG. 2B, the separation groove 12 is formed up to the end of the sapphire substrate 11, so that N ₂ gas generated at the time of laser lift-off is generated. Can be released to the outside.

On the other hand, in the case where the separation grooves 12 are formed so that each of the chip formation regions 31 is surrounded by one independent separation groove 12 as shown in FIG. N ₂ gas remains in the vicinity of (that is, the separation groove 12). For this reason, when the separation groove 12 is formed as shown in FIG. 3A, the separation groove 12 is prevented from being damaged by the pressure of the N ₂ gas remaining in the separation groove 12. It is necessary to adjust the size.

Further, when each separation groove 12 is communicated with another adjacent separation groove 12 as shown in FIG. 3B, N ₂ generated at the time of laser lift-off due to the communication between the separation grooves 12. The gas can be dispersed throughout the surface of the sapphire substrate 11. Such dispersion of N ₂ gas can prevent breakage of each chip. That is, even when there is a difference in the amount of N ₂ gas generated from each of the chip formation regions 31, there is no problem that only the chip having a large amount of N ₂ gas is damaged.

  Next, the sapphire substrate 11 can be easily peeled by heating the wafer to which the conductive support 22 is bonded at 30 degrees or more (FIG. 6C). The reason why the sapphire substrate 11 can be easily peeled off by such heating is a temperature at which the melting point of the metal Ga decomposed from the GaN layer by laser light irradiation is relatively low (about 30 ° C.). This is because the melting point is easily reached. Note that after the sapphire substrate 11 is peeled off, the n-type semiconductor layer 14C or the underlying GaN layer 14B is exposed.

(Roughening process)
Next, protrusions 23 effective for improving light extraction efficiency are formed on the surface of the growth layer 14 exposed by the above-described growth substrate peeling step. Specifically, the surface of the growth layer 14 is immersed in a KOH solution (concentration: 5 mol / l) at about 50 ° C. for about 2 hours. In the present embodiment, since the pretreatment such as forming the low temperature buffer layer 14A by performing thermal cleaning during the growth layer forming step is performed, the growth layer 14 that is exposed when the sapphire substrate 11 is peeled off is used. The outermost surface is constituted by an N plane (C-plane) in which N atoms are arranged. Since the C-plane is chemically unstable, irregularities can be formed by wet etching. In addition, as described above, the growth layer 14 grown on the sapphire substrate 11 is a group III nitride semiconductor crystal having a wurtzite type (hexagonal) crystal structure. Accordingly, a plurality of hexagonal pyramidal projections 23 are formed in the exposed surface region of the growth layer 14 by such wet etching (FIG. 8A).

The hexagonal pyramidal projections 23 have a shape derived from the crystal structure of Al _x In _y Ga _z N having a wurtzite type (hexagonal) crystal structure, and the mask is formed by wet etching using a KOH solution. Etc. can be obtained easily and with good reproducibility. Depending on the composition of Al _x In _y Ga _z N and the growth conditions, by performing wet etching under the above conditions, a hexagonal pyramidal protrusion 23 having a width of about 1 μm and an angle between the bottom surface and the side surface of about 60 degrees is obtained. Is formed.

  The above-described wet etching process conditions can be changed according to the composition of the n-type semiconductor layer 14C constituting the growth layer 14, the size of the hexagonal pyramidal projections 23, and the like. For example, when the concentration of the KOH solution is fixed at 5 mol / l, the temperature can be changed between 50 ° C. and 70 ° C. and the time between 0.5 and 3 hours. If the wet etching process is performed at a temperature lower than the temperature range, the hexagonal pyramidal projections 23 become small, and thus there is a possibility that the light extraction efficiency cannot be sufficiently improved. On the other hand, if the wet etching process is performed at a temperature higher than the above temperature range, the etching rate is too high, so that the active layer 14D constituting the growth layer 14 may be etched or the hexagonal pyramidal projections 23 may be etched. There is also a possibility that the size becomes non-uniform.

  When the wet etching process is completed, the wafer is taken out from the KOH solution, and cleaned and dried.

(N-electrode formation process)
Next, an n-electrode 24 is formed on a part of the surface of the growth layer 14 on which the hexagonal pyramidal projections 23 are formed. As a specific forming method, a resist is applied on the surface of the growth layer 14 on which the hexagonal pyramidal projections 23 are formed. Subsequently, the resist is patterned by photolithography. An n-electrode 24 is formed in the patterned resist opening by electron beam evaporation (FIG. 8B). For example, the n electrode 24 is a multilayer film made of Ti / Al. Here, as for each film thickness, Ti is 25 nm and Al is 1000 nm. Note that the n-electrode 24 may be formed by resistance heating vapor deposition. After the formation of the n-electrode 24, the patterned resist is removed.

(Chip separation process)
A dicing apparatus is used to divide the wafer formed through the above steps into chips. The wafer is mounted on a dicing apparatus and is diced along a dicing line, whereby the wafer is divided into chips (FIG. 8C). Further, the wafer may be formed into chips by dicing using a pulse laser. In the present embodiment, since the separation groove 12 becomes a dicing line when the semiconductor light emitting element is divided into individual chips, the separation can be easily performed.

  The semiconductor light emitting device 100 according to this example is completed through the above steps.

As described above, in the manufacturing method of this embodiment, the separation groove 12 having a desired shape is formed in the sapphire substrate 11 which is a growth substrate, and the insulating film 17b and the pad electrode 19b formed inside the separation groove 12 are formed. The insulating film 17a and the pad electrode 19a formed on the element formation region are separated from each other. Further, in the manufacturing method of the present embodiment, the metal layer 20 is filled on the separation groove 12. Further, the metal layer 20 is not formed inside the separation groove 12. From the above, it is possible to prevent chip breakage due to N ₂ gas generated when the sapphire substrate 11 is peeled off, and to improve the heat dissipation of the semiconductor light emitting device.

It is sectional drawing which each manufacturing process in the manufacturing method of the semiconductor light-emitting device which is an Example of this invention. It is a top view of the sapphire substrate after formation of a separation groove. It is a top view of the sapphire substrate after formation of a separation groove. It is an enlarged view of the area | region 4 enclosed with the broken line of FIG.1 (c). It is sectional drawing which each manufacturing process in the manufacturing method of the semiconductor light-emitting device which is an Example of this invention. It is sectional drawing which each manufacturing process in the manufacturing method of the semiconductor light-emitting device which is an Example of this invention. It is an enlarged view of the area | region 7 enclosed by the broken line of FIG.6 (b). It is sectional drawing which each manufacturing process in the manufacturing method of the semiconductor light-emitting device which is an Example of this invention.

Explanation of symbols

11 Sapphire substrate 12 Separation groove 14 Growth layer 15 P electrodes 17a and 17b Insulating films 19a and 19b Pad electrode 20 Metal layer 22 Conductive support 23 Protrusion 24 N electrode 100 Semiconductor light emitting device

Claims (7)

A groove forming step of forming a plurality of separation grooves defining a semiconductor light emitting element region on the surface of the growth substrate;
On the growth substrate on which the isolation trench is formed, the first conductivity type and Al _x In _y Ga _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + a first semiconductor layer composed of y + z = 1), an active layer, and a second conductivity type, and Al _x In _y Ga _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) , X + y + z = 1), a growth step of sequentially stacking second semiconductor layers made of x + y + z = 1),
A first electrode forming step of forming a first electrode on the growth layer formed in the semiconductor light emitting element region;
Separating the growth layer by etching the separation groove portion; and
An insulating film forming step of forming an insulating film on the exposed surface of the growth layer formed in the semiconductor light emitting element region and the bottom of the separation groove;
A pad electrode forming step of forming a pad electrode on the exposed portion of the first electrode and the insulating film;
A metal layer forming step of forming a metal layer covering the pad electrode outside the separation groove;
A peeling step of peeling the growth substrate from the growth layer by a laser lift-off method to expose the growth layer,
In the insulating film forming step, the insulating film inside the separation groove and the insulating film outside the separation groove are formed apart from each other,
In the pad electrode formation step, the pad electrode inside the separation groove and the pad electrode outside the separation groove are formed apart from each other.   The method of manufacturing a semiconductor light emitting device according to claim 1, wherein the separation grooves are formed in a lattice shape and communicate with each other.   The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the separation groove communicates with the outside of the growth substrate.   4. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein a depth of the isolation trench is deeper than a total thickness of the insulating film and the pad electrode. 5.   5. The metal layer forming step according to claim 1, wherein in the metal layer forming step, a resist is formed on the pad electrode inside the separation groove, and the metal layer is formed on the resist. A method for manufacturing a semiconductor light emitting device.   6. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein in the separation step, a side surface of the growth layer is inclined by a predetermined angle from a bottom surface of the separation groove.   The method for manufacturing a semiconductor light-emitting element according to claim 1, further comprising a bonding step of bonding a support onto the metal layer after the metal layer forming step.

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