JP5281535B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Manufacturing method of semiconductor light emitting device Download PDF

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JP5281535B2
JP5281535B2 JP2009232623A JP2009232623A JP5281535B2 JP 5281535 B2 JP5281535 B2 JP 5281535B2 JP 2009232623 A JP2009232623 A JP 2009232623A JP 2009232623 A JP2009232623 A JP 2009232623A JP 5281535 B2 JP5281535 B2 JP 5281535B2
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semiconductor film
substrate
support substrate
semiconductor
emitting device
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JP2011082307A (en
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康之 柴田
吉鎬 梁
崇子 千野根
二郎 東野
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Stanley Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor light-emitting apparatus having a bonded structure of a supporting substrate and a semiconductor film, with higher yield compared with the conventional types. <P>SOLUTION: The semiconductor film is formed on a growing substrate by the vapor phase epitaxy method. An electrode layer is formed on the semiconductor film. A support substrate for supporting the semiconductor film is prepared. A recess part deeper than a height of a convex part is formed on a region, which is on a surface of the support substrate and which includes a part, corresponding to the convex part generated at an edge part of the semiconductor film, when the semiconductor film and a supporting substrate are jointed. A junction layer is formed on a surface on a side jointed to the semiconductor film of the supporting substrate. Positioning is carried out so that the edge part of the semiconductor film and the recess part mutually overlap to joint the semiconductor film and the supporting substrate via the junction layer and the electrode layer. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、半導体発光装置に関し、特に、半導体膜の成膜に用いられる成長用基板とは別の支持基板によって半導体膜が支持されるいわゆる貼り合わせ構造を有する発光ダイオード(LED:Light Emitting Diode、以下LEDと称する)の製造方法に関する。   The present invention relates to a semiconductor light emitting device, and in particular, a light emitting diode (LED) having a so-called bonded structure in which a semiconductor film is supported by a support substrate different from a growth substrate used for forming a semiconductor film. (Hereinafter referred to as LED).

従来技術Conventional technology

LEDは、有機金属化学気相成長法(MOCVD法:Metal Organic Chemical Vapor Deposition)等を用いてサファイア基板等の成長用基板の上にGaN系半導体膜等をエピタキシャル成長させることにより製造される。MOCVD法は、有機金属材料蒸気と水素化物ガスを、加熱した成長用基板上に吹き付け、熱分解させて半導体結晶を得る方法である。例えばInGaNからなる半導体膜を形成する場合には、液体トリメチルガリウム(TMGa)と、固体トリメチルインジウム(TMIn)より材料蒸気を取り出し、これとアンモニア(NH)ガスとを混合して、約800℃に加熱したサファイア基板上に吹き付ける。すると、材料ガスはサファイア基板上で熱分解反応を起こし、メタンガスなどを遊離しながらInGaN結晶を生成する。 An LED is manufactured by epitaxially growing a GaN-based semiconductor film or the like on a growth substrate such as a sapphire substrate using a metal organic chemical vapor deposition (MOCVD) method or the like. The MOCVD method is a method for obtaining a semiconductor crystal by spraying an organic metal material vapor and a hydride gas onto a heated growth substrate and thermally decomposing the vapor. For example, in the case of forming a semiconductor film made of InGaN, a material vapor is taken out from liquid trimethylgallium (TMGa) and solid trimethylindium (TMIn), and this is mixed with ammonia (NH 3 ) gas. Spray onto a heated sapphire substrate. Then, the material gas undergoes a thermal decomposition reaction on the sapphire substrate, and an InGaN crystal is generated while releasing methane gas and the like.

しかしながら、成長用基板上にMOCVD法等の気相成長法によって半導体膜を形成する場合、成長用基板のエッジ近傍で原料ガスの流れに乱れが生じ、この部分で異常成長が起りやすい。その結果、成長用基板のエッジ近傍において半導体膜が他の部分よりも突出した凸部が形成されることとなる。例えば半導体膜の膜厚が6μmである場合、この凸部の高さは12〜18μmに達する場合もある。半導体膜のエッジ部にこのような凸部が形成されると、その後に行われるフォトリソグラフィ工程においてフォトマスクと非処理基板との密着性が悪化して、半導体膜のパターニング不良を招来する。   However, when a semiconductor film is formed on the growth substrate by a vapor deposition method such as MOCVD, the flow of the source gas is disturbed near the edge of the growth substrate, and abnormal growth is likely to occur in this portion. As a result, a convex portion is formed in which the semiconductor film protrudes from other portions in the vicinity of the edge of the growth substrate. For example, when the thickness of the semiconductor film is 6 μm, the height of the convex portion may reach 12 to 18 μm. When such a convex portion is formed at the edge portion of the semiconductor film, the adhesion between the photomask and the non-processed substrate is deteriorated in the subsequent photolithography process, which leads to poor patterning of the semiconductor film.

特許文献1および特許文献2には、サファイア基板のエッジ部に曲面加工又はテーパ加工を施して、予め異常成長が起こり易いサファイア基板のエッジ部の表面の高さを低くしておくことにより凸部の発生を防止して、半導体膜の表面を平坦にすることができる旨が記載されている。   In Patent Document 1 and Patent Document 2, a convex portion is obtained by subjecting the edge portion of the sapphire substrate to curved surface processing or taper processing, and reducing the height of the surface of the edge portion of the sapphire substrate in which abnormal growth is likely to occur in advance. It is described that the surface of the semiconductor film can be flattened by preventing the occurrence of.

特開2000−331940号公報JP 2000-331940 A 特開2006−147891号公報JP 2006-147891 A

半導体膜をサファイア基板とは別のシリコン基板や金属基板等の支持基板で支持するLED構造が知られている。このような構造のLEDは、サファイア基板上に半導体膜を成長させた後、支持基板と半導体膜を接合層を介して貼り合せ、サファイア基板をレーザリフトオフ法(LLO法)等で除去することによって得ることができる。かかる構造によれば、支持基板の材料の選択によって、LEDの熱伝導率や光取り出し効率の向上を図ることも可能であり、また、支持基板を導電層として利用することも可能である。   There is known an LED structure in which a semiconductor film is supported by a support substrate such as a silicon substrate or a metal substrate different from the sapphire substrate. In an LED having such a structure, after a semiconductor film is grown on a sapphire substrate, the support substrate and the semiconductor film are bonded through a bonding layer, and the sapphire substrate is removed by a laser lift-off method (LLO method) or the like. Can be obtained. According to this structure, it is possible to improve the thermal conductivity and light extraction efficiency of the LED by selecting the material of the support substrate, and it is also possible to use the support substrate as a conductive layer.

このような、貼り合せ構造を有するLEDにおいて、半導体膜のエッジ部に上記したような凸部が発生すると、図1に示すように、半導体膜1のエッジ部において半導体膜1と支持基板2の未接合領域が生じる。未接合領域を有したままサファイア基板3の剥離を行うと、未接合領域における半導体膜は脱落してしまうため、LEDチップとして使用することができない。半導体膜1と支持基板2との未接合領域の幅Aは、5mm程度にまで及ぶ場合もあり、LEDチップの歩留りを著しく低下させる要因となっていた。   In such an LED having a bonded structure, when the above-described convex portion occurs at the edge portion of the semiconductor film, the semiconductor film 1 and the support substrate 2 are formed at the edge portion of the semiconductor film 1 as shown in FIG. An unjoined region is generated. If the sapphire substrate 3 is peeled while having an unbonded region, the semiconductor film in the unbonded region falls off and cannot be used as an LED chip. The width A of the unbonded region between the semiconductor film 1 and the support substrate 2 sometimes reaches about 5 mm, which is a factor that significantly reduces the yield of LED chips.

特許文献1および特許文献2の如く、サファイア基板のエッジ部にR加工等を施すことにより半導体膜の平坦性を確保することが可能となり、かかる手法を支持基板と貼り合わせる構成のLEDに適用しても一定の効果が期待できる。しかしながら、R加工を施したサファイア基板の表面は、半導体膜の成長に適した結晶面から離れるため、この部分に形成される半導体膜の膜質が変化し、これにより発光特性が変化してしまうおそれがある。すなわち、サファイア基板のR加工を施した領域上に形成される半導体膜は、通常LEDとして使用することができない。サファイア基板のR加工は機械的研磨によって行われるため、加工精度に限界があり、LEDチップとして使用できない領域は半導体膜のエッジから数百μmに及ぶ。このように、サファイア基板のエッジ部にR加工を施す手法によってもなおLEDチップとして使用できない領域が広範囲に及び、歩留り改善効果は限定的である。   As in Patent Document 1 and Patent Document 2, it is possible to ensure the flatness of the semiconductor film by performing R processing or the like on the edge portion of the sapphire substrate, and this method is applied to an LED having a structure in which the semiconductor substrate is bonded to the support substrate. However, a certain effect can be expected. However, since the surface of the sapphire substrate subjected to R processing is separated from the crystal plane suitable for the growth of the semiconductor film, the film quality of the semiconductor film formed in this portion may change, which may change the light emission characteristics. There is. That is, the semiconductor film formed on the R-processed region of the sapphire substrate cannot usually be used as an LED. Since the R processing of the sapphire substrate is performed by mechanical polishing, the processing accuracy is limited, and the region that cannot be used as the LED chip extends to several hundred μm from the edge of the semiconductor film. As described above, the area that cannot be used as the LED chip even by the technique of performing the R processing on the edge portion of the sapphire substrate covers a wide range, and the yield improvement effect is limited.

本発明は上記した点に鑑みてなされたものであり、支持基板と半導体膜との貼り合せ構造を有する半導体発光装置を従来よりも高い歩留りで製造することができる半導体発光装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above points, and provides a method for manufacturing a semiconductor light-emitting device capable of manufacturing a semiconductor light-emitting device having a bonded structure of a support substrate and a semiconductor film at a higher yield than before. The purpose is to do.

本発明の半導体発光装置の製造方法は、成長用基板の上に気相成長法によって半導体膜を形成する工程と、前記半導体膜の上に電極層を形成する工程と、前記半導体膜を支持するための支持基板を用意する工程と、前記支持基板の表面であって、前記半導体膜と前記支持基板とを接合したときに前記半導体膜のエッジ部に生じる凸部に対応する部分を含む領域に前記凸部の高さよりも深い凹部を形成する工程と、前記支持基板の前記半導体膜と接合させる側の表面に接合層を形成する工程と、前記半導体膜のエッジ部と前記凹部が重なるように位置合わせして前記接合層および前記電極層を介して前記半導体膜と前記支持基板とを接合する工程と、を含むことを特徴としている。   The method for manufacturing a semiconductor light emitting device according to the present invention includes a step of forming a semiconductor film on a growth substrate by a vapor deposition method, a step of forming an electrode layer on the semiconductor film, and supporting the semiconductor film. And a region including a portion corresponding to a convex portion generated at an edge portion of the semiconductor film when the semiconductor film and the support substrate are bonded to each other. A step of forming a concave portion deeper than the height of the convex portion, a step of forming a bonding layer on a surface of the support substrate to be bonded to the semiconductor film, and an edge portion of the semiconductor film and the concave portion so as to overlap each other. And a step of aligning and bonding the semiconductor film and the support substrate through the bonding layer and the electrode layer.

本発明に係る半導体発光装置によれば、半導体膜のエッジ部に凸部が生じている場合であっても、支持基板と半導体膜とを貼り合せたときに、支持基板に形成された凹部に半導体膜の凸部が収まることとなるで、半導体膜のエッジ部において支持基板に接合されない未接合領域の発生を防止することができる。これにより、LEDチップの歩留りを向上させることができる。   According to the semiconductor light emitting device of the present invention, even when the convex portion is generated at the edge portion of the semiconductor film, when the support substrate and the semiconductor film are bonded to each other, the concave portion formed in the support substrate is formed. Since the convex portions of the semiconductor film are accommodated, it is possible to prevent the occurrence of an unjoined region that is not joined to the support substrate at the edge portion of the semiconductor film. Thereby, the yield of LED chips can be improved.

エッジ部に凸部が形成された半導体膜と支持基板とを貼り合せたときの状態を示す断面図であるIt is sectional drawing which shows a state when the semiconductor film in which the convex part was formed in the edge part, and a support substrate are bonded together (a)〜(c)は、本発明の実施例に係る半導体発光装置の製造方法を示す断面図である。(A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device based on the Example of this invention. (d)〜(g)は、本発明の実施例に係る半導体発光装置の製造方法を示す断面図である。(D)-(g) is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device based on the Example of this invention. (h)〜(j)は、本発明の実施例に係る半導体発光装置の製造方法を示す断面図である。(H)-(j) is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device based on the Example of this invention. 本発明の実施例である半導体発光装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor light-emitting device which is an Example of this invention. 本発明の他の実施例である半導体発光装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor light-emitting device which is another Example of this invention.

以下、本発明の実施例について図面を参照しつつ説明する。尚、以下に示す図において、実質的に同一又は等価な構成要素、部分には同一の参照符を付している。   Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals.

図2(a)〜(c)、図3(d)〜(g)、図4(h)〜(j)は、本発明の実施例に係る半導体発光装置の製造方法を示す断面図である。本実施例に係る半導体発光装置は、半導体膜の成長に使用する成長用基板とは別に用意された支持基板によって半導体膜の支持を行う構成を有するものである。   2A to 2C, 3D to 3G, and 4H to 4J are cross-sectional views illustrating a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention. . The semiconductor light emitting device according to this example has a configuration in which a semiconductor film is supported by a support substrate prepared separately from a growth substrate used for growing a semiconductor film.

はじめに、半導体膜の成長用基板として使用する2インチサファイア基板20を用意する。尚、サファイア基板20のエッジ部は、R加工や面取り加工が施されていない(図1(a)。   First, a 2-inch sapphire substrate 20 used as a semiconductor film growth substrate is prepared. Note that the edge portion of the sapphire substrate 20 is not subjected to R processing or chamfering processing (FIG. 1A).

次に、サファイア基板20のサーマルクリーニングを行った後、サファイア基板20上にMOCVD法によりバッファー層、下地GaN層、n-GaN層、活性層、p型AlGaNクラッド層、p−GaN層を順次成膜して構成される半導体膜21を形成する。   Next, after the sapphire substrate 20 is thermally cleaned, a buffer layer, a base GaN layer, an n-GaN layer, an active layer, a p-type AlGaN cladding layer, and a p-GaN layer are sequentially formed on the sapphire substrate 20 by MOCVD. A semiconductor film 21 configured as a film is formed.

具体的には、雰囲気温度を500℃とし、TMG(トリメチルガリウム)(流量10.4μmol/min)およびNH(流量3.3LM)を約3分間供給してGaN層からなるバッファー層を形成する。その後、雰囲気温度を1000℃まで昇温し、約30秒間保持することでバッファー層を結晶化させる。続いて、雰囲気温度を1000℃に保持したままTMG(流量45μmol/min)およびNH(流量4.4LM)を約20分間供給し、膜厚1μm程度の下地GaN層を形成する。次に、雰囲気温度1000℃にてTMG(流量45μmol/min)、NH(流量4.4LM)およびドーパントガスとしてSiH(流量2.7×10-9mol/min)を約40分間供給し、膜厚4μm程度のn-GaN層を形成する。続いて、n−GaN層の上に活性層を形成する。本実施例では、活性層には、InGaN/GaNからなる多重量子井戸構造を適用した。すなわち、InGaN/GaNを1周期として5周期成長を行う。具体的には、雰囲気温度700℃にてTMG(流量3.6μmol/min)、TMI(トリメチルインジウム)(流量10μmol/min)、NH(流量4.4LM)を約33秒間供給し、膜厚約2.2nmのInGaN井戸層を形成し、続いてTMG(流量3.6μmol/min)、NH(流量4.4LM)を約320秒間供給して膜厚約15nmのGaN障壁層を形成する。かかる処理を5周期分繰り返すことにより活性層が形成される。次に、雰囲気温度を870℃まで昇温し、TMG(流量8.1μmol/min)、TMA(トリメチルアルミニウム)(流量7.5μmol/min)、NH(流量4.4LM)およびドーパントとしてCP2Mg(bis-cyclopentadienyl Mg)(流量2.9×10-7μmol/min)を約5分間供給し、膜厚約40nmのp型AlGaNクラッド層を形成する。続いて、雰囲気温度を保持したまま、TMG(流量18μmol/min)、NH(流量4.4LM)およびドーパントとしてCP2Mg(流量2.9×10-7μmol/min)を約7分間供給し、膜厚約150nmのp−GaN層を形成する。サファイア基板20上には、これらの各層によって構成される膜厚約6μmの半導体膜21が形成される。サファイア基板20のエッジ部には、成膜時における原料ガスの流れの乱れに起因して、高さ10μm程度の凸部21aが生じることとなる(図2(b))。 Specifically, the atmosphere temperature is set to 500 ° C., TMG (trimethyl gallium) (flow rate 10.4 μmol / min) and NH 3 (flow rate 3.3 LM) are supplied for about 3 minutes to form a buffer layer made of a GaN layer. Thereafter, the temperature of the atmosphere is raised to 1000 ° C. and held for about 30 seconds to crystallize the buffer layer. Subsequently, TMG (flow rate: 45 μmol / min) and NH 3 (flow rate: 4.4 LM) are supplied for about 20 minutes while maintaining the atmospheric temperature at 1000 ° C., and a base GaN layer having a thickness of about 1 μm is formed. Next, TMG (flow rate 45 μmol / min), NH 3 (flow rate 4.4 LM) and SiH 4 (flow rate 2.7 × 10 −9 mol / min) as a dopant gas are supplied for about 40 minutes at an ambient temperature of 1000 ° C. An n-GaN layer of about 4 μm is formed. Subsequently, an active layer is formed on the n-GaN layer. In this example, a multiple quantum well structure made of InGaN / GaN was applied to the active layer. That is, five cycles of growth are performed with InGaN / GaN as one cycle. Specifically, TMG (flow rate 3.6 μmol / min), TMI (trimethylindium) (flow rate 10 μmol / min), NH 3 (flow rate 4.4 LM) are supplied for about 33 seconds at an atmospheric temperature of 700 ° C., and the film thickness is about 2 A 2 nm InGaN well layer is formed, and then TMG (flow rate 3.6 μmol / min) and NH 3 (flow rate 4.4 LM) are supplied for about 320 seconds to form a GaN barrier layer having a thickness of about 15 nm. An active layer is formed by repeating this process for five cycles. Next, the ambient temperature was raised to 870 ° C., TMG (flow rate 8.1 μmol / min), TMA (trimethylaluminum) (flow rate 7.5 μmol / min), NH 3 (flow rate 4.4 LM) and CP2Mg (bis-cyclopentadienyl as a dopant). Mg) (flow rate: 2.9 × 10 −7 μmol / min) is supplied for about 5 minutes to form a p-type AlGaN cladding layer having a thickness of about 40 nm. Subsequently, while maintaining the ambient temperature, TMG (flow rate 18 μmol / min), NH 3 (flow rate 4.4 LM) and CP2Mg (flow rate 2.9 × 10 −7 μmol / min) as a dopant were supplied for about 7 minutes, and the film thickness was about A 150 nm p-GaN layer is formed. On the sapphire substrate 20, a semiconductor film 21 having a film thickness of about 6 μm is formed. At the edge portion of the sapphire substrate 20, a convex portion 21a having a height of about 10 μm is generated due to the disturbance of the flow of the source gas during film formation (FIG. 2B).

次に、半導体膜21上にPt(1nm)/Ag(300nm)/Ti(100nm)/Pt(200nm)/Au(200nm)を順次スパッタ法などによって堆積することによりp電極層22を形成する(図2(c))
一方で、支持基板として使用するシリコン単結晶等からなる厚さ525μmの3インチシリコン基板10を用意する。そして、このシリコン基板10を熱酸化炉に投入し、酸素および水蒸気雰囲気で熱酸化処理を施して、シリコン基板10表面に膜厚1μm程度の二酸化シリコン(SiO)からなる酸化膜11を形成する(図3(d))。
Next, Pt (1 nm) / Ag (300 nm) / Ti (100 nm) / Pt (200 nm) / Au (200 nm) are sequentially deposited on the semiconductor film 21 by a sputtering method or the like to form the p electrode layer 22 (see FIG. FIG. 2 (c))
On the other hand, a 3-inch silicon substrate 10 having a thickness of 525 μm made of a silicon single crystal or the like used as a support substrate is prepared. Then, this silicon substrate 10 is put into a thermal oxidation furnace and subjected to thermal oxidation treatment in an oxygen and water vapor atmosphere to form an oxide film 11 made of silicon dioxide (SiO 2 ) having a thickness of about 1 μm on the surface of the silicon substrate 10. (FIG. 3 (d)).

次に、酸化膜11上にレジストマスク12を形成する。レジストマスク12は、半導体膜21と支持基板であるシリコン基板10とを貼り合せたときに半導体膜21のエッジ部に形成された凸部21aに対向する部分を含む領域に開口部12aを有する。具体的には、開口12aは、内径Rが2インチサファイア基板20よりも約15μm小さい円の周囲に、開口幅Lが約30μmの円環状をなしている。開口部21aは、フォトリソグラフィ等の微細加工技術を用いて形成することができるので、高い精度のレジストマスクを形成することができる(図3(e))。尚、支持基板として用いられるシリコン基板10の径は、半導体膜と支持基板を貼り合せた後の各工程におけるハンドリング性を考慮してサファイア基板20よりも大きいことが好ましい。   Next, a resist mask 12 is formed on the oxide film 11. The resist mask 12 has an opening 12a in a region including a portion facing the convex portion 21a formed on the edge portion of the semiconductor film 21 when the semiconductor film 21 and the silicon substrate 10 as a supporting substrate are bonded to each other. Specifically, the opening 12a has an annular shape with an opening width L of about 30 μm around a circle whose inner diameter R is about 15 μm smaller than the 2-inch sapphire substrate 20. Since the opening 21a can be formed using a fine processing technique such as photolithography, a highly accurate resist mask can be formed (FIG. 3E). In addition, it is preferable that the diameter of the silicon substrate 10 used as the support substrate is larger than that of the sapphire substrate 20 in consideration of handling properties in each process after the semiconductor film and the support substrate are bonded together.

次に、シリコン基板10をBHF(バッファードフッ酸)に浸漬し、レジストマスク12の開口部12aから露出した酸化膜11をエッチングする。これにより、酸化膜11にはレジストマスク12の開口パターンと同一のパターンを有する開口部11aが形成される。その後、レジストマスク12を除去する。次に、シリコン基板10を40重量パーセントの濃度を有する水酸化カリウム水溶液(KOH)浸漬する。これにより、酸化膜11の開口部11aにおいて露出したシリコン基板10をエッチングし、シリコン基板10の表面に幅約30μm、深さ約20μmの円環状の溝によって構成される凹部10aを形成する。凹部10aの深さは、サファイア基板20上に形成された半導体膜21の凸部21aの高さよりも深く形成されていればよい。凹部10aの深さは、酸化膜11の開口部11aの幅を変えることによって調整することが可能である。すなわち、凹部10aの深さを深くするためには、酸化膜の開口部11aの幅を広くすればよい。しかしながら、凹部10aの深さをあまり深くしすぎると、LEDチップの収率が低下することとなるので、凹部10aの深さは50μm以下であることが好ましい。尚、KOHを用いてSiをエッチングすると、所定の結晶面が現れる異方性エッチングとなり、凹部10aの断面形状は台形状(エッチングが進むと逆三角形状)となる(図3(f))。   Next, the silicon substrate 10 is immersed in BHF (buffered hydrofluoric acid), and the oxide film 11 exposed from the opening 12a of the resist mask 12 is etched. As a result, an opening 11 a having the same pattern as the opening pattern of the resist mask 12 is formed in the oxide film 11. Thereafter, the resist mask 12 is removed. Next, the silicon substrate 10 is immersed in a potassium hydroxide aqueous solution (KOH) having a concentration of 40 weight percent. As a result, the silicon substrate 10 exposed in the opening 11a of the oxide film 11 is etched, and a recess 10a constituted by an annular groove having a width of about 30 μm and a depth of about 20 μm is formed on the surface of the silicon substrate 10. The depth of the concave portion 10 a only needs to be deeper than the height of the convex portion 21 a of the semiconductor film 21 formed on the sapphire substrate 20. The depth of the recess 10 a can be adjusted by changing the width of the opening 11 a of the oxide film 11. That is, in order to increase the depth of the recess 10a, the width of the opening 11a of the oxide film may be increased. However, if the depth of the recess 10a is made too deep, the yield of the LED chip will be reduced. Therefore, the depth of the recess 10a is preferably 50 μm or less. When Si is etched using KOH, anisotropic etching appears where a predetermined crystal plane appears, and the cross-sectional shape of the recess 10a becomes trapezoidal (inverted triangular shape as etching progresses) (FIG. 3 (f)).

次に、シリコン基板10を再度BHF(バッファードフッ酸)に浸漬し、酸化膜11を除去する(図3(g))。   Next, the silicon substrate 10 is again immersed in BHF (buffered hydrofluoric acid), and the oxide film 11 is removed (FIG. 3G).

次に、蒸着法などにより、シリコン基板10の凹部10aが形成されている側の表面にPt、Ti、Ni、Au、Pt、AuSuを順次成膜することにより、共晶材を含む電極層13を形成する(図4(h))。この電極層13は、半導体膜21とシリコン基板10とを貼り合わせる際の接合層として機能する。   Next, Pt, Ti, Ni, Au, Pt, and AuSu are sequentially formed on the surface of the silicon substrate 10 on which the concave portion 10a is formed by vapor deposition or the like, whereby the electrode layer 13 containing a eutectic material is formed. Is formed (FIG. 4H). The electrode layer 13 functions as a bonding layer when the semiconductor film 21 and the silicon substrate 10 are bonded together.

次に、上記各処理を施して作製されたシリコン基板10と、先の工程でサファイア基板20上に形成した半導体膜21とを貼り合わせる。このとき、半導体膜21のエッジ部とシリコン基板10に形成された凹部10aとが重なるように位置合わせを行う。すなわち、半導体膜の凸部21aがシリコン基板10の凹部10a内に収まるように位置合わせする。そして、p電極層22と共晶材を含む電極層13とが対向した状態で半導体膜21とシリコン基板10とを密着させ、窒素雰囲気下で熱圧着する。シリコン基板10上の電極層13に含まれる共晶材の溶融および固化によって半導体膜21とシリコン基板10とが接合される(図4(i))。このように、シリコン基板10の表面には、半導体膜21を当接したときに半導体膜21のエッジ部に形成された凸部21aを収容し得る凹部10aが形成されているので、エッジ部においても半導体膜21とシリコン基板10との密着性が確保され、図1に示したようなエッジ部における未接合領域の発生を防止することができる。   Next, the silicon substrate 10 manufactured by performing each of the above processes and the semiconductor film 21 formed on the sapphire substrate 20 in the previous step are bonded together. At this time, alignment is performed so that the edge portion of the semiconductor film 21 and the concave portion 10a formed in the silicon substrate 10 overlap. That is, the alignment is performed so that the convex portion 21 a of the semiconductor film is accommodated in the concave portion 10 a of the silicon substrate 10. Then, the semiconductor film 21 and the silicon substrate 10 are brought into close contact with the p electrode layer 22 and the electrode layer 13 containing a eutectic material facing each other, and thermocompression-bonded in a nitrogen atmosphere. The semiconductor film 21 and the silicon substrate 10 are joined by melting and solidifying the eutectic material contained in the electrode layer 13 on the silicon substrate 10 (FIG. 4I). As described above, the surface of the silicon substrate 10 is formed with the concave portion 10a that can accommodate the convex portion 21a formed on the edge portion of the semiconductor film 21 when the semiconductor film 21 abuts. Also, the adhesion between the semiconductor film 21 and the silicon substrate 10 is ensured, and the occurrence of an unbonded region at the edge portion as shown in FIG. 1 can be prevented.

次に、サファイア基板20を半導体膜21から剥離する。サファイア基板20の剥離には、LLO(レーザリフトオフ)法等の公知の手法を用いることができる。LLO法においては、照射されたレーザがサファイア基板20上に形成されているGaN層を金属GaとNガスに分解する。このため、半導体膜内のn−GaN層又は下地GaN層内で上記分解が起り、サファイア基板20を剥離した面には、n-GaN層又は下地GaN層が表出する(図4(j))。 Next, the sapphire substrate 20 is peeled from the semiconductor film 21. For peeling off the sapphire substrate 20, a known method such as an LLO (laser lift-off) method can be used. In the LLO method, the irradiated laser decomposes the GaN layer formed on the sapphire substrate 20 into metal Ga and N 2 gas. For this reason, the decomposition occurs in the n-GaN layer or the underlying GaN layer in the semiconductor film, and the n-GaN layer or the underlying GaN layer appears on the surface from which the sapphire substrate 20 is peeled off (FIG. 4J). ).

次に、サファイア基板20を剥離することによって表出した半導体膜21の表面にエッチングを施して表面を平坦化させた後、リフトオフ法などによってTiAl等からなるn電極を形成する。その後、ダイシング工程において、LEDチップを個片化する。以上の各工程を経て半導体発光装置が完成する。   Next, the surface of the semiconductor film 21 exposed by peeling the sapphire substrate 20 is etched to flatten the surface, and then an n-electrode made of TiAl or the like is formed by a lift-off method or the like. Thereafter, the LED chips are separated into individual pieces in the dicing process. The semiconductor light emitting device is completed through the above steps.

以上の説明から明らかなように、本発明に係る半導体発光装置の製造方法によれば、半導体膜21のエッジ部に凸部21aが生じている場合であっても、支持基板10と半導体膜21を貼り合せたときに、支持基板10に形成された凹部10aに半導体膜の凸部21aが収まることとなるで、半導体膜21のエッジ部において、支持基板10に接合されない未接合領域の発生を防止することができる。これにより、図5に示すように、半導体膜21のエッジから内側20〜30μmまで使用可能となり、LEDチップの歩留りを向上させることができる。支持基板10に設けられる凹部10aは既存のフォトリソグラフィ等の微細加工技術を適用して形成することができるので、サファイア基板に曲面加工やテーパ加工などの面取り加工を施す手法に比べ、半導体膜の使用可能領域を更に拡大することができ、更なる歩留り改善を図ることが可能となる。   As is clear from the above description, according to the method for manufacturing a semiconductor light emitting device according to the present invention, even when the convex portion 21 a is generated at the edge portion of the semiconductor film 21, the support substrate 10 and the semiconductor film 21. When the substrate is bonded, the convex portion 21a of the semiconductor film is accommodated in the concave portion 10a formed in the support substrate 10, so that an unbonded region that is not bonded to the support substrate 10 is generated at the edge portion of the semiconductor film 21. Can be prevented. Thereby, as shown in FIG. 5, it becomes possible to use from the edge of the semiconductor film 21 to the inner side of 20 to 30 μm, and the yield of the LED chip can be improved. Since the concave portion 10a provided in the support substrate 10 can be formed by applying an existing micromachining technique such as photolithography, the semiconductor film is formed in comparison with a method of performing chamfering such as curved surface processing or taper processing on the sapphire substrate. The usable area can be further expanded, and the yield can be further improved.

尚、上記した実施例においては、KOHを用いてシリコン基板をエッチングすることにより凹部を形成することとしたが、これに限定されず、例えばRIEなどのドライエッチングによって凹部を形成することとしてもよい。   In the above-described embodiment, the concave portion is formed by etching the silicon substrate using KOH. However, the present invention is not limited to this, and the concave portion may be formed by dry etching such as RIE. .

また、支持基板に形成される凹部の形態は、上記したような溝状に限らず、図6に示すように、半導体膜のエッジ部に対応する部分から外側の領域を全てエッチングすることにより得られる切り欠き状であってもよい。   In addition, the shape of the recess formed in the support substrate is not limited to the groove shape as described above, and can be obtained by etching all regions outside the portion corresponding to the edge portion of the semiconductor film as shown in FIG. It may be a notch shape.

また、支持基板はシリコン基板に限らず、Ge基板やGaAs基板、Cu等からなる金属基板等であってもよい。また、成長用基板は、サファイア基板に限らず、GaN基板やSiC基板であってもよい。   The support substrate is not limited to a silicon substrate, but may be a Ge substrate, a GaAs substrate, a metal substrate made of Cu, or the like. Further, the growth substrate is not limited to the sapphire substrate, but may be a GaN substrate or a SiC substrate.

10 シリコン基板
10a 凹部
11 酸化膜
20 サファイア基板
21 半導体膜
21a 凸部
DESCRIPTION OF SYMBOLS 10 Silicon substrate 10a Concave part 11 Oxide film 20 Sapphire substrate 21 Semiconductor film 21a Convex part

Claims (3)

成長用基板の上に気相成長法によって半導体膜を形成する工程と、
前記半導体膜の上に電極層を形成する工程と、
前記半導体膜を支持するための支持基板を用意する工程と、
前記支持基板の表面であって、前記半導体膜と前記支持基板とを接合したときに前記半導体膜のエッジ部に生じる凸部に対応する部分を含む領域に前記凸部の高さよりも深い凹部を形成する工程と、
前記支持基板の前記半導体膜と接合させる側の表面に接合層を形成する工程と、
前記半導体膜のエッジ部と前記凹部が重なるように位置合わせして前記接合層および前記電極層を介して前記半導体膜と前記支持基板とを接合する工程と、を含むことを特徴とする半導体発光装置の製造方法。
Forming a semiconductor film on the growth substrate by vapor deposition;
Forming an electrode layer on the semiconductor film;
Preparing a support substrate for supporting the semiconductor film;
A concave portion deeper than the height of the convex portion is formed on a surface of the support substrate, including a portion corresponding to the convex portion generated at the edge portion of the semiconductor film when the semiconductor film and the support substrate are bonded. Forming, and
Forming a bonding layer on the surface of the support substrate to be bonded to the semiconductor film;
Aligning the edge portion of the semiconductor film with the concave portion and joining the semiconductor film and the support substrate through the bonding layer and the electrode layer. Device manufacturing method.
前記成長用基板を除去する工程を更に含むことを特徴とする請求項1に記載の半導体発光装置の製造方法。   The method of manufacturing a semiconductor light emitting device according to claim 1, further comprising a step of removing the growth substrate. 前記凹部は円環状の溝からなることを特徴とする請求項1又は2に記載の半導体発光装置の製造方法。   The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the concave portion is formed of an annular groove.
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