JP2013183063A - 半導体装置の製造方法及びコンピュータ記録媒体 - Google Patents
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Abstract
【解決手段】第1の膜と第2の膜とが交互に積層された多層膜と、フォトレジスト層とを有する基板をエッチングして、階段状の構造を形成する半導体装置の製造方法であって、フォトレジスト層をマスクとして第1の膜をプラズマエッチングする第1工程と、少なくともシリコン製部材を含む上部電極と、下部電極とを具備したプラズマ処理装置を使用し、上部電極に負の直流電圧を印加した状態で、アルゴンガスと水素ガスとを含む処理ガスを下部電極に印加する高周波電力によってプラズマ化し、当該プラズマに基板上に形成されたフォトレジスト層を晒す第2工程と、フォトレジスト層をトリミングする第3工程と、第3工程の後第2の膜をプラズマエッチングする第4工程とを繰り返して行う。
【選択図】図3
Description
図1は、実施形態に係る半導体装置の製造方法に用いるプラズマ処理装置の構成を示すものである。まず、プラズマ処理装置の構成について説明する。
(二酸化シリコン膜のエッチング)
処理ガス:C4F6/Ar/O2=15/750/35sccm
圧力:3.33Pa(25mTorr)
高周波電力(高い周波数の高周波/低い周波数の高周波):300W/300W
直流電圧:−150V
(フォトレジスト膜の改質)
処理ガス:H2/Ar=100/800sccm
圧力:6.65Pa(50mTorr)
高周波電力(高い周波数の高周波/低い周波数の高周波):300W/0W
直流電圧:−900V
(フォトレジスト膜のトリミング)
処理ガス:O2=1496sccm
圧力:106.4Pa(800mTorr)
高周波電力(高い周波数の高周波/低い周波数の高周波):2400W/0W
(窒化シリコン膜のエッチング)
処理ガス:CH2F2/Ar/O2=70/420/35sccm
圧力:6.65Pa(50mTorr)
高周波電力(高い周波数の高周波/低い周波数の高周波):400W/400W
直流電圧:−300V
(堆積物除去処理)
処理ガス:O2/CF4=150/350sccm
圧力:26.6Pa(200mTorr)
高周波電力(高い周波数の高周波/低い周波数の高周波):1500W/0W
Claims (7)
- 第1の誘電率を有する第1の膜と、前記第1の誘電率とは異なる第2の誘電率を有する第2の膜とが交互に積層された多層膜と、前記多層膜の上層に位置しエッチングマスクとして機能するフォトレジスト層とを有する基板をエッチングして、階段状の構造を形成する半導体装置の製造方法であって、
前記フォトレジスト層をマスクとして前記第1の膜をプラズマエッチングする第1工程と、
少なくともシリコン製部材を含む上部電極と、前記上部電極と対向して配設され、前記基板が載置される下部電極とを具備したプラズマ処理装置を使用し、前記上部電極に負の直流電圧を印加した状態で、アルゴンガスと水素ガスとを含む処理ガスを前記下部電極に印加する高周波電力によってプラズマ化し、当該プラズマに前記基板上に形成されたフォトレジスト層を晒す第2工程と、
前記第2工程の後、前記フォトレジスト層をトリミングする第3工程と、
前記第3工程によってトリミングした前記フォトレジスト層及び前記第1工程でプラズマエッチングした前記第1の膜をエッチングマスクとして前記第2の膜をプラズマエッチングする第4工程とを有し、
前記第1工程乃至前記第4工程を繰り返して行うことにより、前記多層膜を階段状の構造とすることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法であって、
前記第1工程と、前記第2工程との間に、前記フォトレジスト層に付着した堆積物を除去する堆積物除去工程を具備する
ことを特徴とする半導体装置の製造方法。 - 請求項1又は2記載の半導体装置の製造方法であって、
前記第2工程では、前記上部電極に−900V以上の負の直流電圧を印加する
ことを特徴とする半導体装置の製造方法。 - 請求項1〜3いずれか1項記載の半導体装置の製造方法であって、
前記第1の膜と前記第2の膜は、
二酸化シリコン膜とドープドポリシリコン膜、
二酸化シリコン膜と窒化シリコン膜、
ポリシリコン膜とドープドポリシリコン膜
のいずれかであることを特徴とする半導体装置の製造方法。 - 請求項1〜4いずれか1項記載の半導体装置の製造方法であって、
前記第1の膜と、前記第2の膜は、合計64層以上積層されている
ことを特徴とする半導体装置の製造方法。 - 基板上に形成されたフォトレジスト層をマスクとして当該フォトレジスト層の下層に形成された膜をプラズマエッチングする半導体装置の製造方法であって、
少なくともシリコン製部材を含む上部電極と、前記上部電極と対向して配設され基板が載置される下部電極とを具備したプラズマ処理装置を使用し、前記上部電極に負の直流電圧を印加した状態で、アルゴンガスと水素ガスとを含む処理ガスを前記下部電極に印加する高周波電力によってプラズマ化し、当該プラズマに前記フォトレジスト層を晒すフォトレジストの改質工程と、
前記フォトレジストの改質工程の後、前記フォトレジスト層を、トリミングするトリミング工程とを具備し、
前記トリミング工程における前記フォトレジスト層の高さ方向のトリミング量yと水平方向のトリミング量xとの比(y/x)が0.7以下である
ことを特徴とする半導体装置の製造方法。 - 被処理基板を収容する処理チャンバーと、
前記処理チャンバー内に処理ガスを供給する処理ガス供給機構と、
前記処理ガスのプラズマを発生させるプラズマ発生機構と
を具備したプラズマ処理装置を制御する制御プログラムが記録されたコンピュータ記録媒体であって、
前記制御プログラムは、請求項1〜6いずれか1項記載の半導体装置の製造方法が実行されるように前記プラズマ処理装置を制御する
ことを特徴とするコンピュータ記録媒体。
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US14/375,182 US9355861B2 (en) | 2012-03-02 | 2013-02-26 | Semiconductor device manufacturing method and computer-readable storage medium |
PCT/JP2013/001133 WO2013128900A1 (ja) | 2012-03-02 | 2013-02-26 | 半導体装置の製造方法及びコンピュータ記録媒体 |
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JP2019121750A (ja) * | 2018-01-11 | 2019-07-22 | 東京エレクトロン株式会社 | エッチング方法およびエッチング装置 |
KR20210096576A (ko) | 2020-01-28 | 2021-08-05 | 도쿄엘렉트론가부시키가이샤 | 에칭 방법 및 플라즈마 처리 장치 |
WO2023090168A1 (ja) * | 2021-11-19 | 2023-05-25 | 東京エレクトロン株式会社 | 窒化膜の成膜方法及びプラズマ処理装置 |
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JP6422262B2 (ja) * | 2013-10-24 | 2018-11-14 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
US9305839B2 (en) * | 2013-12-19 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Curing photo resist for improving etching selectivity |
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WO2023090168A1 (ja) * | 2021-11-19 | 2023-05-25 | 東京エレクトロン株式会社 | 窒化膜の成膜方法及びプラズマ処理装置 |
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JP5934523B2 (ja) | 2016-06-15 |
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