JP2013179103A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP2013179103A
JP2013179103A JP2012040832A JP2012040832A JP2013179103A JP 2013179103 A JP2013179103 A JP 2013179103A JP 2012040832 A JP2012040832 A JP 2012040832A JP 2012040832 A JP2012040832 A JP 2012040832A JP 2013179103 A JP2013179103 A JP 2013179103A
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semiconductor element
solder
temperature
holes
substrate
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Koyo Ono
公洋 小野
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/364—Polymers
    • H01L2924/3641—Outgassing

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which allows solder bonding to be performed in a short period of time without generating voids.SOLUTION: When bonding a semiconductor element 5 to an electrode 3 via solder 6, a plurality of through-holes 8 are formed in advance in a region on the electrode 3 to which the semiconductor element 5 is bonded. As an atmospheric condition for bonding by the solder 6, a semiconductor device manufacturing method includes: a temperature raising step of raising temperature to a level equal to or higher than a melting point of the solder 6 so as to melt the solder 6; a pressure raising step of increasing a bonding atmospheric pressure to a level higher than that during the temperature raising step, while keeping a molten state of the solder 6; and a temperature lowering step of lowering the bonding atmospheric temperature to a level equal to or lower than the melting point of the solder 6 so as to solidify the solder 6.

Description

本発明は半導体装置の製造方法に関し、特に基板に対して半導体素子を半田付け等でろう接（ろう付け）するようにした半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a semiconductor element is brazed to a substrate by soldering or the like.

例えば電気自動車やハイブリッド車等の電動車用インバータに搭載される半導体装置として、電極として機能する基板に対して半導体素子を半田接合したものがある。そして、半田層にボイド（空隙）が発生しているようなことがあると、半導体素子の駆動時の発熱によって破壊に至るおそれがあることから、このボイドの解消を目的とした半導体装置の製造方法として、減圧下で半田接合を行うようにしたいわゆる脱泡工法のほかに、特許文献１に記載されているように、半田の溶融前に減圧して半田溶融後に復圧または加圧するいわゆる圧縮工法が提案されている。   For example, as a semiconductor device mounted on an inverter for an electric vehicle such as an electric vehicle or a hybrid vehicle, there is one in which a semiconductor element is soldered to a substrate that functions as an electrode. If there is a void (void) in the solder layer, there is a risk of destruction due to heat generated when the semiconductor element is driven. Therefore, a semiconductor device is manufactured for the purpose of eliminating this void. As a method, in addition to the so-called defoaming method in which solder bonding is performed under reduced pressure, as described in Patent Document 1, the pressure is reduced before melting the solder and the pressure is restored or increased after the solder is melted. A construction method has been proposed.

より具体的には、上記特許文献１に記載された技術では、半導体素子とセラミック基板との間に半田を挟んだ状態で当該半田の固相線以下の温度にて減圧する一方、この減圧状態にて半田の液相線以上の温度まで加熱し、さらにこの加熱状態のままで上記減圧状態の圧力よりも高い圧力まで加圧した後、この加圧状態で半田を固化させるようにしている。   More specifically, in the technique described in Patent Document 1, the pressure is reduced at a temperature below the solidus of the solder while the solder is sandwiched between the semiconductor element and the ceramic substrate. Then, the solder is heated to a temperature higher than the liquidus of the solder, and further pressurized in this heated state to a pressure higher than the pressure in the decompressed state, and then the solder is solidified in this pressurized state.

特開２００５−２０５４１８号公報JP-A-2005-205418

しかしながら、特許文献１に代表されるような圧縮工法では、雰囲気圧力が半田層の内部のボイドにまで伝わりにくいことから、ボイドを低減または解消しようとすると、半田の溶融状態を維持しつつ且つ雰囲気圧力の高い状態を長時間維持する必要があり、半田接合に要する時間が長くなる。この傾向は、溶融した半田の粘性が高い場合には一段と顕著となる。   However, in the compression method represented by Patent Document 1, since the atmospheric pressure is difficult to be transmitted to the voids in the solder layer, when reducing or eliminating the voids, the molten state of the solder is maintained and the atmosphere is maintained. It is necessary to maintain a high pressure state for a long time, and the time required for solder joining becomes long. This tendency becomes more remarkable when the melted solder has a high viscosity.

本発明はこのような課題に着目してなされたものであり、特にボイドの発生のないろう接を短時間で行えるようにした半導体装置の製造方法を提供するものである。   The present invention has been made paying attention to such a problem, and in particular, provides a method for manufacturing a semiconductor device in which brazing without generation of voids can be performed in a short time.

本発明は、基板のうち半導体素子が接合される領域に予め貫通穴を形成しておく一方、半田等のろう材による接合雰囲気条件として、ろう材の融点以上の温度まで上昇させて当該ろう材を溶融させる昇温工程と、接合雰囲気圧力を上記昇温工程よりも増加させる昇圧工程と、上記接合雰囲気温度をろう材の融点以下の温度まで下降させて当該ろう材を固化させる降温工程と、を含むものとした。   In the present invention, a through hole is formed in advance in a region of a substrate to which a semiconductor element is bonded, and as a bonding atmosphere condition by a brazing material such as solder, the brazing material is raised to a temperature equal to or higher than the melting point of the brazing material. A temperature raising step for melting the solder, a pressure raising step for increasing the bonding atmosphere pressure more than the temperature raising step, a temperature lowering step for lowering the bonding atmosphere temperature to a temperature below the melting point of the brazing material and solidifying the brazing material, Included.

本発明によれば、基板のうち半導体素子が接合される領域に予め貫通穴が形成されているので、溶融したろう材層に含まれるボイドに対して雰囲気圧力が伝わりやすくなり、雰囲気圧力をもってボイドを押し潰すかたちで短時間のうちにそのボイドを低減または解消することができる。   According to the present invention, since a through hole is formed in advance in a region of the substrate to which the semiconductor element is bonded, the atmospheric pressure is easily transmitted to the void contained in the molten brazing material layer, and the void is maintained with the atmospheric pressure. The void can be reduced or eliminated in a short time by crushing.

本発明に係る半導体装置の製造方法が適用される半導体装置の一例を示す概略説明図。BRIEF DESCRIPTION OF THE DRAWINGS Schematic explanatory drawing which shows an example of the semiconductor device to which the manufacturing method of the semiconductor device which concerns on this invention is applied. 図１の要部拡大説明図。The principal part expansion explanatory view of FIG. 図２の縦断面拡大図。The longitudinal cross-sectional enlarged view of FIG. 半導体素子の駆動時の温度分布を示す説明図。Explanatory drawing which shows the temperature distribution at the time of the drive of a semiconductor element. 図３における貫通穴の具体的な配置例を示す説明図。Explanatory drawing which shows the specific example of arrangement | positioning of the through-hole in FIG. 図３における貫通穴の別の具体的な配置例を示す説明図。Explanatory drawing which shows another specific example of arrangement | positioning of the through-hole in FIG.

図１〜４は本発明に係る半導体装置の製造方法を実施するためのより具体的な形態を示し、特に図１は例えば電気自動車やハイブリッド車等の電動車用インバータに搭載される電力変換のための半導体装置の一例を示し、また図２は図１の要部拡大図を示している。   1 to 4 show a more specific form for carrying out the method for manufacturing a semiconductor device according to the present invention. In particular, FIG. 1 shows an example of power conversion mounted on an inverter for an electric vehicle such as an electric vehicle or a hybrid vehicle. FIG. 2 shows an enlarged view of the main part of FIG.

図１，２に示す半導体装置１は、略偏平箱状に成形された樹脂製のケース２に電極として機能する平板状の基板３と複数の端子４がそれぞれインサート成形等の手法により埋設されていて、基板３の上にパワー素子等の複数の半導体素子５がろう材層である半田層６にて接合（半田付け）されているとともに、各半導体素子５と端子４とが金線あるいはアルミニウム線等のリード線７にて接続されているものである。   In the semiconductor device 1 shown in FIGS. 1 and 2, a flat substrate 3 functioning as an electrode and a plurality of terminals 4 are embedded in a resin case 2 formed in a substantially flat box shape by a technique such as insert molding. A plurality of semiconductor elements 5 such as power elements are joined (soldered) on the substrate 3 by a solder layer 6 which is a brazing material layer, and each semiconductor element 5 and the terminal 4 are connected to a gold wire or aluminum. They are connected by lead wires 7 such as wires.

上記基板３に対してそれぞれの半導体素子５を半田接合するにあたっては、周知のように、基板３上の所定位置にペレット状またはシート状の半田６とともに半導体素子５を位置決めし、基板３と半導体素子５との間に半田６を挟んだ状態でケース２ごと所定の加熱炉に投入する。そして、加熱炉での雰囲気温度を半田６の融点以上の温度まで加熱・昇温させることでその半田６を溶融させ、その後に雰囲気温度を半田６の融点未満の温度まで下降させてその半田６を固化させることで基板３に対する半導体素子５の半田接合を行うものとする。   When soldering each semiconductor element 5 to the substrate 3, as is well known, the semiconductor element 5 is positioned together with the pellet-shaped or sheet-shaped solder 6 at a predetermined position on the substrate 3, and the substrate 3 and the semiconductor The case 2 is put into a predetermined heating furnace with the solder 6 sandwiched between the elements 5. Then, the solder 6 is melted by heating and raising the ambient temperature in the heating furnace to a temperature equal to or higher than the melting point of the solder 6, and then the ambient temperature is lowered to a temperature lower than the melting point of the solder 6. It is assumed that the semiconductor element 5 is soldered to the substrate 3 by solidifying.

この場合において、図３に示すように、基板３のうち半田６を介して半導体素子５が接合される領域に基板３自体の表裏両面に貫通するように予め複数の貫通穴８を形成しておくものとし、各貫通穴８の上部開口面を半田６に臨ませた状態で半田接合を行うものとする。   In this case, as shown in FIG. 3, a plurality of through holes 8 are formed in advance in the region of the substrate 3 where the semiconductor element 5 is bonded via the solder 6 so as to penetrate both the front and back surfaces of the substrate 3 itself. It is assumed that solder bonding is performed with the upper opening surface of each through hole 8 facing the solder 6.

基板３は先に述べたように電極として機能するものであるために、銅やアルミニウムなどの電気伝導率および熱伝導率に優れた金属材料にて形成されていて、溶融した半田６の濡れ性の改善のために例えばニッケルめっき等の表面処理が施されていることが望ましく、この基板３に対して半田接合にて半導体素子５が実装されることになる。そして、上記のようにニッケルめっき等の表面処理が施されている基板３に対して例えばプレスによるピアス加工を施すことで複数の貫通穴８が形成される。これにより、各貫通穴８の内周面には表面処理が施されておらず、基板３を形成している金属材料そのものの素地が露出していることになる。   Since the substrate 3 functions as an electrode as described above, the substrate 3 is formed of a metal material having excellent electrical conductivity and thermal conductivity such as copper and aluminum, and wettability of the molten solder 6. For example, surface treatment such as nickel plating is preferably performed, and the semiconductor element 5 is mounted on the substrate 3 by solder bonding. Then, a plurality of through holes 8 are formed by, for example, performing piercing with a press on the substrate 3 that has been subjected to surface treatment such as nickel plating as described above. As a result, the inner peripheral surface of each through hole 8 is not subjected to surface treatment, and the base material of the metal material itself forming the substrate 3 is exposed.

なお、各貫通穴８の大きさは溶融した半田６が漏れ出さないような大きさに設定される。また、各貫通穴８の配置の詳細については後述する。   In addition, the size of each through hole 8 is set to such a size that the molten solder 6 does not leak out. Details of the arrangement of the through holes 8 will be described later.

基板３に対して半導体素子５を半田接合する際の雰囲気条件として、先ず上記のように基板３と半導体素子５との間にペレット状またはシート状の半田６を挟んだ状態で接合雰囲気温度を半田６の融点以上の温度まで上昇させて当該半田６を溶融させるものとする。この工程は接合雰囲気温度の昇温工程に相当する。   As an atmosphere condition when the semiconductor element 5 is solder-bonded to the substrate 3, first, the bonding atmosphere temperature is set with the pellet-shaped or sheet-shaped solder 6 sandwiched between the substrate 3 and the semiconductor element 5 as described above. It is assumed that the solder 6 is melted by raising the temperature to a temperature equal to or higher than the melting point of the solder 6. This step corresponds to a step of raising the bonding atmosphere temperature.

そして、半田６が溶融したならば、接合雰囲気の圧力に着目して、その接合雰囲気圧力が上記昇温工程よりも高くなるようにその接合雰囲気圧力を増圧させる。例えば、上記昇温工程での圧力が大気圧であるならば、大気圧よりも高い圧力（正圧）となるように接合雰囲気圧力を高める。この工程ではなおも半田６の溶融状態が維持される。また、この工程は接合雰囲気圧力の昇圧工程に相当する。   When the solder 6 is melted, paying attention to the pressure of the bonding atmosphere, the bonding atmosphere pressure is increased so that the bonding atmosphere pressure becomes higher than the temperature raising step. For example, if the pressure in the temperature raising step is atmospheric pressure, the bonding atmosphere pressure is increased so that the pressure (positive pressure) is higher than atmospheric pressure. In this step, the molten state of the solder 6 is still maintained. This process corresponds to a step of increasing the bonding atmosphere pressure.

さらに、上記昇圧工程で増加させた接合雰囲気圧力を維持しながら、接合雰囲気温度を半田６の融点未満の温度まで下降させてその半田６を固化させるものとする。こうすることにより、半導体素子５は基板３上の所定位置に半田接合されることになる。この工程は接合雰囲気温度の降温工程に相当する。   Furthermore, it is assumed that the soldering atmosphere is solidified by lowering the bonding atmosphere temperature to a temperature lower than the melting point of the solder 6 while maintaining the bonding atmosphere pressure increased in the above-described boosting step. By doing so, the semiconductor element 5 is soldered to a predetermined position on the substrate 3. This process corresponds to a temperature lowering process of the bonding atmosphere temperature.

上記のように、接合雰囲気圧力の昇圧工程において、半田６の溶融状態を維持した状態で接合雰囲気圧力を昇圧させることにより、その雰囲気圧力が溶融している半田６に直ちに伝わり、いわゆる溶融状態の半田６の濡れ性が向上することで良好な半田接合を行うことができる。その上、図３に示すように仮に溶融した半田６の中にボイドＱが含まれていた場合に、複数の貫通穴８があることによって溶融状態の半田６に対して接合雰囲気圧力が伝わりやすく、短時間のうちにその半田６の中に含まれているボイドＱが接合雰囲気圧力にて押し潰されるようにして縮小または解消されることになる。   As described above, in the step of increasing the bonding atmosphere pressure, by increasing the bonding atmosphere pressure while maintaining the molten state of the solder 6, the atmospheric pressure is immediately transmitted to the molten solder 6, so-called molten state. As the wettability of the solder 6 is improved, good solder bonding can be performed. Moreover, as shown in FIG. 3, when the void Q is included in the molten solder 6, the bonding atmosphere pressure is easily transmitted to the molten solder 6 due to the presence of the plurality of through holes 8. In a short time, the void Q contained in the solder 6 is reduced or eliminated by being crushed by the bonding atmosphere pressure.

さらに、先に述べたように各貫通穴８の内周面にはニッケルめっき等の表面処理が施されておらず、基板３の金属材料そのものの素地が露出していて、ニッケルめっき等の表面処理が施されている基板３の表裏両面に比べていわゆる濡れ性は悪いものとなっている。そのため、溶融した半田６が各貫通穴８へと濡れ拡がるのを防ぎ、基板３と半導体素子５との間の半田６の層の厚さのばらつきを抑制することができる。   Further, as described above, the inner peripheral surface of each through hole 8 is not subjected to surface treatment such as nickel plating, and the base material of the metal material itself of the substrate 3 is exposed, and the surface of nickel plating or the like is exposed. So-called wettability is poor compared to the front and back sides of the substrate 3 that has been treated. Therefore, it is possible to prevent the melted solder 6 from spreading into the respective through holes 8 and to suppress variations in the thickness of the layer of the solder 6 between the substrate 3 and the semiconductor element 5.

ここで、基板３に対して半田接合された半導体素子５における実際の駆動時の発熱による温度特性を図４に示した。同図から明らかなように、半導体素子５の駆動時にはその半導体素子５の中心Ｃ付近が最も発熱しやすく、中心Ｃから離れるほど発熱が低下する傾向があり、その結果として半導体素子５の中心Ｃを基点とした半径Ｒの同心円上においてはほぼ同じ温度分布を示すことから、この点を考慮して図３に示した複数の貫通穴８の配置を決定するものとする。   Here, FIG. 4 shows temperature characteristics due to heat generation during actual driving in the semiconductor element 5 solder-bonded to the substrate 3. As can be seen from the figure, when the semiconductor element 5 is driven, the vicinity of the center C of the semiconductor element 5 is most likely to generate heat, and as the distance from the center C increases, the heat generation tends to decrease. As a result, the center C of the semiconductor element 5 is reduced. Since the same temperature distribution is shown on the concentric circle with the radius R from the base point, the arrangement of the plurality of through holes 8 shown in FIG. 3 is determined in consideration of this point.

この複数の貫通穴８のより具体的な配置としては、例えば図５に示すように、半導体素子５の中心Ｃに対して距離が遠くなるほど基板３の単位面積当たりの貫通穴８の断面積（開口面積）を増加させるべく、言い換えるならば、半導体素子５の中心Ｃに近い部分における貫通穴８の開口面積よりも半導体素子８の中心Ｃから遠い周縁部分における貫通穴８の開口面積を大きくなるようにするべく、複数の貫通穴８の形状および大きさを全て矩形の角穴状のもので統一した上で、半径Ｒ１の同心円上にある複数の貫通穴８の数よりも半径Ｒ１よりも大きな半径Ｒ２（Ｒ２＞Ｒ１）の同心円上にある複数の貫通穴８の数を多く設定してある。   As a more specific arrangement of the plurality of through holes 8, for example, as shown in FIG. 5, as the distance from the center C of the semiconductor element 5 increases, the cross-sectional area of the through holes 8 per unit area of the substrate 3 In other words, the opening area of the through hole 8 in the peripheral portion far from the center C of the semiconductor element 8 is larger than the opening area of the through hole 8 in the portion near the center C of the semiconductor element 5. In order to do so, the shape and size of the plurality of through holes 8 are all unified with a rectangular square hole shape, and more than the number of the plurality of through holes 8 on the concentric circle of the radius R1 than the radius R1. The number of the plurality of through-holes 8 on a concentric circle having a large radius R2 (R2> R1) is set.

なお、半径Ｒ１同心円上にある複数の貫通穴８は等ピッチにて配置されていて、同様に半径Ｒ２の同心円上にある複数の貫通穴８も等ピッチにて配置されている。また、当然のことながら、複数の貫通穴８の大きさや数の選定にあたっては、半導体素子５が耐熱温度以上まで昇温することがないように予め実験や熱解析を行った上で決定するものとする。   The plurality of through holes 8 on the concentric circle with the radius R1 are arranged at an equal pitch, and similarly, the plurality of through holes 8 on the concentric circle with the radius R2 are arranged at an equal pitch. Of course, when selecting the size and number of the plurality of through-holes 8, it is determined after conducting experiments and thermal analysis in advance so that the temperature of the semiconductor element 5 does not rise above the heat-resistant temperature. And

こうすることにより、図４に基づいて先に説明したように、半導体素子５の実際の駆動時にその半導体素子５の中心Ｃ付近が最も発熱しやすく、中心Ｃから離れるほど発熱が低下する傾向があり、上記のように多数の貫通穴８を形成することで、相対的に半導体素子５の中心Ｃから遠い周縁部分での基板３側への熱伝導による放熱性は低下することになるものの、当該部位の発熱温度は半導体素子５の中心部に比べて低いので、半導体素子５が耐熱温度以上まで昇温するのを回避することができる。言い換えるならば、相対的に半導体素子５の中心Ｃから遠い周縁部分により多くの貫通穴８を形成しても、半導体素子５の安定した放熱性または冷却性能を確保することができることになる。   By doing so, as described above with reference to FIG. 4, when the semiconductor element 5 is actually driven, the vicinity of the center C of the semiconductor element 5 is most likely to generate heat, and the heat generation tends to decrease as the distance from the center C increases. Yes, by forming a large number of through-holes 8 as described above, heat dissipation due to heat conduction to the substrate 3 side at the peripheral portion relatively far from the center C of the semiconductor element 5 is reduced, Since the heat generation temperature of the part is lower than that of the central portion of the semiconductor element 5, it is possible to avoid the semiconductor element 5 from being heated to a temperature higher than the heat resistance temperature. In other words, even if many through holes 8 are formed in the peripheral portion relatively far from the center C of the semiconductor element 5, stable heat dissipation or cooling performance of the semiconductor element 5 can be ensured.

また、複数の貫通穴８，１８のより具体的な別の配置例としては、例えば図６に示すように、半導体素子５の中心Ｃに対して距離が遠くなるほど基板３の単位面積当たりの貫通穴８，１８の断面積を増加させるべく、言い換えるならば、半導体素子５の中心Ｃに近い部分における貫通穴８の開口面積よりも半導体素子５の中心Ｃから遠い周縁部分における貫通穴１８の開口面積を大きくなるようにするべく、半径Ｒ１の同心円上にある矩形の角穴状をなす複数の貫通穴８に対して、半径Ｒ１よりも大きな半径Ｒ２（Ｒ２＞Ｒ１）の同心円上にある複数の貫通穴１８の数を図５のものより少なくする一方で、個々の貫通穴１８の大きさを貫通穴８よりも大きく設定してある。この図６の貫通穴８，１８の配置によっても図５と同様の効果が得られることになる。   As another more specific example of the arrangement of the plurality of through holes 8 and 18, as shown in FIG. 6, for example, as the distance from the center C of the semiconductor element 5 increases, the perforation per unit area of the substrate 3 In other words, in order to increase the cross-sectional area of the holes 8 and 18, in other words, the opening of the through hole 18 in the peripheral portion farther from the center C of the semiconductor element 5 than the opening area of the through hole 8 in the portion near the center C of the semiconductor element 5 In order to increase the area, a plurality of through holes 8 having a rectangular square hole shape on a concentric circle having a radius R1 and a plurality of concentric circles having a radius R2 (R2> R1) larger than the radius R1. While the number of through holes 18 is smaller than that of FIG. 5, the size of each through hole 18 is set larger than that of the through hole 8. The same effect as in FIG. 5 can be obtained by the arrangement of the through holes 8 and 18 in FIG.

ここで、図５，６に示した複数の貫通穴８，１８の配置は一例に過ぎず、必ずしも複数の貫通穴８，１８を半径Ｒ１およびＲ２の同心円上に規則性をもって配置する必要はなく、例えばアトランダムな配置としてもよい。要は、先に述べたように、半導体素子５の中心部に対して距離が遠くなるほど基板３の単位面積当たりの貫通穴８，１８の断面積を増加するような配置となっていれば所期の目的は達成することができる。   Here, the arrangement of the plurality of through holes 8 and 18 shown in FIGS. 5 and 6 is merely an example, and it is not always necessary to arrange the plurality of through holes 8 and 18 on the concentric circles having the radii R1 and R2 with regularity. For example, an at random arrangement may be employed. In short, as described above, as long as the distance from the center of the semiconductor element 5 increases, the cross-sectional area of the through holes 8 and 18 per unit area of the substrate 3 increases. The purpose of the period can be achieved.

また、上記実施の形態では、基板３に対する半導体素子５の接合にろう材として半田を用いた半田付けの例を示しているが、他のろう材を用いたろう付け等のろう接技術にも本発明を適用することができる。   In the above-described embodiment, an example of soldering using solder as a brazing material for joining the semiconductor element 5 to the substrate 3 is shown, but the present invention is also applied to brazing techniques such as brazing using other brazing materials. The invention can be applied.

１…半導体装置
３…基板
５…半導体素子
６…半田（ろう材）
８…貫通穴
１８…貫通穴 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 3 ... Board | substrate 5 ... Semiconductor element 6 ... Solder (brazing material)
8 ... Through hole 18 ... Through hole

Claims (6)

基板に対して半導体素子をろう接するようにした半導体装置の製造方法において、
上記基板のうち半導体素子が接合される領域に予め貫通穴を形成しておく一方、
ろう材による接合雰囲気条件として、
上記基板と半導体素子との間にろう材を挟んだ状態で接合雰囲気温度をろう材の融点以上の温度まで上昇させて当該ろう材を溶融させる昇温工程と、
接合雰囲気圧力を上記昇温工程よりも増加させる昇圧工程と、
上記昇圧工程で増加させた接合雰囲気圧力を維持しながら上記接合雰囲気温度をろう材の融点未満の温度まで下降させて当該ろう材を固化させる降温工程と、
を含むことを特徴とする半導体装置の製造方法。 In a method of manufacturing a semiconductor device in which a semiconductor element is brazed to a substrate,
While forming a through hole in advance in a region of the substrate where the semiconductor element is bonded,
As a joining atmosphere condition by brazing material,
A temperature raising step for melting the brazing material by raising the bonding atmosphere temperature to a temperature equal to or higher than the melting point of the brazing material in a state where the brazing material is sandwiched between the substrate and the semiconductor element,
A pressure increasing step for increasing the bonding atmosphere pressure more than the temperature raising step;
A temperature lowering step of solidifying the brazing filler metal by lowering the bonding atmosphere temperature to a temperature lower than the melting point of the brazing filler metal while maintaining the bonding atmosphere pressure increased in the boosting step;
A method for manufacturing a semiconductor device, comprising: 上記半導体素子の中心に近い部分における貫通穴の開口面積よりも上記半導体素子の中心から遠い周縁部分における貫通穴の開口面積を大きく設定してあることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The semiconductor device according to claim 1, wherein an opening area of the through hole in a peripheral portion far from the center of the semiconductor element is set larger than an opening area of the through hole in a portion near the center of the semiconductor element. Manufacturing method. 上記基板には複数の貫通穴を形成してあり、
上記半導体素子の中心に近い部分における貫通穴の数よりも上記半導体素子の中心から遠い周縁部分における複数の貫通穴の数を多く設定してあることを特徴とする請求項２に記載の半導体装置の製造方法。 The substrate has a plurality of through holes,
3. The semiconductor device according to claim 2, wherein the number of the plurality of through holes in the peripheral portion far from the center of the semiconductor element is set larger than the number of through holes in the portion near the center of the semiconductor element. Manufacturing method. 上記複数の貫通穴は共に同一の形状および同一の大きさのものであることを特徴とする請求項３に記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, wherein the plurality of through holes have the same shape and the same size. 上記基板には複数の貫通穴を形成してあり、
上記半導体素子の中心に近い部分における貫通穴の大きさよりも上記半導体素子の中心から遠い周縁部分における複数の貫通穴の大きさを大きく設定してあることを特徴とする請求項２に記載の半導体装置の製造方法。 The substrate has a plurality of through holes,
3. The semiconductor according to claim 2, wherein the size of the plurality of through holes in the peripheral portion far from the center of the semiconductor element is set larger than the size of the through hole in the portion near the center of the semiconductor element. Device manufacturing method. 上記半導体素子の中心から遠い周縁部分における複数の貫通穴の配置として、半導体素子の中心と同心円上に配置してあることを特徴とする請求項３〜５のいずれか一つに記載の半導体装置の製造方法。   6. The semiconductor device according to claim 3, wherein the plurality of through-holes in the peripheral portion far from the center of the semiconductor element are arranged concentrically with the center of the semiconductor element. Manufacturing method.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS546066U (en) * 1977-06-15 1979-01-16
JPS5820536U (en) * 1981-08-03 1983-02-08 三菱電機株式会社 semiconductor equipment
JPS62291090A (en) * 1986-06-10 1987-12-17 関西日本電気株式会社 Method of fitting electronic parts
JP2007180447A (en) * 2005-12-28 2007-07-12 Toyota Industries Corp Soldering method, soldering apparatus, and method of manufacturing semiconductor device
JP2010123654A (en) * 2008-11-18 2010-06-03 Stanley Electric Co Ltd Optical semiconductor apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS546066U (en) * 1977-06-15 1979-01-16
JPS5820536U (en) * 1981-08-03 1983-02-08 三菱電機株式会社 semiconductor equipment
JPS62291090A (en) * 1986-06-10 1987-12-17 関西日本電気株式会社 Method of fitting electronic parts
JP2007180447A (en) * 2005-12-28 2007-07-12 Toyota Industries Corp Soldering method, soldering apparatus, and method of manufacturing semiconductor device
JP2010123654A (en) * 2008-11-18 2010-06-03 Stanley Electric Co Ltd Optical semiconductor apparatus

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