JP2013157044A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2013157044A JP2013157044A JP2012014712A JP2012014712A JP2013157044A JP 2013157044 A JP2013157044 A JP 2013157044A JP 2012014712 A JP2012014712 A JP 2012014712A JP 2012014712 A JP2012014712 A JP 2012014712A JP 2013157044 A JP2013157044 A JP 2013157044A
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- bit line
- memory cell
- circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 230000004044 response Effects 0.000 claims description 23
- 230000004913 activation Effects 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 11
- 230000003213 activating effect Effects 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract description 13
- 238000010168 coupling process Methods 0.000 abstract description 13
- 238000005859 coupling reaction Methods 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 18
- 101100203174 Zea mays SGS3 gene Proteins 0.000 description 9
- 230000008859 change Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 201000008103 leukocyte adhesion deficiency 3 Diseases 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012014712A JP2013157044A (ja) | 2012-01-27 | 2012-01-27 | 半導体装置 |
| US13/748,433 US9245612B2 (en) | 2012-01-27 | 2013-01-23 | Semiconductor device having bit lines hierarchically structured |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012014712A JP2013157044A (ja) | 2012-01-27 | 2012-01-27 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013157044A true JP2013157044A (ja) | 2013-08-15 |
| JP2013157044A5 JP2013157044A5 (https=) | 2015-02-26 |
Family
ID=48870078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012014712A Withdrawn JP2013157044A (ja) | 2012-01-27 | 2012-01-27 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9245612B2 (https=) |
| JP (1) | JP2013157044A (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9552866B2 (en) | 2014-03-10 | 2017-01-24 | Micron Technology, Inc. | Semiconductor device including subword driver circuit |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8004926B2 (en) * | 2008-02-05 | 2011-08-23 | Marvell World Trade Ltd. | System and method for memory array decoding |
| JP2016170303A (ja) * | 2015-03-13 | 2016-09-23 | シナプティクス・ジャパン合同会社 | 半導体装置及び電子機器 |
| ITUA20161478A1 (it) | 2016-03-09 | 2017-09-09 | St Microelectronics Srl | Circuito e metodo di lettura di una cella di memoria di un dispositivo di memoria non volatile |
| US9542980B1 (en) * | 2016-03-29 | 2017-01-10 | Nanya Technology Corp. | Sense amplifier with mini-gap architecture and parallel interconnect |
| US10468087B2 (en) * | 2016-07-28 | 2019-11-05 | Micron Technology, Inc. | Apparatuses and methods for operations in a self-refresh state |
| WO2018125135A1 (en) * | 2016-12-29 | 2018-07-05 | Intel Corporation | Sram with hierarchical bit lines in monolithic 3d integrated chips |
| TWI842855B (zh) * | 2019-03-29 | 2024-05-21 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07111083A (ja) * | 1993-08-20 | 1995-04-25 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP4909619B2 (ja) * | 2006-04-13 | 2012-04-04 | パナソニック株式会社 | 半導体記憶装置 |
| JP5222619B2 (ja) | 2008-05-02 | 2013-06-26 | 株式会社日立製作所 | 半導体装置 |
| JP5518313B2 (ja) | 2008-08-29 | 2014-06-11 | ピーエスフォー ルクスコ エスエイアールエル | センスアンプ回路及び半導体記憶装置 |
| JP2011034614A (ja) * | 2009-07-30 | 2011-02-17 | Elpida Memory Inc | 半導体装置及びこれを備えるシステム |
| JP5666108B2 (ja) * | 2009-07-30 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びこれを備えるシステム |
| JP2011129237A (ja) * | 2009-12-21 | 2011-06-30 | Elpida Memory Inc | 半導体装置及び半導体記憶装置 |
| JP2011175719A (ja) * | 2010-02-25 | 2011-09-08 | Elpida Memory Inc | 半導体装置 |
| JP2012099195A (ja) * | 2010-11-04 | 2012-05-24 | Elpida Memory Inc | 半導体装置 |
| JP2012123893A (ja) * | 2010-11-19 | 2012-06-28 | Elpida Memory Inc | 半導体装置 |
| JP2012123878A (ja) * | 2010-12-09 | 2012-06-28 | Elpida Memory Inc | 半導体装置及びその制御方法 |
-
2012
- 2012-01-27 JP JP2012014712A patent/JP2013157044A/ja not_active Withdrawn
-
2013
- 2013-01-23 US US13/748,433 patent/US9245612B2/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9552866B2 (en) | 2014-03-10 | 2017-01-24 | Micron Technology, Inc. | Semiconductor device including subword driver circuit |
| US10332584B2 (en) | 2014-03-10 | 2019-06-25 | Micron Technology, Inc. | Semiconductor device including subword driver circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US9245612B2 (en) | 2016-01-26 |
| US20130194857A1 (en) | 2013-08-01 |
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Legal Events
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| A711 | Notification of change in applicant |
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| A521 | Request for written amendment filed |
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| A521 | Request for written amendment filed |
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| A621 | Written request for application examination |
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| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160118 |
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| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20160219 |