JP2013131592A - Lead terminal and semiconductor device using the same - Google Patents

Lead terminal and semiconductor device using the same Download PDF

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JP2013131592A
JP2013131592A JP2011279295A JP2011279295A JP2013131592A JP 2013131592 A JP2013131592 A JP 2013131592A JP 2011279295 A JP2011279295 A JP 2011279295A JP 2011279295 A JP2011279295 A JP 2011279295A JP 2013131592 A JP2013131592 A JP 2013131592A
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bonding
semiconductor device
lead terminal
main conductive
joint surface
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JP2013131592A5 (en
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Hiroaki Tatsumi
裕章 巽
Kenichi Hayashi
建一 林
Taketsugu Otsu
健嗣 大津
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a lead terminal that implements efficient manufacturing of a semiconductor device mounted with a plurality of semiconductor elements and a reliable joint, and such a semiconductor device.SOLUTION: A lead terminal 51 includes: a flat main conductive part 51m; joint surface parts 51j formed at a predetermined interval along a direction (z) perpendicular to a plane and in respective predetermined positions along directions (xy) of extension of the plane relative to the main conductive part 51m, and having joint surfaces P51 arranged so as to face respective surface side electrodes 2s, 3a of a plurality of semiconductor elements 2, 3; and connecting parts 51f connecting the joint surface parts 51j to the main conductive part 51m, respectively, such that the interval between each joint surface P51 and the main conductive part 51m varies with pressure applied between the main conductive part 51m and the joint surface P51 while maintaining parallelism between the joint surface P51 and the main conductive part 51m.

Description

本発明は、基板上に実装された複数の半導体素子に対してまとめて電気接続を行うリード端子およびこれを用いた半導体装置に関するものである。   The present invention relates to a lead terminal for collectively connecting to a plurality of semiconductor elements mounted on a substrate, and a semiconductor device using the lead terminal.

モータのインバータ制御などに用いられる電力変換用の半導体装置には、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor）などの縦型半導体素子が搭載されている。半導体素子の表裏面には金属メタライズによる電極が形成されており、一般的な半導体装置の場合、半導体素子の裏面電極が基板に、表面電極には配線部材がそれぞれ電気接続されている。とくに大電流にて動作する半導体装置では、ボンディングワイヤよりも断面積の大きなリード端子を用い、表面電極にはんだを用いて接合する場合が多い。   2. Description of the Related Art A semiconductor device for power conversion used for motor inverter control or the like is equipped with vertical semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors). Electrodes of metal metallization are formed on the front and back surfaces of the semiconductor element. In a general semiconductor device, the back electrode of the semiconductor element is electrically connected to the substrate, and the wiring member is electrically connected to the front electrode. In particular, in a semiconductor device that operates with a large current, a lead terminal having a cross-sectional area larger than that of a bonding wire is used, and the surface electrode is often joined using solder.

このような接合を効率よく行うため、基板上に搭載した複数の半導体素子の表面電極に対して配線板を一括してはんだ付けする半導体装置の製造方法が提案されている（例えば、特許文献１参照。）。一方、近年の産業機器や電鉄、自動車等の技術発展に伴って半導体装置には動作温度上限の拡大が期待されており、特に、炭化ケイ素（ＳｉＣ）、窒化ガリウム（ＧａＮ）のようなバンドギャップの大きな材料を用いた高温動作が可能な半導体素子が開発されている。そのため、半導体素子周辺の構成部材に対しても同様に高耐熱化が求められており、はんだのような融点の低い材料を用いる接合技術よりも耐熱性の高い接合技術が求められている。   In order to perform such bonding efficiently, a method of manufacturing a semiconductor device in which wiring boards are soldered to the surface electrodes of a plurality of semiconductor elements mounted on a substrate has been proposed (for example, Patent Document 1). reference.). On the other hand, semiconductor devices are expected to increase the upper limit of operating temperature with the recent technological development of industrial equipment, electric railways, automobiles, etc. Especially, band gaps such as silicon carbide (SiC) and gallium nitride (GaN) are expected. A semiconductor element capable of high-temperature operation using a large material has been developed. For this reason, high heat resistance is similarly demanded for components around the semiconductor element, and a joining technique having higher heat resistance than a joining technique using a material having a low melting point such as solder is demanded.

そこで、はんだに代わる高耐熱接合技術として、ナノ粒子の焼結性を利用した焼結接合技術（例えば、特許文献２または３参照。）や、高耐熱な化合物層を積極的に利用したＩＭＣ（金属間化合物：Inter Metallic Compound）接合技術（例えば、特許文献４参照。）などが提案されている。   Therefore, as a high heat-resistant joining technique replacing solder, a sintered joining technique using nanoparticle sinterability (see, for example, Patent Document 2 or 3), or an IMC that actively uses a high heat-resistant compound layer ( Intermetallic compounds have been proposed (for example, see Patent Document 4).

特開２００９−２２４５５０号公報（段落００３８〜００７１図３〜図１３）JP 2009-224550 A (paragraphs 0038 to 0071 FIGS. 3 to 13) 特開２００７−２１４３４０号公報（段落００１３〜００２０、００２４、図３）JP 2007-214340 A (paragraphs 0013 to 0020, 0024, FIG. 3) 特開２００７−４４７５４号公報（段落００１２〜００１５、図１、図２）JP 2007-44754 (paragraphs 0012 to 0015, FIGS. 1 and 2) 特開２００９−２９０００７号公報（段落００１８〜００３９、図１〜図３）JP 2009-290007 A (paragraphs 0018 to 0039, FIGS. 1 to 3)

しかしながら、はんだ接合と異なり、焼結接合技術や金属間化合物接合技術といった耐熱性の高い接合技術では、接合の際に被接合材間に所定の圧を印加する必要がある。そのため、基板上に搭載された複数の半導体素子の高さにばらつきがある場合、複数の半導体素子に対して剛性のあるリードフレームを一括して接合しようとすると、素子による接合状態のばらつきが生じ、接合部の信頼性が低下するという問題があった。   However, unlike solder joining, in a joining technique having high heat resistance such as a sintering joining technique or an intermetallic compound joining technique, it is necessary to apply a predetermined pressure between the materials to be joined. For this reason, when there is a variation in the height of a plurality of semiconductor elements mounted on a substrate, if a rigid lead frame is collectively bonded to the plurality of semiconductor elements, variations in the bonding state due to the elements occur. There is a problem that the reliability of the joint portion is lowered.

本発明は、上記のような課題を解決するためになされたもので、複数の半導体素子を搭載した半導体装置を効率よく製造できるとともに、信頼性が高い接合が可能なリード端子およびこれを用いた半導体装置を得ることを目的としている。   The present invention has been made in order to solve the above-described problems, and can efficiently manufacture a semiconductor device on which a plurality of semiconductor elements are mounted and uses a lead terminal capable of highly reliable bonding and the same. The object is to obtain a semiconductor device.

本発明のリード端子は、基板の主面に複数の半導体素子が配置された半導体装置に用いられ、前記複数の半導体素子のそれぞれの表側の電極と外部回路とを電気接続するためのリード端子であって、平坦状の主導電部と、前記主導電部に対して面の垂直方向に所定の間隔をあけるとともに、面の延在方向の所定位置にそれぞれ形成され、前記複数の半導体素子のそれぞれの表側の電極に対向するように配置される接合面を有する接合面部と、前記主導電部とそれぞれの接合面間に加えた圧力に応じて、当該接合面と前記主導電部との平行を維持しながら、当該接合面と前記主導電部間の間隔が変化するように前記接合面部のそれぞれと前記主導電部とを連結する連結部と、を備えたことを特徴とする。   The lead terminal of the present invention is used in a semiconductor device in which a plurality of semiconductor elements are arranged on the main surface of a substrate, and is a lead terminal for electrically connecting each front side electrode of the plurality of semiconductor elements and an external circuit. A planar main conductive portion and a predetermined interval in a direction perpendicular to the surface with respect to the main conductive portion, and formed at predetermined positions in the surface extending direction, and each of the plurality of semiconductor elements In accordance with the pressure applied between the main conductive part and the respective joint surfaces, the joint surface and the main conductive part are arranged in parallel according to the joint surface part having the joint surface disposed so as to face the front electrode of While maintaining, it has the connection part which connects each of the said joint surface part and the said main conductive part so that the space | interval between the said joint surface and the said main conductive part may change, It is characterized by the above-mentioned.

本発明のリード端子によれば、加えた力に応じて、平行を維持しながら接合面の高さを変化させるので、高さむらがある複数の素子に対して適切な圧力をかけて接合することができる、効率よく製造できるとともに、信頼性が高い接合が可能となる。   According to the lead terminal of the present invention, the height of the joining surface is changed while maintaining parallelness in accordance with the applied force, so that joining is performed by applying appropriate pressure to a plurality of elements having unevenness in height. In addition to being able to manufacture efficiently, highly reliable bonding is possible.

本発明の実施の形態１にかかるリード端子およびこれを用いた半導体装置の構成を説明するための部分平面図と断面図である。FIG. 2 is a partial plan view and a cross-sectional view for explaining the configuration of the lead terminal according to the first embodiment of the present invention and the semiconductor device using the lead terminal. 本発明の実施の形態１にかかるリード端子の構成を説明するための斜視図、断面図および平面図である。It is a perspective view, a sectional view, and a top view for explaining composition of a lead terminal concerning Embodiment 1 of the present invention. 本発明の実施の形態１にかかる半導体装置の製造方法を説明するために工程に応じた半導体装置の状態を示した側面図である。It is the side view which showed the state of the semiconductor device according to the process in order to demonstrate the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる半導体装置の製造方法を説明するためのフローチャートである。4 is a flowchart for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention; 本発明の実施の形態１の変形例にかかるリード端子の構成を説明するための斜視図、断面図および平面図である。FIG. 6 is a perspective view, a cross-sectional view, and a plan view for explaining a configuration of a lead terminal according to a modification of the first embodiment of the present invention. 本発明の実施の形態２にかかるリード端子およびこれを用いた半導体装置の構成を説明するための部分平面図と断面図である。FIG. 9 is a partial plan view and a cross-sectional view for explaining the configuration of a lead terminal according to a second embodiment of the present invention and a semiconductor device using the lead terminal. 本発明の実施の形態２にかかる半導体装置の製造方法を説明するために工程に応じた半導体装置の状態を示した側面図である。It is the side view which showed the state of the semiconductor device according to the process in order to demonstrate the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる半導体装置の製造方法を説明するためのフローチャートである。7 is a flowchart for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention; 本発明の実施の形態３にかかる半導体装置の製造方法を説明するために工程による半導体装置の状態を示した側面図である。It is the side view which showed the state of the semiconductor device by a process in order to demonstrate the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる半導体装置の製造方法を説明するためのフローチャートである。12 is a flowchart for explaining a manufacturing method of a semiconductor device according to a third embodiment of the present invention;

実施の形態１．
図１〜図４は、本発明の実施の形態１にかかるリード端子およびこれを用いた半導体装置について説明するためのものであって、図１は半導体装置から封止体を除いた状態を仮定したもので、図１（ａ）は部分平面図、図１（ｂ）は図１（ａ）のＢ−Ｂ線による部分断面図である。図２は半導体装置に用いるリードフレームに形成されたリード端子のうちのひとつのリード端子（ソース端子）の構成を示すもので、図２（ａ）はリード端子の半導体素子との接合面を含む部分の斜視図、図２（ｂ）は図２（ａ）の部分断面図、図２（ｃ）は図２（ａ）の領域Ｃ部分の平面図である。図３は製造方法を説明するための工程に応じた半導体装置の状態を示す側面図であり、図４は製造方法を説明するためのフローチャートである。また、図５は変形例にかかるリード端子の構成を説明するためのもので、変形例ごとのリード端子の主導電部から接合面部にかけての連結部を含む部分の側面図、あるいは側面図と接合面部側から見た透過図の組み合わせである。 Embodiment 1 FIG.
1 to 4 are diagrams for explaining a lead terminal according to a first embodiment of the present invention and a semiconductor device using the lead terminal, and FIG. 1 assumes a state in which a sealing body is removed from the semiconductor device. FIG. 1A is a partial plan view, and FIG. 1B is a partial cross-sectional view taken along line BB in FIG. 1A. FIG. 2 shows a configuration of one lead terminal (source terminal) of lead terminals formed on a lead frame used in a semiconductor device. FIG. 2A includes a bonding surface of the lead terminal with a semiconductor element. FIG. 2B is a partial sectional view of FIG. 2A, and FIG. 2C is a plan view of a region C portion of FIG. 2A. FIG. 3 is a side view showing the state of the semiconductor device in accordance with the steps for explaining the manufacturing method, and FIG. 4 is a flowchart for explaining the manufacturing method. FIG. 5 is a view for explaining the configuration of the lead terminal according to the modification, and is a side view of the portion including the connecting portion from the main conductive portion to the joint surface portion of the lead terminal for each modification, or joined to the side view. It is the combination of the permeation | transmission figure seen from the surface part side.

本発明の実施の形態１にかかるリード端子は、基板に配置された複数の半導体素子の表面電極に対する接合面のそれぞれが、加えられた圧力に応じて、主導電部に対して平行移動するものである。そして、半導体装置は上記構造のリード端子を用いることで、複数の半導体素子の表面電極に一括してリード端子を接合したものである。以下、図を用いて説明する。   In the lead terminal according to the first exemplary embodiment of the present invention, each of the bonding surfaces of the plurality of semiconductor elements arranged on the substrate with respect to the surface electrode is translated with respect to the main conductive portion in accordance with the applied pressure. It is. The semiconductor device uses the lead terminals having the above-described structure, and the lead terminals are collectively bonded to the surface electrodes of the plurality of semiconductor elements. This will be described below with reference to the drawings.

半導体装置１は、図１に示すように、基板４の主面上に複数の縦型半導体素子２、３が搭載されるとともに、各半導体素子が圧力に応じて接合面Ｐ５１が平行移動するリード端子５１により電気接続されたものである。本実施の形態１および以降の実施の形態においては、複数の縦型半導体素子２、３として、２個のスイッチング素子（ＭＯＳＦＥＴ）２と２個の整流素子（ＳＢＤ：Schottky diode）３を用いて２×２配列した例について説明する。２個のスイッチング素子２のそれぞれ裏面に設けたドレイン電極２ｄと、２個の整流素子３のそれぞれ裏面に設けたカソード電極３ｃとが、基板４に焼結性接合材料を用いた焼結接合部８を介して接合（電気接続）されている。そして、スイッチング素子２の表面に設けたソース電極２ｓおよび整流素子３の表面に設けたアノード電極３ａは、それぞれ、リードフレーム５に形成されたリード端子のうち、平坦状の主導電部５１ｍに可撓性の連結部５１ｆを介して接合面部５１ｊが連結されたソース端子５１に接合されている。   As shown in FIG. 1, the semiconductor device 1 has a plurality of vertical semiconductor elements 2 and 3 mounted on the main surface of the substrate 4, and each semiconductor element has a lead whose joint surface P <b> 51 moves in parallel according to pressure. The terminal 51 is electrically connected. In the first embodiment and the subsequent embodiments, two switching elements (MOSFETs) 2 and two rectifier elements (SBD: Schottky diode) 3 are used as the plurality of vertical semiconductor elements 2 and 3. An example of 2 × 2 arrangement will be described. Sintered joints in which a drain electrode 2d provided on each of the back surfaces of the two switching elements 2 and a cathode electrode 3c provided on each of the back surfaces of the two rectifying elements 3 are formed on the substrate 4 using a sinterable bonding material. 8 is joined (electrical connection). The source electrode 2 s provided on the surface of the switching element 2 and the anode electrode 3 a provided on the surface of the rectifying element 3 can be applied to the flat main conductive portion 51 m among the lead terminals formed on the lead frame 5. It is joined to the source terminal 51 to which the joint surface part 51j is connected via the flexible connection part 51f.

このとき、ソース電極２ｓおよびアノード電極３ａと接合面Ｐ５１とを焼結接合部８によって直接接合してもよいが、後述するように接合性の向上のために、本実施の形態においては、導電性金属板（導電板）７を間に入れて接合するようにしている。つまり、ソース電極２ｓと導電板７とを焼結接合部８を介して接合するとともに、導電板７と接合面Ｐ５１とを焼結接合部８を介して接合することにより、ソース電極２ｓとソース端子５１とを電気接続している。同様に、アノード電極３ａと導電板７とを焼結接合部８を介して接合するとともに、導電板７と接合面Ｐ５１とを焼結接合部８を介して接合することにより、アノード電極３ａとソース端子５１とを電気接続している。   At this time, the source electrode 2s, the anode electrode 3a, and the bonding surface P51 may be directly bonded by the sintered bonding portion 8. However, in the present embodiment, as described later, A conductive metal plate (conductive plate) 7 is interposed between them. That is, the source electrode 2 s and the conductive plate 7 are joined via the sintered joint portion 8, and the conductive plate 7 and the joint surface P 51 are joined via the sintered joint portion 8, whereby the source electrode 2 s and the source plate 7. The terminal 51 is electrically connected. Similarly, the anode electrode 3a and the conductive plate 7 are joined through the sintered joint portion 8, and the conductive plate 7 and the joint surface P51 are joined through the sintered joint portion 8, thereby The source terminal 51 is electrically connected.

なお、上記電気接続においては、基本的に同じ焼結性接合材料を用いて焼結接合部８を構成したが、後述する製造方法において区別するため、基板４と半導体素子２、３の裏面電極との接合部を８ａ、半導体素子２、３の表面電極と導電板７との接合部を８ｂ、導電板７とソース端子５１の接合面Ｐ５１との接合部を８ｃと称して区別する。   In the electrical connection, the sintered joint 8 is basically formed using the same sinterable joining material. However, in order to distinguish in the manufacturing method described later, the back electrodes of the substrate 4 and the semiconductor elements 2 and 3 are used. The joint between the surface electrode of the semiconductor elements 2 and 3 and the conductive plate 7 is referred to as 8b, and the joint between the conductive plate 7 and the joint surface P51 of the source terminal 51 is referred to as 8c.

スイッチング素子２のゲート電極２ｇは、リードフレーム５に形成された制御端子５３とボンディングワイヤ６により接続されている。また、リードフレーム５に形成されたドレイン端子５２は、基板４と超音波接合技術により接続されている。そして、基板４の半導体素子２、３が接合された面の反対側に形成された放熱面を除き、全体が封止樹脂９によって封止されている。   A gate electrode 2 g of the switching element 2 is connected to a control terminal 53 formed on the lead frame 5 by a bonding wire 6. The drain terminal 52 formed on the lead frame 5 is connected to the substrate 4 by an ultrasonic bonding technique. The entire substrate 4 is sealed with a sealing resin 9 except for the heat dissipation surface formed on the opposite side of the surface where the semiconductor elements 2 and 3 are bonded.

半導体素子２、３を構成する材料としては、シリコンウエハを基材とした一般的な素子材料でも良いが、本発明においては炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料を用いたときの効果が高く、特に顕著な効果が期待できる炭化ケイ素を用いた。   The material constituting the semiconductor elements 2 and 3 may be a general element material based on a silicon wafer, but in the present invention, it is compared with silicon such as silicon carbide (SiC), gallium nitride (GaN), or diamond. Thus, silicon carbide is used which is highly effective when a so-called wide band gap semiconductor material having a wide band gap is used and can be expected to have a particularly remarkable effect.

焼結接合部８を形成する焼結性接合材料は、ナノメーターレベルの金属微粒子（金属ナノ粒子）の反応性により、その金属がバルクで示す融点よりも低い温度で焼結する現象を利用したものである。しかし、金属ナノ粒子は、その反応性の高さから、常温でも接触するだけで焼結が進行する。そのため、焼結性接合材料では、金属ナノ粒子が凝集して焼結反応が進行するのを抑制するため、金属ナノ粒子間を独立した状態で分散保持するための有機分散材によって保持されている。さらに、接合工程において焼結反応を生じさせるため、加熱により有機分散材と反応して金属ナノ粒子を裸にする分散材捕捉材と、分散材と分散材捕捉材との反応物質を捕捉して揮散する揮発性有機成分等が添加されている。つまり、焼結性接合材料は、骨材たる金属ナノ粒子が有機成分中に分散されてペースト状になったもの（ペースト８Ｐと称する）であり、ペースト８Ｐを所望の被接合部材間に供給し、加熱することで焼結接合を達成するものである。   The sinterable bonding material for forming the sintered joint 8 utilizes the phenomenon that the metal sinters at a temperature lower than the melting point shown in bulk due to the reactivity of the nanometer level metal fine particles (metal nanoparticles). Is. However, due to the high reactivity of metal nanoparticles, sintering proceeds just by contacting them at room temperature. Therefore, in the sinterable bonding material, in order to prevent the metal nanoparticles from aggregating and advancing the sintering reaction, the metal nanoparticles are held by the organic dispersion material for dispersing and holding the metal nanoparticles in an independent state. . Further, in order to cause a sintering reaction in the joining process, the dispersion trapping material that reacts with the organic dispersion material by heating to bare the metal nanoparticles, and the reactants of the dispersion material and the dispersion material trapping material are captured. Volatile organic components that volatilize are added. That is, the sinterable bonding material is a paste in which metal nanoparticles as an aggregate are dispersed in an organic component (referred to as paste 8P), and the paste 8P is supplied between desired members to be bonded. The sintered joining is achieved by heating.

このとき、ペースト８Ｐ中の有機成分の分解とナノ粒子の焼結によって、接合後の焼結接合部８の体積は、初期のペースト時の体積に対して約半分程度に減少する。そのため、ボイドの少ない信頼性の高い焼結接合部８を得るためには、接合時に所定の圧を印加しながら加熱しなければならない。したがって、大電流に対応するため、ワイヤなどと比較して板厚の厚い（断面積の大きな）リードフレーム５のような配線材料を複数の半導体素子に同時に接合する場合に、素子による高さばらつきを補償して加圧できるようにする必要がある。そこで、本実施の形態に示すように、圧力に応じて接合面Ｐ５１を主導電部５１ｍ側に平行移動できるように接合面部５１ｊを主導電部５１ｍに連結する可撓性の連結部５１ｆで連結したリード端子構造が必要となる。   At this time, due to the decomposition of the organic component in the paste 8P and the sintering of the nanoparticles, the volume of the sintered bonded portion 8 after bonding is reduced to about half of the initial paste volume. For this reason, in order to obtain a highly reliable sintered joint portion 8 with few voids, it is necessary to heat while applying a predetermined pressure during joining. Therefore, in order to cope with a large current, when a wiring material such as a lead frame 5 having a larger plate thickness (large cross-sectional area) than a wire or the like is bonded to a plurality of semiconductor elements at the same time, the height varies depending on the elements. It is necessary to compensate for this so that it can be pressurized. Therefore, as shown in the present embodiment, the joint surface 51j is connected by the flexible connection portion 51f that connects the joint surface portion 51j to the main conductive portion 51m so that the joint surface P51 can be translated to the main conductive portion 51m side according to the pressure. Lead terminal structure is required.

ソース端子５１の主導電部５１ｍから接合面部５１ｊにかけての構成、つまり連結部５１ｆの構成について図２を用いて説明する。ソース端子５１には、２×２配列した半導体素子２、３の電極２ｓ、３ａ（厳密には導電板７を介して）とそれぞれ電気接続するための接合面Ｐ５１を有する接合面部５１ｊが設けられている。ソース端子５１はリードフレーム５内に形成された端子であって、主導電部５１ｍから接合面部５１ｊにかけての部分も連続する板材を折り曲げることによって形成したものである。主導電部５１ｍは、他端側が図示しない外部端子に向かって延在（ｘ方向）し、複数の半導体素子２、３の直近上に延びる一端側が平坦状をなしており、半導体装置において基板４と平行に配置されるものである。そして、主導電部５１ｍの一端部と中間部から幅方向に（ｙ方向）に分岐して延びた板材のそれぞれをｘ軸に沿って互い違いに２回折り曲げることで、可撓性を有する連結部５１ｆと、接合面部５１ｊが順次形成されることになる。これにより、ｘ方向から見たとき（図２（ｂ））に主導電部５１ｍから接合面部５１ｊにかけてＺ型形状をなし、主導電部５１ｍに対して接合面Ｐ５１が平行に配置される。   The configuration of the source terminal 51 from the main conductive portion 51m to the joint surface portion 51j, that is, the configuration of the connecting portion 51f will be described with reference to FIG. The source terminal 51 is provided with a joint surface portion 51j having a joint surface P51 for electrical connection with the electrodes 2s and 3a (strictly, through the conductive plate 7) of the semiconductor elements 2 and 3 arranged in 2 × 2. ing. The source terminal 51 is a terminal formed in the lead frame 5, and the portion from the main conductive portion 51 m to the joint surface portion 51 j is also formed by bending a continuous plate material. The main conductive portion 51m has the other end extending toward an external terminal (not shown) (in the x direction), and one end extending immediately above the plurality of semiconductor elements 2 and 3 has a flat shape. Are arranged in parallel with each other. Then, each of the plate members branched and extended in the width direction (y direction) from the one end portion and the intermediate portion of the main conductive portion 51m is bent twice alternately along the x axis, thereby having a flexible connecting portion. 51f and the joint surface portion 51j are sequentially formed. As a result, when viewed from the x direction (FIG. 2B), a Z shape is formed from the main conductive portion 51m to the bonding surface portion 51j, and the bonding surface P51 is arranged in parallel to the main conductive portion 51m.

ここで、接合信頼性を損なう原因である複数の半導体素子の高さのばらつきは、スイッチング素子２やダイオード３のように、もともと厚みの異なる素子を混載した場合の他、素子の製造公差によって生じる可能性があるとともに、基板４との接合部の厚みのばらつき等から生じる可能性もある。ここでは例として５０μｍの高さばらつき（標準高さ±２５μｍ）が生じる場合について述べる。この場合、各接合面Ｐ５１と被接合材との間（接合部材）には、連結部５１ｆのバネ定数とバネたわみ量の違いの範囲で定まった加圧力が付与されることになる。焼結接合技術や、後の実施の形態で説明する金属間化合物接合技術で求められる加圧力としてここでは１０ＭＰａを所定の接合加圧力とし、許容されるバラつき範囲を１０ＭＰａ±２．５ＭＰａとした場合の連結部５１ｆの形状を例示することとした。   Here, the variation in the heights of the plurality of semiconductor elements, which is a cause of impairing the junction reliability, occurs due to the manufacturing tolerance of the elements in addition to the case where elements having different thicknesses are mixedly mounted, such as the switching element 2 and the diode 3. In addition, there is a possibility that it may be caused by variations in the thickness of the joint portion with the substrate 4. Here, as an example, a case where a height variation of 50 μm (standard height ± 25 μm) occurs will be described. In this case, a pressing force determined in the range of the difference between the spring constant of the connecting portion 51f and the spring deflection amount is applied between each joining surface P51 and the material to be joined (joining member). In this case, the applied pressure required for the sintering joining technique and the intermetallic compound joining technique described in the following embodiment is 10 MPa as a predetermined joining pressure, and the allowable variation range is 10 MPa ± 2.5 MPa. The shape of the connecting portion 51f is exemplified.

連結部５１ｆは、プレス加工にてリードフレーム５を製造する際に同時に成形されており、特にプレス曲げ工程にて主導電部５１ｍから接合面部５１ｊにかけてＺ曲げすることで屈曲状の変形部５１ｆｂ１、５１ｆｂ２が成形されている。ここで、リードフレーム５の板厚を０．６ｍｍ、Ｚ型に曲げられた連結部５１ｆの各変形部５１ｆｂ１、５１ｆｂ２の曲げ角度を４５度とすると、解析結果からばね定数は約３０００Ｎ／ｍｍとなり、接合面積（≒接合面部５１ｊの面積）が３０ｍｍ２だとすると、連結部５１ｆの厚み（ｚ方向）を０．１ｍｍ縮ませることで、接合部に所定の加圧力１０ＭＰａを付与できることになる。そこから素子の基板４からの高さが標準高さ±２５μｍの範囲でバラつく場合においても、接合部に生じる加圧力は７．５〜１２．５ＭＰａの範囲に収まる。つまり、上記構造の連結部５１ｆによって主導電部５１ｍと接合面部５１ｊとを連結することで、素子の高さばらつきが最大５０μｍある場合でも、所定の加圧力バラつきの範囲内で加圧接合することが可能となることがわかる。 The connecting portion 51f is formed at the same time when the lead frame 5 is manufactured by press working, and in particular, by bending the main conductive portion 51m to the joint surface portion 51j in a press bending process, the bent deformed portion 51fb1, 51fb2 is molded. Here, when the plate thickness of the lead frame 5 is 0.6 mm and the bending angle of each of the deformed portions 51fb1 and 51fb2 of the connecting portion 51f bent into the Z shape is 45 degrees, the spring constant is about 3000 N / mm from the analysis result. If the bonding area (≈the area of the bonding surface portion 51j) is 30 mm 2 , a predetermined pressure of 10 MPa can be applied to the bonding portion by reducing the thickness (z direction) of the connecting portion 51f by 0.1 mm. Even when the height of the element from the substrate 4 varies within the range of the standard height of ± 25 μm, the applied pressure generated at the junction is within the range of 7.5 to 12.5 MPa. In other words, by connecting the main conductive portion 51m and the bonding surface portion 51j by the connecting portion 51f having the above structure, even when the height variation of the element is 50 μm at the maximum, pressure bonding is performed within a predetermined pressure variation range. It turns out that is possible.

さらに、図２（ｂ）、（ｃ）に示すように、接合面Ｐ５１の中心部Ｐｃを通る接合面Ｐ５１（ｘｙ面）に垂直な軸Ｘｃ（ｚ方向）の両側に変形部５１ｆｂ１、５１ｆｂ２が位置するように、連結部５１ｆを形成した。そのため、連結部５１ｆの高さが変化する、つまり、各変形部５１ｆｂ１、５１ｆｂ２の曲げ角度が変化しても、接合面Ｐ５１と主導電部５１ｍ間の平行度が変化せず、面内での圧力分布も一様になる。つまり、半導体素子２、３の各電極に接合面Ｐ５１を対向させ、主導電部５１ｍに平らな面を押し当てて圧力をかけることで半導体素子２、３の電極２ｓ、３ａ（導電板７）との接触面に所定範囲の圧力を印加することができる。   Further, as shown in FIGS. 2B and 2C, deformed portions 51fb1 and 51fb2 are provided on both sides of the axis Xc (z direction) perpendicular to the joint surface P51 (xy plane) passing through the center portion Pc of the joint surface P51. The connecting portion 51f was formed so as to be positioned. Therefore, even if the height of the connecting portion 51f changes, that is, even if the bending angle of each of the deforming portions 51fb1 and 51fb2 changes, the parallelism between the joint surface P51 and the main conductive portion 51m does not change, and in-plane The pressure distribution is also uniform. That is, the bonding surface P51 is opposed to each electrode of the semiconductor elements 2 and 3, and a flat surface is pressed against the main conductive portion 51m to apply pressure, whereby the electrodes 2s and 3a of the semiconductor elements 2 and 3 (conductive plate 7). A predetermined range of pressure can be applied to the contact surface.

また、ここでは素子高さの違いが最大５０μｍである場合について説明したが、これ以上の厚さ範囲でバラつく可能性がある場合でも、連結部５１ｆの板厚を薄くしたり、曲げ角度を大きくしたりすることで解決可能である。その際にも、接合面Ｐ５１の中心部Ｐｃを通る軸Ｘｃの両側に変形部５１ｆｂ１、５１ｆｂ２が位置するように、連結部５１ｆを形成すれば、必要な変形量が変化しても、接合面Ｐ５１内にかかる圧力分布を一様にすることができる。   In addition, although the case where the difference in element height is 50 μm at the maximum has been described here, even when there is a possibility of variations in the thickness range beyond this, the thickness of the connecting portion 51f is reduced or the bending angle is changed. It can be solved by increasing the size. Even in this case, if the connecting portion 51f is formed so that the deformable portions 51fb1 and 51fb2 are located on both sides of the axis Xc passing through the center portion Pc of the joint surface P51, even if the required deformation amount changes, the joint surface The pressure distribution in P51 can be made uniform.

なお、焼結性接合材料との接合性を考慮して、接合面Ｐ５１には、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）などの金属膜、あるいは、金、銀、銅、白金（Ｐｔ）、パラジウム（Ｐｄ）などが最表面にくるような薄膜層が形成されている。   In consideration of the bondability with the sinterable bonding material, the bonding surface P51 has a metal film such as gold (Au), silver (Ag), copper (Cu), or gold, silver, copper, platinum. A thin film layer is formed such that (Pt), palladium (Pd), and the like are on the outermost surface.

一方、焼結性接合材料で接続される半導体素子２、３の電極２ｓ、２ｄ、３ａおよび３ｃも、焼結性接合材料との接合性を考慮して、厚さ数百ｎｍ〜数μｍの金、銀、銅などの電極膜で形成、あるいは、金、銀、銅、白金、パラジウムなどが最表面にくるように例えばニッケル（Ｎｉ）／金といった薄膜層構造で形成している。なお、接合面部５１ｊや半導体素子２、３に形成する電極の材料としては、上記材料に限定されることはなく、焼結性接合材料や被接合材、および基板４、導電板７との接合性や安定性等を考慮して適宜選定すればよい。   On the other hand, the electrodes 2s, 2d, 3a and 3c of the semiconductor elements 2 and 3 connected by the sinterable bonding material are also several hundred nm to several μm in thickness in consideration of the bondability with the sinterable bonding material. It is formed with an electrode film of gold, silver, copper or the like, or it is formed with a thin film layer structure such as nickel (Ni) / gold so that gold, silver, copper, platinum, palladium or the like comes to the outermost surface. Note that the material of the electrodes formed on the bonding surface portion 51j and the semiconductor elements 2 and 3 is not limited to the above materials, and the bonding between the sinterable bonding material and the material to be bonded, and the substrate 4 and the conductive plate 7 is possible. May be selected as appropriate in consideration of properties and stability.

ただし、製造プロセスの初期工程から熱履歴を受ける半導体素子２、３の電極をニッケル／金といった薄膜多層構造で形成した場合、以下のような場合には、製造プロセスについて考慮する必要がある。電極最表面の薄膜厚が例えば金メタライズで数十〜２００ｎｍ程度と薄く、かつその下地層として焼結性接合材料との接合性に劣る金属（例えばニッケル）が用いられると、複数回の加熱製造プロセス中に付与される熱履歴によってニッケル下地層が電極最表面にまで拡散してくることがあり、接合性の低下を招く。その場合、後述する導電板７を用いた製造方法が接合性の低下を抑制するうえで有効になる。   However, when the electrodes of the semiconductor elements 2 and 3 that receive a thermal history from the initial step of the manufacturing process are formed with a thin film multilayer structure such as nickel / gold, it is necessary to consider the manufacturing process in the following cases. When a thin metal film on the outermost surface of the electrode is thin, for example, about several tens to 200 nm of gold metallization, and a metal (for example, nickel) that is inferior in bondability with a sinterable bonding material is used as the underlying layer, heating is performed multiple times. The nickel underlayer may diffuse to the outermost surface of the electrode due to the thermal history applied during the process, resulting in a decrease in bondability. In that case, the manufacturing method using the conductive plate 7 to be described later is effective in suppressing deterioration of the bonding property.

導電板７は、焼結性接合材料を用いた接合技術によって接合可能な接合部表面状態を有する金属板であり、接合部表面は金、銀、銅、白金、パラジウムなどが望ましい。このとき、導電板７の材質を導電性のあるアルミニウム（Ａｌ）や銅、ニッケル、チタン（Ｔｉ）、鉄（Ｆｅ）等の金属材料やＣｕ−Ｍｏ、Ａｌ−ＳｉＣなどの導電性セラミック複合材料、Ｃｕ−Ｉｎｖａｒ−Ｃｕなどのクラッド材料とし、接合部表面にのみ焼結接合技術で接合可能な上記金属をめっき等によって設けてもかまわない。ただし、上記表面に施した接合可能な金属層は、少なくとも５００ｎｍ以上、理想的には１〜５μｍ程度の厚さを有し、複数回の加熱プロセスに伴う熱履歴後も接合部表面に接合性に劣る金属が拡散し湧出してこないよう配慮されたものでなければならない。なお、図１では、説明を簡略化するため、スイッチング素子２の表面には、ひとつの電極２ｓのみに導電板７を適用している例について記載しているが、表面に複数の電極（主電力用）が区分けして形成されている場合でも適用可能である。   The conductive plate 7 is a metal plate having a bonded portion surface state that can be bonded by a bonding technique using a sinterable bonding material, and the bonded portion surface is preferably made of gold, silver, copper, platinum, palladium, or the like. At this time, the conductive plate 7 is made of a conductive metal material such as aluminum (Al), copper, nickel, titanium (Ti), iron (Fe), etc., or a conductive ceramic composite material such as Cu-Mo, Al-SiC. Alternatively, a clad material such as Cu-Invar-Cu may be used, and the above-described metal that can be bonded only by a sintered bonding technique on the surface of the bonding portion may be provided by plating or the like. However, the metal layer that can be bonded on the surface has a thickness of at least 500 nm or more, ideally about 1 to 5 μm, and can be bonded to the surface of the bonded portion even after a thermal history associated with multiple heating processes. It must be designed so that inferior metals will not diffuse and spring out. 1 shows an example in which the conductive plate 7 is applied to only one electrode 2s on the surface of the switching element 2 for the sake of simplicity, but a plurality of electrodes (mainly on the surface). It can be applied even when (for power) is formed separately.

次に、上記半導体装置１を製造する方法について図３の側面図と図４のフローチャートのステップ番号を用いて説明する。なお、図３（以降の実施の形態における図７、図９も）は、側面を示すものであるが、その工程において注目すべき部材にハッチングを施して表現している。
まず、図３（ａ）に示すように、基板４の半導体素子２、３を接合する領域にペースト８Ｐを供給する（ステップＳ１１０）とともに、半導体素子２、３のソース電極２ｓ、アノード電極３ａにもペースト８Ｐを供給する（ステップＳ１２０）。そして、基板４のペースト８Ｐを供給した部分に、半導体素子２、３の裏面電極であるドレイン電極２ｄ、カソード電極３ｃを合わせるように設置する。さらに、設置した半導体素子２、３のペースト８Ｐが供給された部分にそれぞれ導電板７を設置し（ステップＳ２００）、１回目接合における被接合体とする。 Next, a method for manufacturing the semiconductor device 1 will be described using the side view of FIG. 3 and the step numbers of the flowchart of FIG. Note that FIG. 3 (also in FIGS. 7 and 9 in the following embodiments) shows a side surface, but is expressed by hatching a member to be noted in the process.
First, as shown in FIG. 3A, the paste 8P is supplied to the region where the semiconductor elements 2 and 3 of the substrate 4 are joined (step S110), and the source electrode 2s and the anode electrode 3a of the semiconductor elements 2 and 3 are applied. Also supplies the paste 8P (step S120). Then, the drain electrode 2d and the cathode electrode 3c, which are the back electrodes of the semiconductor elements 2 and 3, are installed so as to match the portion of the substrate 4 to which the paste 8P is supplied. Furthermore, the conductive plates 7 are respectively installed in the portions where the paste 8P of the installed semiconductor elements 2 and 3 is supplied (step S200), and are to be joined in the first bonding.

その後、図３（ｂ）に示すように、被接合体を加熱プレス装置２１に挿入し、加熱プレスステージ面２１ｓと加熱プレスツール面２１ｔとで加熱加圧して、１回目接合を行う（ステップＳ３００）。このとき、半導体素子２、３の厚さ（基板４からの高さ）が異なる場合にも所定範囲の加圧力がかかるように、被接合体と加熱プレスツール面２１ｔとの間には、所定のばね係数に相当するクッション性を有するシート材（緩衝部材）２２を挿入する。これにより、焼結接合部８ａおよび８ｂが形成され、基板４と半導体素子２、３の裏面電極２ｄ、３ｃとの電気接続および半導体素子２、３のソース電極２ｓ、アノード電極３ａと導電板７との電気接続が達成され、１次組立体１Ａ１が形成される。   Then, as shown in FIG.3 (b), a to-be-joined body is inserted in the heat press apparatus 21, and it heat-presses with the heat press stage surface 21s and the heat press tool surface 21t, and 1st joining is performed (step S300). ). At this time, there is a predetermined gap between the object to be bonded and the heating press tool surface 21t so that a predetermined range of pressure is applied even when the thickness of the semiconductor elements 2 and 3 (height from the substrate 4) is different. A sheet material (buffer member) 22 having a cushioning property corresponding to the spring coefficient is inserted. As a result, sintered joints 8a and 8b are formed, and the electrical connection between the substrate 4 and the back electrodes 2d and 3c of the semiconductor elements 2 and 3 and the source electrode 2s, the anode electrode 3a and the conductive plate 7 of the semiconductor elements 2 and 3 are formed. And the primary assembly 1A1 is formed.

続いて、図３（ｃ）に示すようにリードフレーム５の接合面Ｐ５１にペースト８Ｐを供給する（ステップＳ１３０）。そして、１次組立体１Ａ１と加熱プレスツール面２１ｔとの間の緩衝部材２２を取り外し、導電板７とペースト８Ｐが供給された接合面Ｐ５１とを位置合わせしながらリードフレーム５を１次組立体１Ａ１上に設置し（ステップＳ４００）、２回目接合における被接合体とする。その後、図３（ｄ）に示すように、再び加熱プレス装置２１にて被接合体を直接加熱加圧して２回目接合を行う。これにより、焼結接合部８ｃが形成され、導電板７とソース端子５１との電気接続が達成され２次組立体１Ａ２が形成される。   Subsequently, as shown in FIG. 3C, the paste 8P is supplied to the bonding surface P51 of the lead frame 5 (step S130). Then, the buffer member 22 between the primary assembly 1A1 and the heating press tool surface 21t is removed, and the lead frame 5 is assembled to the primary assembly while positioning the conductive plate 7 and the bonding surface P51 supplied with the paste 8P. It installs on 1A1 (step S400), and it is set as the to-be-joined body in the second joining. Then, as shown in FIG.3 (d), a to-be-joined body is directly heat-pressed with the heat press apparatus 21, and 2nd joining is performed. Thereby, the sintered joint 8c is formed, the electrical connection between the conductive plate 7 and the source terminal 51 is achieved, and the secondary assembly 1A2 is formed.

このとき、従来のようにリード端子の主導電部（本体）と接合面との間に可撓性を有する部材が介在していない場合、たとえ１回目接合のようにクッション性のある緩衝部材２２を用いたとしても、リードフレームが厚さ（高さ）の異なる半導体素子２、３に応じて変形することができないので、接合不良が発生する可能性が高い。しかしながら、本実施の形態に示すように、ソース端子５１は主導電部５１ｍと接合面部５１ｊとを可撓性のある連結部５１ｆで連結したので、高さが異なる素子に対しても、所定範囲の面圧をかけることができ、焼結接合技術による信頼性の高い焼結接合部８の形成が可能となり、結果、半導体装置１の耐熱性および信頼性を向上させることができる。   At this time, when a member having flexibility is not interposed between the main conductive portion (main body) of the lead terminal and the joining surface as in the conventional case, the cushioning member 22 having cushioning properties as in the first joining. However, since the lead frame cannot be deformed according to the semiconductor elements 2 and 3 having different thicknesses (heights), there is a high possibility that a bonding failure will occur. However, as shown in the present embodiment, since the source terminal 51 has the main conductive portion 51m and the joint surface portion 51j connected by a flexible connecting portion 51f, even a device having a different height has a predetermined range. Therefore, it is possible to form the sintered joint 8 having high reliability by the sintering joining technique, and as a result, the heat resistance and reliability of the semiconductor device 1 can be improved.

また、接合面Ｐ５１の中心部Ｐｃを通る軸Ｘｃの両側に変形部５１ｆｂ１、５１ｆｂ２が位置するように、連結部５１ｆを形成したので、接合面Ｐ５１の面内での圧力分布も一様になるので、より信頼性の高い接合が可能となる。   Further, since the connecting portion 51f is formed so that the deformable portions 51fb1 and 51fb2 are located on both sides of the axis Xc passing through the center portion Pc of the joint surface P51, the pressure distribution in the surface of the joint surface P51 is also uniform. Therefore, bonding with higher reliability is possible.

その後、ドレイン端子５２を基板４に対して超音波接合したり、制御端子５３とゲート電極２ｇとをボンディングワイヤ６でワイヤボンドしたりすることで、電気配線が完了する。さらに、基板４の半導体素子２、３が接合された面の反対側に形成された放熱面を除き、全体を封止樹脂９によって封止し、リードフレーム５の各端子を切り離し、折り曲げ形成する等をしてパッケージ化された半導体装置１が完成する。   Thereafter, the drain terminal 52 is ultrasonically bonded to the substrate 4, or the control terminal 53 and the gate electrode 2 g are wire-bonded with the bonding wire 6 to complete the electrical wiring. Further, except for the heat radiation surface formed on the opposite side of the surface of the substrate 4 to which the semiconductor elements 2 and 3 are joined, the whole is sealed with a sealing resin 9, and each terminal of the lead frame 5 is separated and bent. Thus, the packaged semiconductor device 1 is completed.

なお、本実施の形態１においては、上述したように複数回の加熱プロセスに伴う熱履歴後に、半導体素子２、３の表面電極の表面に接合性に劣る金属が拡散し湧出してくる場合も想定して、導電板７を表面電極上に接合するようにしたものである。そのため、このような場合を想定する必要がない場合は、必ずしも導電板７を使用する必要はない。ただし、半導体素子上に導電板を予め基板と同時に接合しておくと、半導体素子表面電極とリードフレームとの位置関係を厳密に制御しなくとも、素子の電極外と接合材あるいはリードフレームとの接触を防止するという効果を得ることもできる。   In the first embodiment, as described above, after the thermal history associated with a plurality of heating processes, a metal having poor bonding properties may diffuse and spring out on the surfaces of the surface electrodes of the semiconductor elements 2 and 3. It is assumed that the conductive plate 7 is bonded onto the surface electrode. Therefore, when it is not necessary to assume such a case, it is not always necessary to use the conductive plate 7. However, if the conductive plate is bonded to the semiconductor element in advance at the same time as the substrate, there is no need to strictly control the positional relationship between the surface electrode of the semiconductor element and the lead frame. The effect of preventing contact can also be obtained.

実施の形態１の変形例．
一方、連結部５１ｆを含む主導電部５１ｍから接合面部５１ｊにかけての形状は上記Ｚ型構造に限るものではない。ただし、リードフレーム５を介して加圧した際に、変形部の変形に伴って、接合面Ｐ５１が導電板７のような被接合面に対して跳ね上がり、平行を維持できるように連結部５１ｆが変形するような構造でなくてはならない。そのため、接合面Ｐ５１の中心Ｐｃを通る接合面Ｐ５１に垂直な軸Ｘｃの両側に、少なくとも一対の変形部を有するような構造でなければならない。 Modification of the first embodiment.
On the other hand, the shape from the main conductive part 51m including the connecting part 51f to the joint surface part 51j is not limited to the Z-type structure. However, when the pressure is applied through the lead frame 5, the connecting portion 51 f is formed so that the joining surface P 51 jumps up with respect to the joined surface such as the conductive plate 7 along with the deformation of the deforming portion and can maintain parallelism. The structure must be deformed. Therefore, the structure must have at least a pair of deformed portions on both sides of the axis Xc perpendicular to the joint surface P51 passing through the center Pc of the joint surface P51.

例えば図５（ａ）、図５（ｂ）に示すようにＭ型、Ｌ型などが例として挙げられる。図５（ａ）においては、屈曲状の変形部５１ｆｂ１〜５１ｆｂ３のうち、５１ｆｂ１と５１ｆｂ３が軸Ｘｃを挟んで変形部５１ｆｂ２と対峙するように構成している。図５（ｂ）においては、屈曲状の変形部５１ｆｂ１が軸Ｘｃを挟んで変形部５１ｆｂ２と対峙するように構成している。これにより、連結部５１ｆの高さ（主導電部５１ｍ〜接合面Ｐ５１間の厚み）が変化しても、接合面Ｐ５１は主導電部５１ｍに対しての平行を維持する、つまり被接合面である半導体素子２、３の電極面との平行を維持することが可能となり、面内で面圧を一様に保つことができる。   For example, as shown in FIG. 5 (a) and FIG. 5 (b), examples include M type and L type. In FIG. 5A, among the bent deformation portions 51fb1 to 51fb3, 51fb1 and 51fb3 are configured to face the deformation portion 51fb2 across the axis Xc. In FIG. 5B, the bent deformable portion 51fb1 is configured to face the deformable portion 51fb2 across the axis Xc. As a result, even if the height of the connecting portion 51f (the thickness between the main conductive portion 51m and the bonding surface P51) changes, the bonding surface P51 maintains parallel to the main conductive portion 51m. It becomes possible to maintain parallelness with the electrode surfaces of certain semiconductor elements 2 and 3, and to keep the surface pressure uniform within the surface.

また、上記変形例も含め、本実施の形態ではリードフレーム５を製造するプレス工程にて連結部５１ｆを設ける（形成する）としたが、別途連結部や接合面部となる部材を作製し、リードフレームに別途作製した連結部や接合面部を溶接、ろう付け、超音波接合、圧接などの導電性を確保できる接合技術で接合してあっても良い。接合面部の材質は少なくとも最表面が焼結性金属材料等の接合部材との接合性及び導電性があるものであればよく、連結部の材質は導電性を示す金属材料であれば特に制限はなく、形状もより自由度が高くなる。例えば、図５（ｃ１）、（ｃ２）に示すようにコイルバネ状の連結部５１ｆとすれば、中心Ｐｃを通る軸Ｘｃを囲むようにらせん状の変形部５１ｆｂｖが形成されているので、軸Ｘｃを挟んで少なくとも対となる変形部を有することになる。   In addition, in the present embodiment, including the above-described modification, the connecting portion 51f is provided (formed) in the pressing process for manufacturing the lead frame 5, but a member to be a connecting portion or a joint surface portion is separately manufactured and the lead is formed. You may join the connection part and joining surface part which were produced separately to the flame | frame with joining techniques which can ensure electroconductivity, such as welding, brazing, ultrasonic joining, and pressure welding. As long as the material of the joining surface portion is at least the outermost surface has bonding property and conductivity with a joining member such as a sinterable metal material, the connecting portion material is not particularly limited as long as it is a metallic material exhibiting conductivity. The shape is also more flexible. For example, as shown in FIGS. 5 (c1) and 5 (c2), if the coil spring-like connecting portion 51f is formed, the helical deformation portion 51fbv is formed so as to surround the axis Xc passing through the center Pc. It will have at least a pair of deformed portions across the surface.

また例えば、図５（ｄ１）、（ｄ２）に示すようにポーラス金属状（多孔金属）の柱状物とすれば、多孔金属を形成する粒子同士の結合部分が変形部となり、柱状物の体積内に変形部が分布することになる。つまり、中心Ｐｃを通る軸Ｘｃを囲むように変形部５１ｆｂｐが形成されていることになるので、軸Ｘｃを挟んで少なくとも対となる変形部を有することになる。   Further, for example, as shown in FIGS. 5 (d1) and 5 (d2), if a porous metal-like (porous metal) columnar material is used, the bonded portion between the particles forming the porous metal becomes a deformed portion, and the volume of the columnar material is within the range. Therefore, the deformed parts are distributed. That is, since the deformed portion 51fbp is formed so as to surround the axis Xc passing through the center Pc, the deformed portion 51 has at least a pair of deformed portions across the axis Xc.

以上のように、本発明の実施の形態１にかかるリード端子であるソース端子５１あるいはソース端子５１を有するリードフレーム５によれば、基板４の主面に複数の半導体素子２、３が配置された半導体装置１に用いられ、複数の半導体素子２、３のそれぞれの表側の電極２ｓ、３ａと外部回路とを電気接続するためのリード端子５１であって、基板４の主面に対して略平行に配置される平坦状の主導電部５１ｍと、主導電部５１ｍに対して面の垂直方向（ｚ）に所定の間隔をあけるとともに、面の延在方向（ｘｙ）の所定位置にそれぞれ形成され、複数の半導体素子２、３のそれぞれの表側の電極２ｓ、３ａに対向するように配置される接合面Ｐ５１を有する接合面部５１ｊと、主導電部５１ｍとそれぞれの接合面Ｐ５１間に加えた圧力に応じて、それぞれの接合面Ｐ５１と主導電部５１ｍとの平行を維持しながら、当該接合面Ｐ５１と主導電部５１ｊ間の間隔が変化するように接合面部５１ｊのそれぞれと主導電部５１ｍとを連結する連結部５１ｆと、を備えるように構成した。そのため、ソース端子５１の各接合面Ｐ５１と複数の半導体素子２、３とを一括して接合する場合、各素子の高さにばらつきがあっても、加えた力に応じて、接合面Ｐ５１と電極２ｓ、３ａとの平行を保ったまま、高さを変化させることができるので、平らな面で挟んで所定の圧を加えれば、各素子に対して適切な圧力範囲の圧力をかけて接合することができる。そのため、耐熱性の高い焼結性接合技術を用いても、効率よく製造できるとともに、信頼性が高い接合が可能となる。   As described above, according to the lead frame 5 having the source terminal 51 or the source terminal 51 according to the first embodiment of the present invention, the plurality of semiconductor elements 2 and 3 are arranged on the main surface of the substrate 4. A lead terminal 51 used in the semiconductor device 1 for electrically connecting the front-side electrodes 2s, 3a of each of the plurality of semiconductor elements 2, 3 and an external circuit, which is substantially the same as the main surface of the substrate 4. A flat main conductive portion 51m arranged in parallel with a predetermined interval in the vertical direction (z) of the surface with respect to the main conductive portion 51m, and at a predetermined position in the surface extending direction (xy). The joint surface portion 51j having a joint surface P51 disposed so as to face the front-side electrodes 2s and 3a of the plurality of semiconductor elements 2 and 3, and the main conductive portion 51m and each joint surface P51 are added. To pressure Next, while maintaining the parallelism between each joint surface P51 and the main conductive portion 51m, the joint surface portion 51j and the main conductive portion 51m are connected so that the interval between the joint surface P51 and the main conductive portion 51j changes. And a connecting portion 51f to be connected. Therefore, when the bonding surfaces P51 of the source terminal 51 and the plurality of semiconductor elements 2 and 3 are bonded together, even if the heights of the elements vary, the bonding surfaces P51 and Since the height can be changed while maintaining parallel to the electrodes 2s and 3a, if a predetermined pressure is applied across a flat surface, bonding is performed by applying a pressure within an appropriate pressure range to each element. can do. For this reason, even if a sinterable bonding technique with high heat resistance is used, it is possible to manufacture efficiently and to perform bonding with high reliability.

とくに、連結部５１ｆのそれぞれには、当該連結部５１ｆが連結する接合面部５１ｊの接合面Ｐ５１の中心Ｐｃを通る接合面Ｐ５１に垂直な軸Ｘｃを挟むように、圧力に応じて変形する変形部５１ｆｂが形成されているように構成した。そのため、主導電部５１ｍと接合面Ｐ５１間に力を加えた場合、接合面Ｐ５１と主導電部５１ｍに対する平行度を維持して変形することが可能となり、接合面Ｐ５１と被接合体との圧力分布を確実に一様に保つことができる。   In particular, each of the connecting portions 51f is a deforming portion that is deformed according to pressure so as to sandwich an axis Xc perpendicular to the joining surface P51 passing through the center Pc of the joining surface P51 of the joining surface portion 51j to which the connecting portion 51f is connected. 51fb was formed. Therefore, when a force is applied between the main conductive portion 51m and the bonding surface P51, it becomes possible to deform while maintaining parallelism with respect to the bonding surface P51 and the main conductive portion 51m, and the pressure between the bonding surface P51 and the object to be bonded. The distribution can be reliably kept uniform.

また、連結部５１ｆから接合面部５１ｊにかけての部分は、それぞれ主導電部５１ｍから延在する板材を折り曲げて形成するようにしたので、容易にリード端子を形成することができる。   Further, since the portion from the connecting portion 51f to the joint surface portion 51j is formed by bending the plate material extending from the main conductive portion 51m, the lead terminal can be easily formed.

あるいは、変形例に示すように、連結部５１ｆから接合面部５１ｊにかけての部分は、それぞれ可撓性部材（例えばコイルや多孔金属材）と板材とを主導電部５１ｍの面内の所定位置に接合して形成するようにすれば、圧力範囲の制御や面圧の一様性等をより容易にコントロールできる。   Alternatively, as shown in the modified example, the portion from the connecting portion 51f to the joint surface portion 51j joins a flexible member (for example, a coil or a porous metal material) and a plate material to a predetermined position in the surface of the main conductive portion 51m. Thus, the control of the pressure range, the uniformity of the surface pressure, and the like can be more easily controlled.

可撓性部材として、軸Ｘｃを囲むように旋回するコイル材にすれば、圧力範囲の制御や面圧の一様性等を容易にコントロールできる。   If the coil member is turned so as to surround the axis Xc as the flexible member, the control of the pressure range, the uniformity of the surface pressure, and the like can be easily controlled.

また、可撓性部材として、多孔金属からなる柱状材を用いても圧力範囲の制御や面圧の一様性等を容易にコントロールできる。   Further, even when a columnar material made of porous metal is used as the flexible member, the control of the pressure range, the uniformity of the surface pressure, and the like can be easily controlled.

また、本発明の実施の形態１にかかる半導体装置１によれば、基板４と、基板４の主面に裏側の電極２ｄ、３ｃが接合された複数の半導体素子２、３と、複数の半導体素子２、３のそれぞれの表側の電極２ｓ、３ａに接合面Ｐ５１が接合された上述したリード端子であるソース端子５１あるいはソース端子５１が形成されたリードフレーム５と、を備えるように構成した。そのため、ソース端子５１の各接合面Ｐ５１と複数の半導体素子２、３とを一括して接合する場合、各素子の高さにばらつきがあっても、加えた力に応じて、接合面Ｐ５１の高さが平行移動するので、平らな面で挟んで所定の圧を加えれば、各素子に対して適切な圧力範囲の圧力をかけて接合することができる。そのため、耐熱性の高い焼結性接合技術を用いても、効率よく製造できるとともに、接合信頼性が高く、劣化が少なく長寿命となる。   Further, according to the semiconductor device 1 according to the first embodiment of the present invention, the substrate 4, the plurality of semiconductor elements 2 and 3 in which the back-side electrodes 2 d and 3 c are joined to the main surface of the substrate 4, and the plurality of semiconductors The source terminal 51 which is the above-described lead terminal in which the joint surface P51 is joined to the electrodes 2s and 3a on the front side of the elements 2 and 3, respectively, or the lead frame 5 on which the source terminal 51 is formed. Therefore, when joining each joint surface P51 of the source terminal 51 and the plurality of semiconductor elements 2 and 3 at once, even if the height of each element varies, the joint surface P51 is changed according to the applied force. Since the height moves in parallel, if a predetermined pressure is applied across a flat surface, the elements can be joined by applying a pressure in an appropriate pressure range. For this reason, even if a sinterable bonding technique with high heat resistance is used, it can be manufactured efficiently, and the bonding reliability is high, the deterioration is small, and the life is long.

とくに、表側の電極２ｓ、３ａ（あるいはそれに接合した導電板７）と接合面Ｐ５１との接合が焼結接合技術により行われたので、接合信頼性が高く、高温動作を繰り返しても劣化が少なく長寿命となる。   In particular, since the electrodes 2s, 3a (or the conductive plate 7 bonded thereto) on the front side and the bonding surface P51 are bonded by the sintering bonding technique, the bonding reliability is high and the deterioration is small even when the high temperature operation is repeated. Long service life.

実施の形態２．
本実施の形態２にかかる半導体装置では、実施の形態１と異なり、ドレイン端子にも可撓性の連結部を設け、焼結性接合材を用い、導電ブロックを介して基板とドレイン端子とを接合するようにしたものである。その他の構成については実施の形態１と同様である。図６〜図８は、本発明の実施の形態２にかかる半導体装置について説明するためのものであって、図６は半導体装置から封止体を除いた状態を仮定したもので、図６（ａ）は部分平面図、図６（ｂ）は図６（ａ）のＢ２−Ｂ２線による部分断面図である。図７は製造方法を説明するための工程に応じた半導体装置の状態を示す側面図であり、図８は製造方法を説明するためのフローチャートである。 Embodiment 2. FIG.
In the semiconductor device according to the second embodiment, unlike the first embodiment, the drain terminal is provided with a flexible connecting portion, a sinterable bonding material is used, and the substrate and the drain terminal are connected via the conductive block. It is made to join. Other configurations are the same as those in the first embodiment. 6 to 8 are for explaining the semiconductor device according to the second embodiment of the present invention, and FIG. 6 assumes a state in which the sealing body is removed from the semiconductor device, and FIG. FIG. 6A is a partial plan view, and FIG. 6B is a partial cross-sectional view taken along line B2-B2 of FIG. FIG. 7 is a side view showing the state of the semiconductor device in accordance with the steps for explaining the manufacturing method, and FIG. 8 is a flowchart for explaining the manufacturing method.

図６に示すように、本実施の形態２にかかる半導体装置１においては、ドレイン端子５２にも、主導電部５２ｍと接合面部５２ｊとを可撓性を有する連結部５２ｆで連結するように形成されている。そして、接合面部５２ｊの接合面Ｐ５２と基板４とは、半導体素子２、３の厚み（本実施の形態では半導体素子の裏面電極から導電板７までの厚み）に相当する厚みを有する導電ブロック２７を介して焼結接合部８を用いて電気接続されている。連結部５２ｆの形状は、実施の形態１と同様の条件を満たすものとしてＺ型とした。   As shown in FIG. 6, in the semiconductor device 1 according to the second embodiment, the drain terminal 52 is formed so that the main conductive portion 52m and the joint surface portion 52j are connected by a flexible connecting portion 52f. Has been. The bonding surface P52 of the bonding surface portion 52j and the substrate 4 have a thickness corresponding to the thickness of the semiconductor elements 2 and 3 (in this embodiment, the thickness from the back electrode of the semiconductor element to the conductive plate 7). Is electrically connected using the sintered joint 8. The shape of the connecting portion 52f is a Z shape that satisfies the same conditions as in the first embodiment.

なお、上記電気接続においても、実施の形態１と同様に基本的に同じ焼結性接合材料を用いて焼結接合部８を構成したが、後述する製造方法において区別するため、基板４と導電ブロック２７との接合部を８ｄ、導電ブロック２７とドレイン端子５２の接合面Ｐ５２との接合部を８ｅと称して区別する。   In the electrical connection as well, the sintered joint 8 is basically formed using the same sinterable joining material as in the first embodiment. However, in order to distinguish in the manufacturing method described later, the substrate 4 and the conductive joint are electrically conductive. The junction between the block 27 and the conductive block 27 and the drain terminal 52 is referred to as 8d and 8e, respectively.

導電ブロック２７は、焼結性接合材料を用いた接合技術によって接合可能な接合部表面状態を有する導電性ブロックであり、接合部表面は金、銀、銅であることが望ましい。このとき、導電ブロック２７材質を導電性のあるアルミニウムや銅、ニッケル、チタン、鉄等の金属材料やＣｕ−Ｍｏ、Ａｌ−ＳｉＣなどの導電性セラミック複合材料、Ｃｕ−Ｉｎｖａｒ−Ｃｕなどのクラッド材料とし、接合部表面にのみ焼結接合技術で接合可能な上記金属をめっき等によって設けてもかまわない。   The conductive block 27 is a conductive block having a joint surface state that can be joined by a joining technique using a sinterable joining material, and the joint surface is desirably gold, silver, or copper. At this time, the conductive block 27 is made of a conductive metal material such as aluminum, copper, nickel, titanium, or iron, a conductive ceramic composite material such as Cu-Mo or Al-SiC, or a clad material such as Cu-Invar-Cu. In addition, the above metal that can be bonded only to the surface of the bonded portion by the sintering bonding technique may be provided by plating or the like.

次に、上記半導体装置１を製造する方法について図７の側面図と図８のフローチャートのステップ番号を用いて説明する。
まず、図７（ａ）に示すように、基板４の半導体素子２、３および導電ブロック２７を接合する領域にペースト８Ｐを供給する（ステップＳ１１２）とともに、半導体素子２、３のソース電極２ｓ、アノード電極３ａにもペースト８Ｐを供給する（ステップＳ１２０）。そして、基板４のペースト８Ｐを供給した部分に、半導体素子２、３の裏面電極であるドレイン電極２ｄ、カソード電極３ｃ、および導電ブロック２７を合わせるように設置する。さらに、設置した半導体素子２、３のペースト８Ｐが供給された部分にそれぞれ導電板７を設置し（ステップＳ２０２）、１回目接合における被接合体とする。 Next, a method for manufacturing the semiconductor device 1 will be described using the side view of FIG. 7 and the step numbers of the flowchart of FIG.
First, as shown in FIG. 7A, a paste 8P is supplied to a region where the semiconductor elements 2 and 3 and the conductive block 27 of the substrate 4 are joined (step S112), and the source electrodes 2s of the semiconductor elements 2 and 3 are connected. The paste 8P is also supplied to the anode electrode 3a (step S120). Then, the drain electrode 2d, the cathode electrode 3c, and the conductive block 27, which are the back electrodes of the semiconductor elements 2 and 3, are installed so as to match the portion of the substrate 4 to which the paste 8P is supplied. Furthermore, the conductive plate 7 is installed in each of the portions where the paste 8P of the installed semiconductor elements 2 and 3 is supplied (step S202), and the body to be bonded in the first bonding is obtained.

その後、図７（ｂ）に示すように、被接合体を加熱プレス装置２１に挿入し、加熱プレスステージ面２１ｓと加熱プレスツール面２１ｔとで加熱加圧して、１回目接合を行う（ステップＳ３００）。このとき、半導体素子２、３、および導電ブロック２７の厚さ（基板４からの高さ）が異なる場合にも所定範囲の加圧力がかかるように、被接合体と加熱プレスツール面２１ｔとの間には、クッション性のあるシート材（緩衝部材）２２を挿入する。これにより、焼結接合部８ａ、８ｂおよび８ｄが形成され、基板４と半導体素子２、３の裏面電極２ｄ、３ｃとの電気接続、半導体素子２、３のソース電極２ｓ、アノード電極３ａと導電板７との電気接続、および基板４と導電ブロック２７との電気接続が達成され、１次組立体１Ａ１が形成される。   Then, as shown in FIG.7 (b), a to-be-joined body is inserted in the heat press apparatus 21, and it heat-presses with the heat press stage surface 21s and the heat press tool surface 21t, and performs 1st time joining (step S300). ). At this time, even when the thicknesses (height from the substrate 4) of the semiconductor elements 2, 3 and the conductive block 27 are different, a predetermined range of applied pressure is applied between the object to be bonded and the hot press tool surface 21t. A sheet material (buffer member) 22 having cushioning properties is inserted between them. As a result, sintered joints 8a, 8b and 8d are formed, and electrical connection between the substrate 4 and the back electrodes 2d and 3c of the semiconductor elements 2 and 3 and the source electrode 2s and the anode electrode 3a of the semiconductor elements 2 and 3 are electrically connected. The electrical connection with the plate 7 and the electrical connection between the substrate 4 and the conductive block 27 are achieved, and the primary assembly 1A1 is formed.

続いて、図７（ｃ）に示すようにリードフレーム５の接合面Ｐ５１、Ｐ５２にペースト８Ｐを供給する（ステップＳ１３２）。そして、１次組立体１Ａ１と加熱プレスツール面２１ｔとの間の緩衝部材２２を取り外し、導電板７とペースト８Ｐが供給された接合面Ｐ５１と、および導電ブロック２７とペースト８Ｐが供給された接合面Ｐ５２とを位置合わせしながらリードフレーム５を１次組立体１Ａ１上に設置し（ステップＳ４０２）、２回目接合における被接合体とする。その後、図７（ｄ）に示すように、再び加熱プレス装置２１にて被接合体を直接加熱加圧して２回目接合を行う。これにより、焼結接合部８ｃ、８ｅが形成され、導電板７とソース端子５１との電気接続、および導電ブロック２７とドレイン端子５２との電気接続が達成され２次組立体１Ａ２が形成される。   Subsequently, as shown in FIG. 7C, the paste 8P is supplied to the joining surfaces P51 and P52 of the lead frame 5 (step S132). Then, the buffer member 22 between the primary assembly 1A1 and the heating press tool surface 21t is removed, the bonding surface P51 supplied with the conductive plate 7 and the paste 8P, and the bonding block 27 supplied with the paste 8P. The lead frame 5 is placed on the primary assembly 1A1 while aligning with the surface P52 (step S402), and is to be joined in the second joining. Then, as shown in FIG.7 (d), the to-be-joined body is directly heat-pressed with the heat press apparatus 21, and 2nd joining is performed. Thus, the sintered joints 8c and 8e are formed, and the electrical connection between the conductive plate 7 and the source terminal 51 and the electrical connection between the conductive block 27 and the drain terminal 52 are achieved, and the secondary assembly 1A2 is formed. .

以上のように、本実施の形態２にかかる半導体装置１によれば、リードフレーム５に形成されたリード端子のうち、基板４と電気接合するためのドレイン端子５２にも、接合面部５２ｊと主導電部５２ｍとを可撓性のある連結部５２ｆで連結するように構成し。接合面Ｐ５２と基板４とを半導体素子２、３の厚みに相当する導電ブロック７を介して接合するようにしたので、ドレイン端子５２も半導体素子２、３と同時に接合できるとともに、適切な面圧範囲に制御でき、信頼性の高い接合が可能となる。とくに、ドレイン端子５２と基板４との超音波接合による接続工程を省略でき、生産性を向上させる効果がある。   As described above, according to the semiconductor device 1 of the second embodiment, among the lead terminals formed on the lead frame 5, the drain terminal 52 for electrical joining to the substrate 4 is also connected to the joint surface portion 52j. The conductive portion 52m is configured to be connected by a flexible connecting portion 52f. Since the joining surface P52 and the substrate 4 are joined via the conductive block 7 corresponding to the thickness of the semiconductor elements 2 and 3, the drain terminal 52 can be joined simultaneously with the semiconductor elements 2 and 3, and an appropriate surface pressure can be obtained. The range can be controlled and highly reliable joining is possible. In particular, the connection step by ultrasonic bonding between the drain terminal 52 and the substrate 4 can be omitted, and the productivity is improved.

実施の形態３．
本実施の形態３にかかる半導体装置は、実施の形態１および２で用いた焼結性接合技術の代わりに金属間化合物接合技術（例えば、特許文献４参照。）を用いたものである。金属間化合物接合技術とは、錫（Ｓｎ）と銀との金属間化合物（Ａｇ３Ｓｎ）層、または錫と銅との金属間化合物（Ｃｕ３Ｓｎ）層を形成することで接合するものであり、被接合面の少なくとも一方が銀または銅である必要があり、ともに銀、またはともに銅であることが望ましい。そして、被接合面の少なくとも一方に銀または銅と反応させるための錫層を形成しておく必要がある。それ以外の構成については、基本的に、実施の形態２で説明したものと同様であり、同様部分については説明を省略する。 Embodiment 3 FIG.
The semiconductor device according to the third embodiment uses an intermetallic compound bonding technique (see, for example, Patent Document 4) instead of the sinterable bonding technique used in the first and second embodiments. Intermetallic compound joining technology is a technique for joining by forming an intermetallic compound (Ag 3 Sn) layer of tin (Sn) and silver or an intermetallic compound (Cu 3 Sn) layer of tin and copper. Yes, at least one of the surfaces to be joined must be silver or copper, and it is desirable that both are silver or copper. And it is necessary to form the tin layer for making it react with silver or copper in at least one of a to-be-joined surface. Other configurations are basically the same as those described in the second embodiment, and the description of the same parts is omitted.

なお、接合層（接合部）の形成メカニズムについてはここでは省略するが、金属間化合物接合技術によって接合を行うためには、被接合面への適切な金属膜構造の形成および、適正な圧力をかけた状態で加熱処理する必要がある。そのため、金属間化合物接合技術を用いる場合でも上述したように、可撓性のある連結部で接合面部が連結されたリード端子を用いることが有効となる。あるいは、金属間化合物接合技術で形成する接合部自体の厚みは、基本的にペーストを塗布して形成した焼結接合部よりも薄くなるので、可撓性のある連結部で接合面部が連結されたリード端子を用いたときの接合信頼性の向上効果はさらに顕著になる。   Although the formation mechanism of the bonding layer (bonding portion) is omitted here, in order to perform bonding by the intermetallic compound bonding technique, an appropriate metal film structure is formed on the bonded surface and an appropriate pressure is applied. It is necessary to heat-treat in the applied state. Therefore, even when using an intermetallic compound bonding technique, as described above, it is effective to use a lead terminal in which the bonding surface portion is connected by a flexible connecting portion. Alternatively, since the thickness of the joint itself formed by the intermetallic compound joining technique is basically thinner than the sintered joint formed by applying the paste, the joint surface portion is connected by a flexible connecting portion. The effect of improving the bonding reliability when using the lead terminals becomes even more remarkable.

次に、上記半導体装置を製造する方法について、図に基づいて説明する。図９と図１０は、本発明の実施の形態３にかかる半導体装置について説明するためのものであって、図９は製造方法を説明するための工程に応じた半導体装置の状態を示す側面図であり、図１０は製造方法を説明するためのフローチャートである。なお、基板４、リードフレーム５、導電板７および導電ブロック２７の材料として、銅を用いた場合について説明する。   Next, a method for manufacturing the semiconductor device will be described with reference to the drawings. FIG. 9 and FIG. 10 are for explaining the semiconductor device according to the third embodiment of the present invention, and FIG. 9 is a side view showing the state of the semiconductor device in accordance with the steps for explaining the manufacturing method. FIG. 10 is a flowchart for explaining the manufacturing method. The case where copper is used as the material of the substrate 4, the lead frame 5, the conductive plate 7 and the conductive block 27 will be described.

まず、図９（ａ）に示すように、半導体素子２、３の主電力を流す表裏の電極（ソース電極２ｓ、ドレイン電極２ｄ、アノード電極３ａ、カソード電極３ｃ）上に、銅の金属層８１を形成し、銅の金属層８１上にさらに錫層８２を形成する（ステップＳ１２３）。さらに、銅の導電ブロック２７の基板４との接合面に錫層８２を形成する（ステップＳ１４３）。そして、基板４の所定位置に、半導体素子２、３の裏面電極であるドレイン電極２ｄ、カソード電極３ｃ、および導電ブロック２７を合わせて設置する。さらに、設置した半導体素子２、３のソース電極２ｓとアノード電極２ａ上にそれぞれ導電板７を設置し（ステップＳ２０３）、１回目接合における被接合体とする。   First, as shown in FIG. 9A, a copper metal layer 81 is formed on front and back electrodes (source electrode 2s, drain electrode 2d, anode electrode 3a, cathode electrode 3c) through which main power of semiconductor elements 2 and 3 flows. And a tin layer 82 is further formed on the copper metal layer 81 (step S123). Further, a tin layer 82 is formed on the bonding surface of the copper conductive block 27 to the substrate 4 (step S143). Then, the drain electrode 2 d, the cathode electrode 3 c, and the conductive block 27, which are back electrodes of the semiconductor elements 2 and 3, are installed at predetermined positions on the substrate 4. Further, the conductive plates 7 are respectively installed on the source electrode 2s and the anode electrode 2a of the installed semiconductor elements 2 and 3 (step S203), and are to be joined in the first bonding.

その後、図９（ｂ）に示すように、被接合体を加熱プレス装置２１に挿入し、加熱プレスステージ面２１ｓと加熱プレスツール面２１ｔとで加熱加圧して、１回目接合を行う（ステップＳ３０３）。このとき、半導体素子２、３、および導電ブロック２７の厚さ（基板４からの高さ）が異なる場合にも所定範囲の加圧力がかかるように、被接合体と加熱プレスツール面２１ｔとの間には、クッション性のあるシート材（緩衝部材）２２を挿入する。これにより、金属間化合物接合層（部）８３ａ、８３ｂおよび８３ｄが形成され、基板４と半導体素子２、３の裏面電極２ｄ、３ｃとの電気接続、半導体素子２、３のソース電極２ｓ、アノード電極３ａと導電板７との電気接続、および基板４と導電ブロック２７との電気接続が達成され、１次組立体１Ａ１が形成される。   Thereafter, as shown in FIG. 9B, the object to be joined is inserted into the heat press apparatus 21, and heated and pressurized by the heat press stage surface 21s and the heat press tool surface 21t to perform the first bonding (step S303). ). At this time, even when the thicknesses (height from the substrate 4) of the semiconductor elements 2, 3 and the conductive block 27 are different, a predetermined range of applied pressure is applied between the object to be bonded and the hot press tool surface 21t. A sheet material (buffer member) 22 having cushioning properties is inserted between them. Thus, intermetallic compound bonding layers (parts) 83a, 83b, and 83d are formed, and electrical connection between the substrate 4 and the back electrodes 2d and 3c of the semiconductor elements 2 and 3, the source electrode 2s of the semiconductor elements 2 and 3, and the anode The electrical connection between the electrode 3a and the conductive plate 7 and the electrical connection between the substrate 4 and the conductive block 27 are achieved, and the primary assembly 1A1 is formed.

続いて、図９（ｃ）に示すようにリードフレーム５の接合面Ｐ５１、Ｐ５２に錫層８２を形成する（ステップＳ１３３）。そして、１次組立体１Ａ１と加熱プレスツール面２１ｔとの間の緩衝部材２２を取り外し、導電板７と錫層８２が形成された接合面Ｐ５１と、および導電ブロック２７と錫層８２が形成された接合面Ｐ５２とを位置合わせしながらリードフレーム５を１次組立体１Ａ１上に設置し（ステップＳ４０３）、２回目接合における被接合体とする。その後、図９（ｄ）に示すように、再び加熱プレス装置２１にて被接合体を直接加熱加圧して２回目接合を行う。これにより、金属間化合物接合層（部）８３ｃ、８３ｅが形成され、導電板７とソース端子５１との電気接続、および導電ブロック２７とドレイン端子５２との電気接続が達成され２次組立体１Ａ２が形成される。   Subsequently, as shown in FIG. 9C, a tin layer 82 is formed on the joint surfaces P51 and P52 of the lead frame 5 (step S133). Then, the buffer member 22 between the primary assembly 1A1 and the heating press tool surface 21t is removed, and the joint surface P51 on which the conductive plate 7 and the tin layer 82 are formed, and the conductive block 27 and the tin layer 82 are formed. The lead frame 5 is placed on the primary assembly 1A1 while aligning with the joining surface P52 (step S403), and the joined body in the second joining is obtained. Then, as shown in FIG.9 (d), the to-be-joined body is directly heat-pressed with the heat press apparatus 21, and 2nd joining is performed. Thus, intermetallic compound bonding layers (parts) 83c and 83e are formed, and electrical connection between the conductive plate 7 and the source terminal 51 and electrical connection between the conductive block 27 and the drain terminal 52 are achieved, and the secondary assembly 1A2 is achieved. Is formed.

上記工程において、金属層８１、基板４、導電板７、導電ブロック２７、ソース端子５１およびドレイン端子５２の材料として銅をベースとした場合について説明したが、被接合面の最表面に銅がくるようにめっき等により薄膜を設けたものでもよい。その場合金属間化合物接合層はＣｕ３Ｓｎ相から形成される。また、材料として銀をベースとした場合、あるいは被接合面の最表面に銀がくるようにめっき等により薄膜が設けたもので上記工程を行った場合、金属間化合物接合層はＡｇ３Ｓｎ相から形成される。 In the above process, the case where copper is used as the material for the metal layer 81, the substrate 4, the conductive plate 7, the conductive block 27, the source terminal 51, and the drain terminal 52 has been described, but copper comes to the outermost surface of the bonded surface. A thin film may be provided by plating or the like. In that case, the intermetallic compound bonding layer is formed from a Cu 3 Sn phase. In addition, when the above process is performed when silver is used as a material, or when a thin film is provided by plating or the like so that silver comes to the outermost surface of the bonded surface, the intermetallic compound bonding layer has an Ag 3 Sn phase. Formed from.

以上のように、本実施の形態３にかかる半導体装置１によれば、主導電部５２ｍと可撓性のある連結部５１ｆで連結された接合面部５１ｊの接合面Ｐ５１と表側の電極２ｓ、３ａとの接合が金属間化合物接合技術により行われるようにした。そのため、ソース端子５１の各接合面Ｐ５１と複数の半導体素子２、３とを一括して接合する場合、各素子の高さにばらつきがあっても、加えた力に応じて、接合面Ｐ５１の高さが平行移動するので、平らな面で挟んで所定の圧を加えれば、各素子に対して適切な圧力範囲の圧力をかけて接合することができる。そのため、耐熱性の高い金属間化合物接合技術を用いても、効率よく製造できるとともに、接合信頼性が高く、劣化が少なく長寿命となる。   As described above, according to the semiconductor device 1 according to the third embodiment, the joint surface P51 of the joint surface portion 51j connected to the main conductive portion 52m and the flexible connection portion 51f and the front-side electrodes 2s, 3a. Was made by the intermetallic compound joining technique. Therefore, when joining each joint surface P51 of the source terminal 51 and the plurality of semiconductor elements 2 and 3 at once, even if the height of each element varies, the joint surface P51 is changed according to the applied force. Since the height moves in parallel, if a predetermined pressure is applied across a flat surface, the elements can be joined by applying a pressure in an appropriate pressure range. For this reason, even if an intermetallic compound bonding technique with high heat resistance is used, it can be efficiently manufactured, bonding reliability is high, deterioration is small, and a long life is achieved.

なお、上記各実施の形態１〜３では、半導体素子２、３（あるいは導電板７）と接合面Ｐ５１との接合を高耐熱技術である焼結性接合材料による焼結接合部８や金属間化合物接合材料による金属間化合物接合部８３を例に説明したが、これに限定する必要はない。例えば、はんだやろう材といったその他の材料であっても、接合面に均一な面圧を印加できるリード端子５１や５２を用いることで、信頼性の高い接合が可能となる。ただし、上述した焼結接合技術や金属間化合物接合技術のように、接合時の面圧条件が厳しい接合技術ほど、より本発明による効果を発揮することができる。   In each of the first to third embodiments, the bonding between the semiconductor elements 2 and 3 (or the conductive plate 7) and the bonding surface P51 is performed by using a sinterable bonding material 8 or a metal-to-metal bonding material, which is a high heat-resistant technology. Although the intermetallic compound joint 83 made of a compound joint material has been described as an example, it is not necessary to limit to this. For example, even other materials such as solder and brazing material can be bonded with high reliability by using the lead terminals 51 and 52 that can apply a uniform surface pressure to the bonding surface. However, the effects of the present invention can be exhibited more as the joining technique has more severe surface pressure conditions during joining, such as the above-described sintered joining technique and intermetallic compound joining technique.

また、上記各実施の形態においては、半導体素子には、炭化ケイ素によって形成されたものを示したが、これに限られることはなく、一般的に用いられているケイ素（Ｓｉ）で形成されたものであってもよい。しかし、ケイ素よりもバンドギャップが大きい、いわゆるワイドギャップ半導体を形成できる炭化ケイ素や、窒化ガリウム系材料又はダイヤモンドを用いた時の方が、動作温度が高く、より、耐熱性の高い接合技術が求められるため、本発明による効果をより一層発揮することができる。   In each of the above embodiments, the semiconductor element is formed of silicon carbide. However, the semiconductor element is not limited to this, and is formed of silicon (Si) that is generally used. It may be a thing. However, the use of silicon carbide that can form so-called wide gap semiconductors, gallium nitride-based materials, or diamond, which has a larger band gap than silicon, requires a higher operating temperature and higher heat resistance bonding technology. Therefore, the effect by this invention can be exhibited further.

１ 半導体装置、
２ スイッチング素子（ＭＯＳＦＥＴ）、 ２ｄ ドレイン電極（裏面電極）、 ２ｇ
ゲート電極（表面電極）、 ２ｓ ソース電極（表面電極）、
３ 整流素子（ＳＢＤ）、 ３ａ アノード電極（表面電極）、 ３ｃ カソード電極（裏面電極）、
４ 基板、
５ リードフレーム、 ５１ ソース端子（５１ｆ：連結部、５１ｆｂ：変形部、５１ｊ：接合面部）、 ５１ｍ 主導電部、 ５２ ドレイン端子（５２ｆ：連結部、５２ｊ：接合面部、５２ｍ：主導電部）、 ５３ 制御端子、
６ ボンディングワイヤ、 ７ 導電性金属板（導電板）、
８ 焼結接合部（接合部）、 ８３ 金属間化合物接合部（接合部）、
９ 封止樹脂（封止体）、 ２１ 加熱プレス装置、 ２２ 緩衝材、
Ｐ５１，Ｐ５２ 接合面、 Ｐｃ 接合面の中心、 Ｘｃ 接合面の中心を通る接合面に垂直な軸。 1 Semiconductor device,
2 switching element (MOSFET), 2d drain electrode (back electrode), 2g
Gate electrode (surface electrode), 2s source electrode (surface electrode),
3 rectifying element (SBD), 3a anode electrode (front surface electrode), 3c cathode electrode (back surface electrode),
4 substrates,
5 lead frame, 51 source terminal (51f: connecting portion, 51fb: deformed portion, 51j: joint surface portion), 51m main conductive portion, 52 drain terminal (52f: connecting portion, 52j: joint surface portion, 52m: main conductive portion), 53 control terminal,
6 Bonding wire, 7 Conductive metal plate (conductive plate),
8 Sintered joint (joint), 83 Intermetallic compound joint (joint),
9 sealing resin (sealing body), 21 heating press device, 22 cushioning material,
P51, P52 joint surface, center of the Pc joint surface, and axis perpendicular to the joint surface passing through the center of the Xc joint surface.

Claims (11)

基板の主面に複数の半導体素子が配置された半導体装置に用いられ、前記複数の半導体素子のそれぞれの表側の電極と外部回路とを電気接続するためのリード端子であって、
平坦状の主導電部と、
前記主導電部に対して面の垂直方向に所定の間隔をあけるとともに、面の延在方向の所定位置にそれぞれ形成され、前記複数の半導体素子のそれぞれの表側の電極に対向するように配置される接合面を有する接合面部と、
前記主導電部とそれぞれの接合面間に加えた圧力に応じて、当該接合面と前記主導電部との平行を維持しながら、当該接合面と前記主導電部間の間隔が変化するように前記接合面部のそれぞれと前記主導電部とを連結する連結部と、
を備えたことを特徴とするリード端子。 A lead terminal for use in a semiconductor device in which a plurality of semiconductor elements are arranged on a main surface of a substrate, and for electrically connecting each front-side electrode of the plurality of semiconductor elements and an external circuit,
A flat main conductive portion;
The main conductive portion is spaced apart in a direction perpendicular to the surface, is formed at a predetermined position in the surface extending direction, and is disposed so as to face each front side electrode of the plurality of semiconductor elements. A bonding surface portion having a bonding surface;
In accordance with the pressure applied between the main conductive portion and each joint surface, the interval between the joint surface and the main conductive portion is changed while maintaining the parallelness between the joint surface and the main conductive portion. A connecting portion that connects each of the joint surface portions and the main conductive portion;
A lead terminal comprising: 前記連結部のそれぞれには、当該連結部が連結する接合面部の中心を通る当該接合面部に垂直な軸を挟むように、前記圧力に応じて変形する変形部が形成されていることを特徴とする請求項１に記載のリード端子。   Each of the connecting portions is formed with a deforming portion that deforms according to the pressure so as to sandwich an axis perpendicular to the joining surface portion passing through the center of the joining surface portion to which the connecting portion is connected. The lead terminal according to claim 1. 前記連結部および前記接合面部は、それぞれ前記主導電部から延在する板材を折り曲げて形成したものであることを特徴とする請求項１または２に記載のリード端子。   3. The lead terminal according to claim 1, wherein each of the connecting portion and the joint surface portion is formed by bending a plate material extending from the main conductive portion. 前記連結部および前記接合面部は、それぞれ前記主導電部の面内の所定位置に可撓性部材を介して板材を接合して形成したものであることを特徴とする請求項１または２に記載のリード端子。   The said connection part and the said joint surface part are each formed by joining a board | plate material via the flexible member in the predetermined position in the surface of the said main electroconductive part. Lead terminal. 前記可撓性部材は、前記軸を囲むように旋回するコイル材であることを特徴とする請求項４に記載のリード端子。   The lead terminal according to claim 4, wherein the flexible member is a coil material that turns so as to surround the shaft. 前記可撓性部材は、多孔金属からなる柱状材であることを特徴とする請求項４に記載のリード端子。   The lead terminal according to claim 4, wherein the flexible member is a columnar material made of a porous metal. 基板と、
前記基板の主面に裏側の電極が接合された複数の半導体素子と、
前記複数の半導体素子のそれぞれの表側の電極に前記接合面が接合された請求項１ないし６のいずれか１項に記載のリード端子と、
を備えたことを特徴とする半導体装置。 A substrate,
A plurality of semiconductor elements in which electrodes on the back side are bonded to the main surface of the substrate;
The lead terminal according to any one of claims 1 to 6, wherein the bonding surface is bonded to an electrode on a front side of each of the plurality of semiconductor elements.
A semiconductor device comprising: 前記表側の電極と前記接合面との接合が焼結接合技術により行われたことを特徴とする請求項７に記載の半導体装置。   The semiconductor device according to claim 7, wherein the front-side electrode and the bonding surface are bonded by a sintering bonding technique. 前記表側の電極と前記接合面との接合が金属間化合物接合技術により行われたことを特徴とする請求項７に記載の半導体装置。   The semiconductor device according to claim 7, wherein the front-side electrode and the bonding surface are bonded by an intermetallic compound bonding technique. 前記縦型半導体素子がワイドバンドギャップ半導体材料により形成されていることを特徴とする請求項７ないし９のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 7, wherein the vertical semiconductor element is made of a wide band gap semiconductor material. 前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンド、のうちのいずれかであることを特徴とする請求項１０に記載の半導体装置。   The semiconductor device according to claim 10, wherein the wide band gap semiconductor material is any one of silicon carbide, a gallium nitride-based material, and diamond.
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