JP2013120914A - Manufacturing method of circuit device - Google Patents

Manufacturing method of circuit device Download PDF

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Publication number
JP2013120914A
JP2013120914A JP2011269548A JP2011269548A JP2013120914A JP 2013120914 A JP2013120914 A JP 2013120914A JP 2011269548 A JP2011269548 A JP 2011269548A JP 2011269548 A JP2011269548 A JP 2011269548A JP 2013120914 A JP2013120914 A JP 2013120914A
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Prior art keywords
circuit board
sealing resin
mold
cavity
resin
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JP2011269548A
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Hideyuki Sakamoto
英行 坂本
Mamoru Ando
守 安藤
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit device which enables a space below a circuit board to be resin sealed without causing voids.SOLUTION: In a manufacturing method of a circuit device of this invention, a gate 58 is provided at a lower mold 54 below a circuit board 14, and a sealing resin 16 is injected from the gate 58 into a cavity 56. In this structure, the sealing resin 16 injected from the gate 58 fills a small region below the circuit board 14 first and then reaches the entire cavity 56. Thus, the occurrence of voids in this region is prevented.

Description

本発明は、上面に回路素子が組み込まれた回路基板を樹脂封止する回路装置の製造方法に関する。   The present invention relates to a method for manufacturing a circuit device in which a circuit board having a circuit element incorporated on an upper surface is sealed with a resin.

トランジスタやチップ素子から成る混成集積回路が上面に組み込まれた回路基板を封止する方法としては、ケース材を用いた封止方法と、樹脂により樹脂封止する方法が有る。   As a method for sealing a circuit board in which a hybrid integrated circuit including transistors and chip elements is incorporated on the upper surface, there are a sealing method using a case material and a resin sealing method using a resin.

ケース材を用いた場合では、中空部を備えた蓋状のケース材を回路基板に嵌合させることで、回路基板の上面に形成された混成集積回路を、ケース材の中空部に収納する。   In the case of using the case material, the hybrid integrated circuit formed on the upper surface of the circuit board is accommodated in the hollow part of the case material by fitting the lid-like case material provided with the hollow part to the circuit board.

樹脂封止が採用された場合は、金型を用いた射出成形により回路基板の上面に形成された混成集積回路が被覆される。図4(A)を参照して、樹脂封止された混成集積回路装置100の構成を説明する。混成集積回路装置100では、先ず、アルミニウム等の金属から成る回路基板101の上面が全面的に絶縁層102により被覆されている。そして、絶縁層102の上面に形成された導電パターン103に回路素子が接続されて所定の混成集積回路が構成されている。回路基板101の上面に配置される素子としては、金属細線107により接続された半導体素子105Aとチップ素子105Bが図示されている。回路基板101の端部では、パッド状の導電パターン103にリード104が固着されている。   When resin sealing is employed, the hybrid integrated circuit formed on the upper surface of the circuit board is covered by injection molding using a mold. With reference to FIG. 4A, the structure of the resin-encapsulated hybrid integrated circuit device 100 will be described. In the hybrid integrated circuit device 100, first, the upper surface of the circuit board 101 made of a metal such as aluminum is entirely covered with the insulating layer 102. A circuit element is connected to the conductive pattern 103 formed on the upper surface of the insulating layer 102 to constitute a predetermined hybrid integrated circuit. As elements disposed on the upper surface of the circuit board 101, a semiconductor element 105A and a chip element 105B connected by a thin metal wire 107 are illustrated. A lead 104 is fixed to the pad-like conductive pattern 103 at the end of the circuit board 101.

封止樹脂106は熱可塑性樹脂であり、回路基板101の上面、側面および下面を被覆している。ここで、回路基板101の上面に形成された回路素子から発生した熱を、回路基板101を経由して良好に外部に放出させるためには、回路基板101の下面を被覆する封止樹脂106を薄くすることが有効である。しかしながら、回路基板101の下面を被覆する封止樹脂106の厚みを例えば0.5mm程度に薄く設定すると、回路基板101の下面が部分的に封止樹脂106により被覆されない問題が発生する。この理由は、金型を用いて封止樹脂106を射出成形する工程にて、回路基板101の下面と金型の内壁下面との間隙が狭くなり、この間隙に十分に封止樹脂が行き渡らなくなるからである。   The sealing resin 106 is a thermoplastic resin, and covers the upper surface, side surface, and lower surface of the circuit board 101. Here, in order to release heat generated from the circuit elements formed on the upper surface of the circuit board 101 to the outside through the circuit board 101, a sealing resin 106 that covers the lower surface of the circuit board 101 is used. Thinning is effective. However, if the thickness of the sealing resin 106 that covers the lower surface of the circuit board 101 is set to be as thin as, for example, about 0.5 mm, there arises a problem that the lower surface of the circuit board 101 is not partially covered with the sealing resin 106. This is because the gap between the lower surface of the circuit board 101 and the lower surface of the inner wall of the mold is narrowed in the step of injection molding the sealing resin 106 using a mold, and the sealing resin does not sufficiently reach the gap. Because.

この問題を回避するための方法を、図4(B)を参照して説明する(下記特許文献1)。ここでは、支持部材110により回路基板101を下面から支持した状態でインジェクションモールドを行っている。具体的には、支持部材110は熱可塑性樹脂から成り、内側の面は回路基板101の下面および側面の一部に当接するサイズである。また、支持部材110の外側の面は金型112の内壁下面および側面に接触する大きさとなっている。従って、支持部材110により支持された状態の回路基板101を金型112のキャビティ114に収納させると、回路基板101の下面と金型112の内壁下面との間隙に支持部材110が位置する。この状態で、熱可塑性樹脂をキャビティ114に注入することにより、回路基板101の樹脂封止が行われる。この方法によると、回路基板101の下面と金型112の内壁下面との間隙には支持部材110が位置しており、この間隙に液状の熱硬化性樹脂を注入する必要がないので、回路基板101の下面が部分的に被覆されないことによるボイドの発生が防止される。また、樹脂封止時の注入圧から金属細線等を保護するために、回路素子が被覆されるように回路基板101の上面にポッティング樹脂120が形成されている。   A method for avoiding this problem will be described with reference to FIG. 4B (Patent Document 1 below). Here, the injection molding is performed with the support member 110 supporting the circuit board 101 from the lower surface. Specifically, the support member 110 is made of a thermoplastic resin, and the inner surface has a size that contacts the lower surface and part of the side surface of the circuit board 101. Further, the outer surface of the support member 110 is in contact with the inner wall lower surface and side surfaces of the mold 112. Therefore, when the circuit board 101 supported by the support member 110 is stored in the cavity 114 of the mold 112, the support member 110 is positioned in the gap between the lower surface of the circuit board 101 and the lower surface of the inner wall of the mold 112. In this state, the circuit board 101 is resin-sealed by injecting a thermoplastic resin into the cavity 114. According to this method, since the support member 110 is located in the gap between the lower surface of the circuit board 101 and the lower surface of the inner wall of the mold 112, it is not necessary to inject liquid thermosetting resin into the gap. Generation of voids due to the lower surface of 101 not being partially covered is prevented. In addition, a potting resin 120 is formed on the upper surface of the circuit board 101 so as to cover the circuit elements in order to protect the fine metal wires and the like from the injection pressure during resin sealing.

特許第3316449号公報Japanese Patent No. 3316449

しかしながら、図4(B)を参照して、支持部材110を排除して通常のトランスファーモールドを行う場合、封止樹脂がキャビティ114に注入されるゲートは、回路基板101の側方に設けられる。従って、回路基板101の側方からキャビティ114に注入された封止樹脂は、回路基板101の上方に優先的に流動してしまい、回路基板101の下方の空間をボイド無く樹脂封止することが困難な問題があった。   However, referring to FIG. 4B, when performing normal transfer molding with the support member 110 removed, the gate into which the sealing resin is injected into the cavity 114 is provided on the side of the circuit board 101. Therefore, the sealing resin injected into the cavity 114 from the side of the circuit board 101 flows preferentially above the circuit board 101, and the space below the circuit board 101 can be resin-sealed without voids. There was a difficult problem.

本発明は上記した問題点を鑑みて成されたものであり、本発明の目的は、回路基板の下方の空間をボイド無く樹脂封止することを可能とする回路装置の製造方法を提供することにある。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method of manufacturing a circuit device that enables resin-sealing of the space below the circuit board without voids. It is in.

本発明の回路装置の製造方法は、上面に回路素子が実装された回路基板をモールド金型のキャビティに収納する工程と、前記キャビティに封止樹脂を注入することにより前記回路基板を前記封止樹脂で被覆する工程と、を有し、前記被覆する工程では、前記回路基板の下方から前記キャビティに前記封止樹脂を注入することを特徴とする。   The method of manufacturing a circuit device according to the present invention includes a step of storing a circuit board having a circuit element mounted on an upper surface in a cavity of a mold, and sealing the circuit board by injecting a sealing resin into the cavity. Coating with resin, and in the coating step, the sealing resin is injected into the cavity from below the circuit board.

本発明によれば、回路基板の下方からキャビティに封止樹脂を注入するので、回路基板の下面とモールド金型との間隙が薄い場合であっても、この間隙に確実に封止樹脂を充填させてボイドの発生を抑制することができる。   According to the present invention, since the sealing resin is injected into the cavity from below the circuit board, even when the gap between the lower surface of the circuit board and the mold is thin, the sealing resin is surely filled into the gap. Thus, generation of voids can be suppressed.

本発明の製造方法で製造される回路装置を示す図であり、(A)は斜視図であり、(B)および(C)は断面図である。It is a figure which shows the circuit apparatus manufactured with the manufacturing method of this invention, (A) is a perspective view, (B) and (C) are sectional drawings. 本発明の回路装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を示す図であり、(A)は使用されるモールド金型を示す平面図であり、(B)はその断面図である。It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is a top view which shows the mold metal mold | die used, (B) is the sectional drawing. 背景技術の回路装置の製造方法を示す図であり、(A)は製造される混成集積回路装置を示す断面図であり、(B)は樹脂封止工程を示す断面図である。It is a figure which shows the manufacturing method of the circuit device of background art, (A) is sectional drawing which shows the hybrid integrated circuit device manufactured, (B) is sectional drawing which shows the resin sealing process.

図1を参照して、本形態が適用される混成集積回路装置10の構成を説明する。図1(A)は混成集積回路装置10の斜視図であり、図1(B)は図1(A)のB−B’線に於ける断面図であり、(C)はC−C’線に於ける断面図である。   A configuration of a hybrid integrated circuit device 10 to which the present exemplary embodiment is applied will be described with reference to FIG. 1A is a perspective view of the hybrid integrated circuit device 10, FIG. 1B is a sectional view taken along line BB ′ of FIG. 1A, and FIG. 1C is CC ′. It is sectional drawing in a line.

混成集積回路装置10は、回路基板14の上面に、導電パターン22と回路素子から成る混成集積回路が組み込まれ、この回路と電気的に接続されたリード24が外部に導出している。更に、回路基板14の上面に構築された混成集積回路、回路基板14の上面、側面および下面は、熱硬化性樹脂から成る封止樹脂16により一体的に被覆されている。   In the hybrid integrated circuit device 10, a hybrid integrated circuit composed of a conductive pattern 22 and circuit elements is incorporated on the upper surface of the circuit board 14, and leads 24 electrically connected to the circuit are led out to the outside. Furthermore, the hybrid integrated circuit constructed on the upper surface of the circuit board 14, and the upper surface, side surfaces, and lower surface of the circuit board 14 are integrally covered with a sealing resin 16 made of a thermosetting resin.

回路基板14は、アルミニウムや銅等の金属から成る基板であり、具体的な大きさは、例えば縦×横×厚さ=61mm×42mm×1mm程度である。ここで、回路基板14の材料として金属以外が採用されても良く、例えば、セラミックや樹脂材料が回路基板14の材料として採用されても良い。   The circuit board 14 is a board made of a metal such as aluminum or copper, and its specific size is, for example, about vertical × horizontal × thickness = 61 mm × 42 mm × 1 mm. Here, a material other than metal may be employed as the material of the circuit board 14, and for example, ceramic or resin material may be employed as the material of the circuit board 14.

絶縁層26は、フィラーが高充填されたエポキシ樹脂から成り、回路基板14の表面全域を覆うように形成されている。   The insulating layer 26 is made of an epoxy resin highly filled with a filler, and is formed so as to cover the entire surface of the circuit board 14.

導電パターン22は厚みが50μm程度の銅等の金属膜から成り、所定の電気回路が実現されるように絶縁層26の表面に形成される。また、リード24が導出する辺に、導電パターン22からなるパッドが形成される。   The conductive pattern 22 is made of a metal film such as copper having a thickness of about 50 μm, and is formed on the surface of the insulating layer 26 so as to realize a predetermined electric circuit. A pad made of the conductive pattern 22 is formed on the side from which the lead 24 is led out.

半導体素子28およびチップ素子30(回路素子)は、半田等の接合材を介して、導電パターン22の所定の箇所に固着されている。半導体素子28としては、トランジスタ、LSIチップ、ダイオード等が採用される。ここでは、半導体素子28と導電パターン22とは、金属細線34を経由して接続される。チップ素子30としては、チップ抵抗やチップコンデンサ等が採用され、両端の電極は半田等の接合材を介して導電パターン22に固着されている。また、半導体素子28が、多量の熱を放出するパワー系の素子である場合は、厚さが数ミリ程度の金属片から成るヒートシンクを介して回路基板14の上面に固着される。   The semiconductor element 28 and the chip element 30 (circuit element) are fixed to predetermined portions of the conductive pattern 22 through a bonding material such as solder. As the semiconductor element 28, a transistor, an LSI chip, a diode, or the like is employed. Here, the semiconductor element 28 and the conductive pattern 22 are connected via a thin metal wire 34. As the chip element 30, a chip resistor, a chip capacitor, or the like is employed, and electrodes at both ends are fixed to the conductive pattern 22 via a bonding material such as solder. Further, when the semiconductor element 28 is a power element that emits a large amount of heat, the semiconductor element 28 is fixed to the upper surface of the circuit board 14 via a heat sink made of a metal piece having a thickness of about several millimeters.

リード24は、回路基板14の周辺部に設けられたパッドに固着され、入力信号や出力信号が通過する外部接続端子として機能している。図1(B)を参照すると、回路基板14の対向する2つの辺に沿って多数個のリード24が設けられているが、1つの側辺または4つの側辺に沿ってリード24が配置されても良い。   The lead 24 is fixed to a pad provided in the peripheral portion of the circuit board 14 and functions as an external connection terminal through which an input signal and an output signal pass. Referring to FIG. 1B, a large number of leads 24 are provided along two opposing sides of the circuit board 14, but the leads 24 are arranged along one side or four sides. May be.

封止樹脂16は、熱硬化性樹脂を用いるトランスファーモールドにより形成される。図1(B)では、封止樹脂16により、導電パターン22、半導体素子28、チップ素子30、金属細線34が封止されている。更に、回路基板14の上面、側面および下面が封止樹脂16により被覆されている。   The sealing resin 16 is formed by transfer molding using a thermosetting resin. In FIG. 1B, the conductive pattern 22, the semiconductor element 28, the chip element 30, and the fine metal wire 34 are sealed with the sealing resin 16. Further, the upper surface, the side surface, and the lower surface of the circuit board 14 are covered with the sealing resin 16.

更に、図1(A)を参照して、紙面上にて左右方向に対向する封止樹脂16の側面中間部に固定部19が設けられている。固定部19は、平面視で封止樹脂16の側面を略半円状に内側に窪ませた部位であり、この部分にビス等の固定手段が配置されることで、封止樹脂16の下面がヒートシンク等の放熱体に当接される。   Further, referring to FIG. 1 (A), a fixing portion 19 is provided at an intermediate portion of the side surface of the sealing resin 16 facing in the left-right direction on the paper surface. The fixing portion 19 is a portion in which the side surface of the sealing resin 16 is recessed inward in a substantially semicircular shape in plan view, and a fixing means such as a screw is disposed in this portion, so that the lower surface of the sealing resin 16 Is brought into contact with a heat sink such as a heat sink.

図1(B)を参照して、回路基板14の下面を被覆する封止樹脂16の厚みL1は、例えば0.1mm以上0.3mm以下である。回路基板14の下面を被覆する封止樹脂16をこの様に薄くすることにより、封止樹脂16の熱抵抗が低減され、半導体素子28から発生した熱が、回路基板14および封止樹脂16を経由して良好に外部に放出される。   Referring to FIG. 1B, the thickness L1 of the sealing resin 16 covering the lower surface of the circuit board 14 is, for example, not less than 0.1 mm and not more than 0.3 mm. By thinning the sealing resin 16 covering the lower surface of the circuit board 14 in this way, the thermal resistance of the sealing resin 16 is reduced, and the heat generated from the semiconductor element 28 causes the circuit board 14 and the sealing resin 16 to move. It is released to the outside through

課題欄にて説明したように、通常のトランスファーモールドにより回路基板14の下面を被覆することは容易では無いが、本願発明では、後述するようにトランスファーモールドの工程において回路基板14の下方から封止樹脂を注入することにより、回路基板14の下面を薄く且つボイドが無い状態で被覆している。   As described in the problem column, it is not easy to cover the lower surface of the circuit board 14 with a normal transfer mold. However, in the present invention, sealing is performed from below the circuit board 14 in the transfer molding process as described later. By injecting the resin, the lower surface of the circuit board 14 is thinly coated with no voids.

図2および図3を参照して、次に、上記した構成の混成集積回路装置の製造方法を説明する。図2はトランスファーモールドを行う工程を示す断面図であり、図3はトランスファーモールドで用いられる金型を示す平面図である。   Next, a method for manufacturing a hybrid integrated circuit device having the above-described configuration will be described with reference to FIGS. FIG. 2 is a cross-sectional view showing a process for performing transfer molding, and FIG. 3 is a plan view showing a mold used in the transfer molding.

本工程では、先ず、トランスファーモールドに用いられる上金型52および下金型54から成る金型50を用意する。   In this step, first, a mold 50 including an upper mold 52 and a lower mold 54 used for transfer molding is prepared.

金型50は、上金型52と下金型54から成り、両者を当接させることでキャビティ56が形成される。上金型52にはイジェクトピン62が配置されており、キャビティ56に樹脂が注入される際にはイジェクトピン62の下面は上金型52の内壁と同一平面上に配置されている。そして、キャビティ56の内部で硬化した後に、イジェクトピン62を下方に移動させることで、封止樹脂が離型される。   The mold 50 includes an upper mold 52 and a lower mold 54, and a cavity 56 is formed by bringing both into contact. An eject pin 62 is disposed on the upper mold 52, and when the resin is injected into the cavity 56, the lower surface of the eject pin 62 is disposed on the same plane as the inner wall of the upper mold 52. And after hardening inside the cavity 56, the sealing resin is released by moving the eject pin 62 downward.

一方、下金型54には、キャビティ56の下方に対応する部分に、ゲート58およびポッド61が配置されている。ゲート58の位置としては回路基板14の中心の下方が好適であり、これによりキャビティ56の全体に満遍なく封止樹脂16を行き渡らせることができる。また、ここでは1つのみのゲート58が設けられているが、回路基板14の下方に複数のゲート58が設けられても良い。ポッド61はゲート58の下方に配置され、その内部には固化された熱硬化性樹脂から成るタブレット59が配置され、このタブレット59はプランジャー63により上方に押圧される構成となっている。   On the other hand, in the lower mold 54, a gate 58 and a pod 61 are arranged in a portion corresponding to the lower part of the cavity 56. The position of the gate 58 is preferably below the center of the circuit board 14, so that the sealing resin 16 can be spread evenly throughout the cavity 56. Although only one gate 58 is provided here, a plurality of gates 58 may be provided below the circuit board 14. The pod 61 is disposed below the gate 58, and a tablet 59 made of a solidified thermosetting resin is disposed inside the pod 61, and the tablet 59 is pressed upward by a plunger 63.

また、本工程においては、金型50はタブレット59が溶融される温度以上に過熱されている。   In this step, the mold 50 is heated to a temperature higher than the temperature at which the tablet 59 is melted.

具体的な封止方法は、先ず、半導体素子等の回路素子が配置された回路基板14を下金型54に配置し、下金型54に上金型52を当接させることで形成されるキャビティ56の内部に回路基板14を収納する。また、回路基板14の両側辺に固定されたリード24が上金型52および下金型54で挟持されることにより、キャビティ56の内部に於ける回路基板14の位置が固定される。   A specific sealing method is formed by first placing the circuit board 14 on which circuit elements such as semiconductor elements are arranged in the lower mold 54 and bringing the upper mold 52 into contact with the lower mold 54. The circuit board 14 is accommodated in the cavity 56. Further, the lead 24 fixed to both sides of the circuit board 14 is sandwiched between the upper mold 52 and the lower mold 54, thereby fixing the position of the circuit board 14 in the cavity 56.

ここで、本工程においては、回路基板14の下方に設けたゲート58から液状の封止樹脂16を注入するので、何ら対策を施さなければ、この注入圧により回路基板14が上方に移動してしまう恐れがある。本形態では、上金型52および下金型54で、リード24を狭持することにより、回路基板14のキャビティ56の内部に於ける位置を固定している。従って、ゲート58から封止樹脂16が注入されることにより、回路基板14を上方に持ち上げるような圧力が作用したとしても、回路基板14の過度の移動は抑制されている。また、回路基板14の移動を確実に防止するために、上金型52の内壁から回路基板14の上面に当接する当接ピンを設けても良い。   Here, in this step, since the liquid sealing resin 16 is injected from the gate 58 provided below the circuit board 14, the circuit board 14 moves upward by this injection pressure unless any countermeasure is taken. There is a risk. In this embodiment, the position within the cavity 56 of the circuit board 14 is fixed by holding the lead 24 between the upper mold 52 and the lower mold 54. Accordingly, even if the pressure that lifts the circuit board 14 is applied by injecting the sealing resin 16 from the gate 58, excessive movement of the circuit board 14 is suppressed. Further, in order to reliably prevent the circuit board 14 from moving, a contact pin that contacts the upper surface of the circuit board 14 from the inner wall of the upper mold 52 may be provided.

次に、ポッド61に投入されたタブレット59を加熱することより、液状または半固形の封止樹脂16とする。その後、プランジャー63を上昇させることにより、ゲート58を経由して封止樹脂16をキャビティ56に注入する。   Next, the tablet 59 put in the pod 61 is heated to obtain a liquid or semi-solid sealing resin 16. Thereafter, the plunger 63 is raised to inject the sealing resin 16 into the cavity 56 via the gate 58.

ゲート58から注入された封止樹脂16は、先ず、紙面上左右方向に分岐した後に回路基板14の周辺部に向かって流動し、回路基板14と下金型54内壁との間の間隙に充填される。次に、封止樹脂16の側方の領域に封止樹脂16が充填され、その後、回路基板14の上方に領域に封止樹脂16が充填され回路素子も被覆される。   The sealing resin 16 injected from the gate 58 first branches in the left-right direction on the paper and then flows toward the periphery of the circuit board 14 to fill the gap between the circuit board 14 and the inner wall of the lower mold 54. Is done. Next, the sealing resin 16 is filled in a region on the side of the sealing resin 16, and then the sealing resin 16 is filled in the region above the circuit board 14 to cover the circuit element.

金型50の左右両端部にエアベントが設けられており、封止樹脂16の注入に伴い、キャビティ56の内部の空気はエアベントを介して外部に放出される。   Air vents are provided at the left and right ends of the mold 50, and the air inside the cavity 56 is released to the outside through the air vent as the sealing resin 16 is injected.

キャビティ56に充分に封止樹脂16が充填された後は、エポキシ樹脂等の熱硬化性樹脂から成る封止樹脂16を充分に加熱硬化させた後に、上金型52と下金型54とを離型する。更に、イジェクトピン62を下方に降下させることにより、封止樹脂16の上面を下方に押圧し、封止樹脂16を上金型52の内壁から分離させる。   After the cavity 56 is sufficiently filled with the sealing resin 16, the sealing resin 16 made of a thermosetting resin such as an epoxy resin is sufficiently heated and cured, and then the upper mold 52 and the lower mold 54 are moved. Release. Further, by lowering the eject pin 62 downward, the upper surface of the sealing resin 16 is pressed downward, and the sealing resin 16 is separated from the inner wall of the upper mold 52.

本工程では、回路基板14の下方の領域で下金型54にゲート58を設け、このゲート58からキャビティ56に封止樹脂16を注入している。従って、回路基板14と下金型54との間隙が非常に狭い場合であっても、ゲート58から注入された封止樹脂16は、最初にこの間隙に注入されるので、回路基板14の下方の領域に封止樹脂16が良好に充填されボイドの発生が抑制されている。   In this step, a gate 58 is provided in the lower mold 54 in a region below the circuit board 14, and the sealing resin 16 is injected from the gate 58 into the cavity 56. Therefore, even when the gap between the circuit board 14 and the lower mold 54 is very narrow, the sealing resin 16 injected from the gate 58 is first injected into this gap. This region is filled with the sealing resin 16 satisfactorily, and generation of voids is suppressed.

図3(A)を参照して、上記工程で用いる金型50の構成を更に説明する。金型50には複数のキャビティ56が設けられ、ここでは、一例として、2列×4行で8個のキャビティ56が金型50に設けられており、各キャビティ56に回路基板14が収納されており、各回路基板14の下方にゲート58が設けられている。   With reference to FIG. 3 (A), the structure of the metal mold | die 50 used at the said process is further demonstrated. The mold 50 is provided with a plurality of cavities 56. Here, as an example, eight cavities 56 in 2 columns × 4 rows are provided in the mold 50, and the circuit board 14 is accommodated in each cavity 56. A gate 58 is provided below each circuit board 14.

図3(B)を参照して、本工程では、各キャビティ56の下方に、封止樹脂を供給するポッド61およびゲート58が設けられている。このようにすることで、各キャビティ56に所定量の封止樹脂を充分に供給することが可能となる。   Referring to FIG. 3B, in this step, a pod 61 and a gate 58 for supplying sealing resin are provided below each cavity 56. By doing so, a predetermined amount of sealing resin can be sufficiently supplied to each cavity 56.

上記工程が終了した後は、リード24を所定の形状や長さに成形する工程、内蔵される混成集積回路装置の特性を検査する工程を経て、図1に示す混成集積回路装置10が製造される。   After the above steps are completed, the hybrid integrated circuit device 10 shown in FIG. 1 is manufactured through a step of forming the lead 24 into a predetermined shape and length and a step of inspecting the characteristics of the built-in hybrid integrated circuit device. The

10 混成集積回路装置
14 回路基板
16 封止樹脂
19 固定部
22 導電パターン
24 リード
26 絶縁層
28 半導体素子
30 チップ素子
34 金属細線
50 金型
52 上金型
54 下金型
56 キャビティ
58 ゲート
59 タブレット
61 ポッド
62 イジェクトピン
63 プランジャー
DESCRIPTION OF SYMBOLS 10 Hybrid integrated circuit device 14 Circuit board 16 Sealing resin 19 Fixed part 22 Conductive pattern 24 Lead 26 Insulating layer 28 Semiconductor element 30 Chip element 34 Metal fine wire 50 Mold 52 Upper mold 54 Lower mold 56 Cavity 58 Gate 59 Tablet 61 Pod 62 Eject pin 63 Plunger

Claims (5)

上面に回路素子が実装された回路基板をモールド金型のキャビティに収納する工程と、
前記キャビティに封止樹脂を注入することにより前記回路基板を前記封止樹脂で被覆する工程と、を有し、
前記被覆する工程では、前記回路基板の下方から前記キャビティに前記封止樹脂を注入することを特徴とする回路装置の製造方法。
Storing a circuit board having circuit elements mounted on the upper surface in a cavity of a mold,
Coating the circuit board with the sealing resin by injecting a sealing resin into the cavity, and
In the covering step, the sealing resin is injected into the cavity from below the circuit board.
前記被覆する工程では、前記回路基板の下面と前記モールド金型の内壁との距離が所定の長さとされた状態で、前記封止樹脂が前記キャビティに注入されることを特徴とする請求項1に記載の回路装置の製造方法。   The sealing resin is injected into the cavity in a state where the distance between the lower surface of the circuit board and the inner wall of the mold is a predetermined length in the covering step. A method for manufacturing the circuit device according to 1. 前記封止樹脂が注入されるゲートを、前記回路基板の中心部の下方に配置することを特徴とする請求項1または請求項2に記載の回路装置の製造方法。   The method for manufacturing a circuit device according to claim 1, wherein the gate into which the sealing resin is injected is disposed below a center portion of the circuit board. 前記キャビティの側方に設けたエアベントから、前記キャビティの内部の空気を外部に放出させることを特徴とする請求項1から請求項3の何れかに記載の回路装置の製造方法。   The method for manufacturing a circuit device according to claim 1, wherein air inside the cavity is discharged to the outside from an air vent provided on a side of the cavity. 前記金型には複数の前記キャビティが設けられ、
前記複数のキャビティの各々で、前記回路基板の下方に対応する領域に前記封止樹脂が注入されるゲートを設けることを特徴とする請求項1から請求項4の何れかに記載の回路装置の製造方法。
The mold is provided with a plurality of the cavities,
5. The circuit device according to claim 1, wherein each of the plurality of cavities is provided with a gate into which the sealing resin is injected in a region corresponding to a lower portion of the circuit board. Production method.
JP2011269548A 2011-12-09 2011-12-09 Manufacturing method of circuit device Ceased JP2013120914A (en)

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Citations (9)

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JPS609131A (en) * 1983-06-29 1985-01-18 Fujitsu Ltd Method for resin sealing of semiconductor device and apparatus thereof
JPH05102217A (en) * 1991-10-02 1993-04-23 Hitachi Ltd Semiconductor device, manufacture thereof and molding apparatus used therefor
JPH0758271A (en) * 1993-08-20 1995-03-03 Mitsubishi Electric Corp Lead frame for semiconductor device and manufacture of semiconductor device using same
JPH07147294A (en) * 1993-11-25 1995-06-06 Tamusu Technol Kk Resin packaging method and device therefor
JPH07183318A (en) * 1993-12-22 1995-07-21 Toyota Motor Corp Electronic circuit device and manufacture thereof
JPH0888292A (en) * 1994-09-19 1996-04-02 Shinko Electric Ind Co Ltd One side resin-sealed semiconductor package, one side-resin sealed semiconductor device and manufacture thereof
JP2004087672A (en) * 2002-08-26 2004-03-18 Denso Corp Resin-sealed type semiconductor device and its manufacturing method
JP2009158781A (en) * 2007-12-27 2009-07-16 Teikoku Tsushin Kogyo Co Ltd Method for mounting electronic component on circuit board
JP2011054623A (en) * 2009-08-31 2011-03-17 Sanyo Electric Co Ltd Circuit device and method for manufacturing the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609131A (en) * 1983-06-29 1985-01-18 Fujitsu Ltd Method for resin sealing of semiconductor device and apparatus thereof
JPH05102217A (en) * 1991-10-02 1993-04-23 Hitachi Ltd Semiconductor device, manufacture thereof and molding apparatus used therefor
JPH0758271A (en) * 1993-08-20 1995-03-03 Mitsubishi Electric Corp Lead frame for semiconductor device and manufacture of semiconductor device using same
JPH07147294A (en) * 1993-11-25 1995-06-06 Tamusu Technol Kk Resin packaging method and device therefor
JPH07183318A (en) * 1993-12-22 1995-07-21 Toyota Motor Corp Electronic circuit device and manufacture thereof
JPH0888292A (en) * 1994-09-19 1996-04-02 Shinko Electric Ind Co Ltd One side resin-sealed semiconductor package, one side-resin sealed semiconductor device and manufacture thereof
JP2004087672A (en) * 2002-08-26 2004-03-18 Denso Corp Resin-sealed type semiconductor device and its manufacturing method
JP2009158781A (en) * 2007-12-27 2009-07-16 Teikoku Tsushin Kogyo Co Ltd Method for mounting electronic component on circuit board
JP2011054623A (en) * 2009-08-31 2011-03-17 Sanyo Electric Co Ltd Circuit device and method for manufacturing the same

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