JP2012178404A - Circuit device and manufacturing method thereof - Google Patents

Circuit device and manufacturing method thereof Download PDF

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JP2012178404A
JP2012178404A JP2011039672A JP2011039672A JP2012178404A JP 2012178404 A JP2012178404 A JP 2012178404A JP 2011039672 A JP2011039672 A JP 2011039672A JP 2011039672 A JP2011039672 A JP 2011039672A JP 2012178404 A JP2012178404 A JP 2012178404A
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circuit board
board
mounting
opening
circuit
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Masaru Kanakubo
優 金久保
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Semiconductor Components Industries LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

PROBLEM TO BE SOLVED: To provide a circuit device in which thermal interference is mitigated.SOLUTION: A hybrid integrated circuit device 10A includes a circuit board 12, a control element 28 and a chip element 24 which are disposed on an upper surface of the circuit board 12, an opening 18 which is formed by partially opening the circuit board 12, a package board 28 which closes the opening 18 from a lower surface, a power element 22 which is packaged on an upper surface of the package board 28, and a space 26 which separates the package board 28 and the circuit board 12. Since the package board 28 and the circuit board 12 are separated by the spacer 26, even if the power element 22 packaged on the package board 28 generates heat under an operational situation, thermal influences to be exerted upon the control element 23 packaged on the circuit board 12 are reduced.

Description

本発明は回路装置およびその製造方法に関し、特に、放熱性が向上された回路装置およびその製造方法に関するものである。   The present invention relates to a circuit device and a manufacturing method thereof, and more particularly to a circuit device having improved heat dissipation and a manufacturing method thereof.

図８を参照して、従来型の回路装置の一例として混成集積回路装置１００の構成を説明する（特許文献１）。先ず、アルミニウム等の金属からなる基板１０１の表面には、樹脂から成る絶縁層１０２を介して導電パターン１０３が形成され、この導電パターン１０３の所望の箇所に回路素子が固着されて、所定の電気回路が形成される。ここでは、回路素子として半導体素子１０５Ａとチップ素子１０５Ｂが採用されている。半導体素子１０５Ａは、例えばトランジスタまたはダイオードであり、上面の電極が金属細線１０７を経由して所定の導電パターン１０３と接続され、裏面の電極は導電パターン１０３に接続されている。一方、コンデンサまたは抵抗器であるチップ素子１０５Ｂは、両端の電極が半田等の接合材１０６を介して所定の導電パターン１０３と接合されている。また、封止樹脂１０８は、基板１０１の表面に形成された電気回路を封止する機能を有する。更に、リード１０９は装置全体の外部接続端子として機能し、内側の端部はパッド状に形成された導電パターン１０３に固着され、外側の端部は封止樹脂１０８から外部に導出する。   With reference to FIG. 8, a configuration of a hybrid integrated circuit device 100 will be described as an example of a conventional circuit device (Patent Document 1). First, a conductive pattern 103 is formed on the surface of a substrate 101 made of a metal such as aluminum via an insulating layer 102 made of resin, and a circuit element is fixed to a desired portion of the conductive pattern 103 so that a predetermined electric circuit is formed. A circuit is formed. Here, a semiconductor element 105A and a chip element 105B are employed as circuit elements. The semiconductor element 105 </ b> A is, for example, a transistor or a diode, and the electrode on the upper surface is connected to the predetermined conductive pattern 103 via the metal thin wire 107, and the electrode on the back surface is connected to the conductive pattern 103. On the other hand, the chip element 105B, which is a capacitor or a resistor, has electrodes at both ends bonded to a predetermined conductive pattern 103 via a bonding material 106 such as solder. In addition, the sealing resin 108 has a function of sealing an electric circuit formed on the surface of the substrate 101. Furthermore, the lead 109 functions as an external connection terminal of the entire device, the inner end is fixed to the conductive pattern 103 formed in a pad shape, and the outer end is led out from the sealing resin 108 to the outside.

この様な構成の混成集積回路装置１００は、金属からなる基板１０１の上面に各回路素子が実装されるので、動作状況下にて半導体素子１０５Ａが発熱しても、発生した熱は基板１０１を経由して良好に外部に放出される。   In the hybrid integrated circuit device 100 having such a configuration, each circuit element is mounted on the upper surface of the substrate 101 made of metal. Therefore, even if the semiconductor element 105A generates heat under an operating condition, the generated heat is applied to the substrate 101. It is released to the outside through

特開２００７−０３６０１４号公報JP 2007-036014 A

しかしながら、数十アンペア程度の大電流のスイッチングを行うパワー素子等を回路素子として採用した場合、上記した構成の混成集積回路装置１００でも放熱性が不十分な問題があった。   However, when a power element or the like that switches a large current of about several tens of amperes is employed as a circuit element, the hybrid integrated circuit device 100 having the above-described configuration has a problem of insufficient heat dissipation.

具体的には、例えば半導体素子１０５Ａから発生された熱が外部に至る経路は、導電パターン１０３、絶縁層１０２、基板１０１、封止樹脂１０８の順番である。この中でも、導電パターン１０３、基板１０１は金属から成るので熱伝導率は良いが、絶縁層１０２および封止樹脂１０８はエポキシ樹脂等の樹脂材料から成るので熱伝導性が悪い。このように、半導体素子１０５Ａの熱が外部に放出される経路に、樹脂からなる部分が含まれることが、放熱性の更なる向上を阻害していた。   Specifically, for example, the path through which the heat generated from the semiconductor element 105A reaches the outside is the order of the conductive pattern 103, the insulating layer 102, the substrate 101, and the sealing resin 108. Among these, since the conductive pattern 103 and the substrate 101 are made of metal, the thermal conductivity is good. However, since the insulating layer 102 and the sealing resin 108 are made of a resin material such as an epoxy resin, the thermal conductivity is bad. As described above, the fact that the portion made of resin is included in the path through which the heat of the semiconductor element 105A is released to the outside has hindered further improvement in heat dissipation.

また、基板１０１の下面を外部に露出させると、裏面を被覆していた封止樹脂１０８が無くなる分、放熱性が向上する。しかしながら、この場合であっても、基板１０１の上面を被覆する絶縁層１０２が、熱の経路に存在するので、放熱性の向上に限界があった。更に、絶縁層１０２自体の熱伝導率を向上させるために、絶縁層１０２はシリカ等の無機フィラーを含むが、この様な対策を施しても絶縁層１０２の熱伝導率は金属には劣る。   Further, when the lower surface of the substrate 101 is exposed to the outside, the heat dissipation is improved by the amount of the sealing resin 108 covering the back surface. However, even in this case, since the insulating layer 102 covering the upper surface of the substrate 101 exists in the heat path, there is a limit to improvement in heat dissipation. Furthermore, in order to improve the thermal conductivity of the insulating layer 102 itself, the insulating layer 102 contains an inorganic filler such as silica, but even if such measures are taken, the thermal conductivity of the insulating layer 102 is inferior to that of a metal.

更にまた、半導体素子１０５Ａの動作時の発熱量が特に大きい場合、発生した熱が基板１０１を経由してチップ素子１０５Ｂ等に伝導し、この結果、高温と成ったチップ素子１０５Ｂの特性が劣化してしまう問題もあった。   Furthermore, when the amount of heat generated during the operation of the semiconductor element 105A is particularly large, the generated heat is conducted to the chip element 105B and the like via the substrate 101, and as a result, the characteristics of the chip element 105B at a high temperature deteriorate. There was also a problem.

本発明は上記した問題を鑑みて成されたものであり、本発明の主たる目的は、放熱性が高く且つ回路素子同士の熱干渉が抑制された回路装置およびその製造方法を提供することにある。   The present invention has been made in view of the above-described problems, and a main object of the present invention is to provide a circuit device that has high heat dissipation and suppresses thermal interference between circuit elements, and a method for manufacturing the circuit device. .

本発明の回路装置は、上面に導電パターンが配置された回路基板と、前記回路基板を部分的に開口した開口部と、前記開口部と重畳するように前記回路基板の下方に配置された実装基板と、前記実装基板の上面に配置されて前記導電パターンと電気的に接続された半導体素子と、を備え、前記実装基板の一部を前記回路基板から離間させることを特徴とする。   The circuit device of the present invention includes a circuit board having a conductive pattern disposed on an upper surface, an opening partly opening the circuit board, and a mounting part disposed below the circuit board so as to overlap the opening part. And a semiconductor element disposed on an upper surface of the mounting board and electrically connected to the conductive pattern, wherein a part of the mounting board is separated from the circuit board.

本発明の回路装置の製造方法は、上面に導電パターンが配置されると共に開口部が設けられた回路基板を用意し、半導体素子が上面に実装された実装基板を、前記開口部と重畳する位置で前記回路基板の下方に配置する工程と、金型のキャビティに前記回路基板および前記実装基板を収納し、前記回路基板の上面、側面および下面の周辺部を封止樹脂で被覆する工程と、を備え、前記実装基板を前記回路基板から離間させることで、前記実装基板と前記回路基板との間に間隙を形成し、前記間隙を経由して前記封止樹脂を流動させることを特徴とする。   In the method for manufacturing a circuit device according to the present invention, a circuit board having a conductive pattern disposed on an upper surface and an opening is prepared, and a mounting substrate on which a semiconductor element is mounted is overlapped with the opening. And placing the circuit board and the mounting board in a cavity of a mold, and covering peripheral portions of the upper surface, side surfaces, and lower surface of the circuit board with a sealing resin, A gap is formed between the mounting board and the circuit board by separating the mounting board from the circuit board, and the sealing resin is caused to flow through the gap. .

本発明によれば、発熱体である半導体素子が実装される実装基板と回路基板とを離間させている。これにより、回路基板と実装基板とが熱的に分離されるので、実装基板に実装された半導体素子が発熱しても、発生した熱は回路基板には殆ど伝導しない。この結果、回路基板に配置された小信号系の半導体素子等が過熱されることによる誤動作が抑止される。   According to the present invention, the mounting substrate on which the semiconductor element as the heating element is mounted is separated from the circuit substrate. As a result, the circuit board and the mounting board are thermally separated, so that even if the semiconductor element mounted on the mounting board generates heat, the generated heat is hardly conducted to the circuit board. As a result, malfunction due to overheating of the small signal semiconductor elements and the like arranged on the circuit board is suppressed.

更に本発明によれば、熱伝導性に優れた材料からなる実装基板を回路基板とは別体で配置し、この実装基板の上面に半導体素子を実装している。これにより、半導体素子から発生した熱は、熱伝導性に優れる実装基板を経由して直ちに外部に放出される。従って、動作時の半導体素子の過熱が抑制され、その誤動作や特性低下が抑制される。   Furthermore, according to the present invention, the mounting board made of a material having excellent thermal conductivity is arranged separately from the circuit board, and the semiconductor element is mounted on the upper surface of the mounting board. As a result, heat generated from the semiconductor element is immediately released to the outside through the mounting substrate having excellent thermal conductivity. Therefore, overheating of the semiconductor element during operation is suppressed, and its malfunction and characteristic deterioration are suppressed.

更に、製法上に於いては、開口部を塞ぐ実装基板と回路基板との間に間隙が存在するので、樹脂封止の工程において、両者の間に存在する間隙を経由して封止樹脂が流通するように成る。この結果、回路基板の開口部および回路基板の下面に封止樹脂が良好に充填され、未重点領域であるボイドの出現が抑制される。   Further, in the manufacturing method, there is a gap between the mounting board and the circuit board that closes the opening, and therefore in the resin sealing process, the sealing resin is passed through the gap that exists between the two. Becomes in circulation. As a result, the opening portion of the circuit board and the lower surface of the circuit board are satisfactorily filled with the sealing resin, and the appearance of voids that are unweighted regions is suppressed.

本発明の回路装置を示す図であり、（Ａ）は斜視図であり、（Ｂ）は断面図であり、（Ｃ）は実装基板を示す斜視図である。It is a figure which shows the circuit apparatus of this invention, (A) is a perspective view, (B) is sectional drawing, (C) is a perspective view which shows a mounting substrate. 本発明の回路装置を示す図であり、（Ａ）−（Ｃ）は他の形態の混成集積回路装置を示す断面図である。It is a figure which shows the circuit apparatus of this invention, (A)-(C) is sectional drawing which shows the hybrid integrated circuit device of another form. 本発明の回路装置を示す図であり、（Ａ）−（Ｂ）は他の形態の混成集積回路装置を示す断面図である。It is a figure which shows the circuit device of this invention, (A)-(B) is sectional drawing which shows the hybrid integrated circuit device of another form. 本発明の他の形態の回路装置を示す図であり、（Ａ）は断面図であり、（Ｂ）は拡大された平面図であり、（Ｃ）は拡大された断面図である。It is a figure which shows the circuit device of the other form of this invention, (A) is sectional drawing, (B) is the expanded top view, (C) is the expanded sectional view. 本発明の他の形態の回路装置を示す断面図である。It is sectional drawing which shows the circuit apparatus of the other form of this invention. 本形態の回路装置の熱抵抗を測定した結果を示すグラフである。It is a graph which shows the result of having measured the thermal resistance of the circuit device of this form. 本形態の回路装置の製造方法を示す図であり、（Ａ）は本工程を示す断面図であり、（Ｂ）は部分的に拡大して示す断面図であり、（Ｃ）は実装基板の部分を示す平面図であり、（Ｄ）は他の形態の回路装置を樹脂封止する状態を示す断面図である。It is a figure which shows the manufacturing method of the circuit device of this form, (A) is sectional drawing which shows this process, (B) is sectional drawing which expands partially, (C) is a mounting substrate. It is a top view which shows a part, (D) is sectional drawing which shows the state which carries out resin sealing of the circuit device of another form. 背景技術の混成集積回路装置を示す断面図である。It is sectional drawing which shows the hybrid integrated circuit device of background art.

図１を参照して、本発明の回路装置の一例として混成集積回路装置１０Ａの構成を説明する。図１（Ａ）は混成集積回路装置１０Ａを示す斜視図であり、図１（Ｂ）はその断面図であり、図１（Ｃ）は実装基板を抜き出して示す斜視図である。   With reference to FIG. 1, the configuration of a hybrid integrated circuit device 10A will be described as an example of the circuit device of the present invention. FIG. 1A is a perspective view showing a hybrid integrated circuit device 10A, FIG. 1B is a cross-sectional view thereof, and FIG. 1C is a perspective view showing an extracted mounting substrate.

図１（Ａ）および図１（Ｂ）を参照して、混成集積回路装置１０Ａは、導電パターン１６および回路素子から成る混成集積回路が上面に組み込まれた回路基板１２と、回路基板１２を部分的に開口した開口部１８と、開口部１８と重畳する様に回路基板１２の下方に配置された実装基板２８と、実装基板２８に実装されたパワー素子２２（半導体素子）とを備えている。更に本形態では、パワー素子２２が実装される実装基板２８と回路基板１２との間にスペーサ２６を配置することにより、両者を離間させている。   Referring to FIGS. 1A and 1B, a hybrid integrated circuit device 10A includes a circuit board 12 in which a hybrid integrated circuit composed of a conductive pattern 16 and circuit elements is incorporated on an upper surface, and a circuit board 12 partially An opening 18 that is open, a mounting substrate 28 disposed below the circuit board 12 so as to overlap the opening 18, and a power element 22 (semiconductor element) mounted on the mounting substrate 28. . Furthermore, in this embodiment, the spacers 26 are arranged between the mounting board 28 on which the power element 22 is mounted and the circuit board 12 so that they are separated from each other.

具体的には、回路基板１２は、回路素子を相互に接続するための導電パターン１６が上面に形成された基板である。回路基板１２の材料としては、ガラスエポキシ樹脂等の樹脂材料、セラミック基板またはアルミニウム等の金属基板が採用される。また、金属基板が回路基板１２として採用される場合は、アルミナ等のフィラーが充填された樹脂からなる絶縁層により回路基板１２の上面が被覆され、この絶縁層の上面に導電パターン１６が形成される。回路基板１２の具体的な大きさは、例えば、縦×横＝６０ｍｍ×８０ｍｍ程度であり、厚みは１．０ｍｍ〜２．０ｍｍ程度である。   Specifically, the circuit board 12 is a board on which a conductive pattern 16 for connecting circuit elements to each other is formed on the upper surface. As a material of the circuit board 12, a resin material such as glass epoxy resin, a ceramic substrate, or a metal substrate such as aluminum is employed. When a metal substrate is employed as the circuit board 12, the upper surface of the circuit board 12 is covered with an insulating layer made of a resin filled with a filler such as alumina, and a conductive pattern 16 is formed on the upper surface of the insulating layer. The The specific size of the circuit board 12 is, for example, about vertical × horizontal = 60 mm × 80 mm, and the thickness is about 1.0 mm to 2.0 mm.

導電パターン１６は厚みが３５μｍ〜７０μｍ程度の銅等の金属から成り、所定の電気回路が形成されるように回路基板１２の上面に形成される。導電パターン１６は、回路素子が固着されるアイランド、金属細線が接続されるパッド、リード１４が固着されるパッドおよび、これらを相互に接続する配線部等を備える。ここでは単層の導電パターン１６が図示されているが、絶縁層を介して積層された多層の導電パターン１６が回路基板１２の上面に形成されても良い。   The conductive pattern 16 is made of a metal such as copper having a thickness of about 35 μm to 70 μm, and is formed on the upper surface of the circuit board 12 so as to form a predetermined electric circuit. The conductive pattern 16 includes an island to which circuit elements are fixed, a pad to which a thin metal wire is connected, a pad to which a lead 14 is fixed, and a wiring portion that connects these to each other. Although a single-layer conductive pattern 16 is shown here, a multilayer conductive pattern 16 laminated via an insulating layer may be formed on the upper surface of the circuit board 12.

導電パターン１６に電気的に接続される回路素子としては、能動素子や受動素子を全般的に採用することができる。具体的には、トランジスタ、ＬＳＩチップ、ダイオード、チップ抵抗、チップコンデンサ、インダクタンスなどを回路素子として採用することができる。図１（Ａ）を参照すると、回路基板１２の上面には、制御素子２３（ＬＳＩ）、チップ素子２４等が回路基板１２の上面に固着されている。一方、ＭＯＳＦＥＴ等であるパワー素子２２は、開口部１８の内部に配置されており、この事項は図１（Ｂ）を参照して後述する。   As a circuit element electrically connected to the conductive pattern 16, an active element or a passive element can be generally employed. Specifically, transistors, LSI chips, diodes, chip resistors, chip capacitors, inductances, and the like can be employed as circuit elements. Referring to FIG. 1A, a control element 23 (LSI), a chip element 24 and the like are fixed to the upper surface of the circuit board 12 on the upper surface of the circuit board 12. On the other hand, the power element 22 such as a MOSFET is disposed inside the opening 18, and this matter will be described later with reference to FIG.

封止樹脂３０は、回路基板１２およびその上面に固着された回路素子を封止するように形成されている。封止樹脂３０は、フィラーが混入されたエポキシ樹脂等の熱硬化性樹脂から成り、トランスファーモールドにより形成される。   The sealing resin 30 is formed so as to seal the circuit board 12 and the circuit elements fixed to the upper surface thereof. The sealing resin 30 is made of a thermosetting resin such as an epoxy resin mixed with a filler, and is formed by transfer molding.

リード１４は、回路基板１２の対向する側辺に沿って、導電パターン１６から成るパッドに固着されており、混成集積回路装置１０Ａの入出力端子として機能している。図１（Ａ）を参照すると、紙面上にて右側の回路基板１２の側辺に沿って多数のリード１４が設けられているが、対向する２つの側辺に沿ってリード１４が固着されても良い。   The lead 14 is fixed to a pad made of the conductive pattern 16 along the opposite side of the circuit board 12 and functions as an input / output terminal of the hybrid integrated circuit device 10A. Referring to FIG. 1A, a large number of leads 14 are provided along the side of the right circuit board 12 on the paper surface, but the leads 14 are fixed along two opposing sides. Also good.

開口部１８は回路基板１２を部分的に開口した部位であり、パワー素子２２を収納可能な大きさで四角形形状を呈している。開口部１８の平面視での大きさは、例えば、縦×横＝０．４ｃｍ以上１．２ｃｍ以下である。このような開口部１８は、回路基板１２に対してプレス加工または研削加工を施すことで形成される。   The opening 18 is a part where the circuit board 12 is partially opened, and has a rectangular shape with a size that can accommodate the power element 22. The size of the opening 18 in plan view is, for example, length × width = 0.4 cm or more and 1.2 cm or less. Such an opening 18 is formed by subjecting the circuit board 12 to pressing or grinding.

実装基板２８は、回路基板１２の開口部１８と重畳する領域で回路基板１２の下方に配置された基板であり、回路基板１２よりも熱伝導性に優れ且つ電気的には絶縁性の材料から成る。実装基板２８の具体的な材料としては、例えばセラミック基板が採用される。実装基板２８の平面視での大きさは、開口部１８よりも若干大きい程度であり、縦×横＝０．５ｃｍ以上１．５ｃｍ以下である。回路基板１２の材料であるエポキシ樹脂の熱伝導率が０．２〔Ｗ・ｍ−１・Ｋ−１〕であるのに対し、実装基板２８の材料であるセラミックの熱伝導率は３０〔Ｗ・ｍ−１・Ｋ−１〕である。また、実装基板２８の下面は封止樹脂３０から外部に露出している。図１（Ａ）を参照すると、回路基板１２に２つの開口部１８が設けられ、これらの開口部１８にパワー素子２２が配置されている。また、ここでは、開口部１８の全域を下方から覆うように実装基板２８が回路基板１２の下面に当接しているが、開口部１８を部分的に覆うように実装基板２８が設けられても良い。 The mounting substrate 28 is a substrate disposed below the circuit board 12 in a region overlapping with the opening 18 of the circuit board 12, and is superior in thermal conductivity than the circuit board 12 and is made of an electrically insulating material. Become. As a specific material of the mounting substrate 28, for example, a ceramic substrate is employed. The size of the mounting substrate 28 in plan view is slightly larger than the opening 18, and the length × width = 0.5 cm or more and 1.5 cm or less. The thermal conductivity of the epoxy resin that is the material of the circuit board 12 is 0.2 [W · m −1 · K −1 ], whereas the thermal conductivity of the ceramic that is the material of the mounting board 28 is 30 [W · M -1 · K -1 ]. Further, the lower surface of the mounting substrate 28 is exposed to the outside from the sealing resin 30. Referring to FIG. 1A, two openings 18 are provided in the circuit board 12, and a power element 22 is disposed in these openings 18. Here, the mounting board 28 is in contact with the lower surface of the circuit board 12 so as to cover the entire area of the opening 18 from below, but the mounting board 28 may be provided so as to partially cover the opening 18. good.

実装基板２８の上面には、銅などの金属箔を所定形状にパターニングした配線パターン３２が形成されている。パワー素子２２の下面に形成された電極は、半田等の導電性固着材を介して、配線パターン３２と接続される。   On the upper surface of the mounting substrate 28, a wiring pattern 32 is formed by patterning a metal foil such as copper into a predetermined shape. The electrode formed on the lower surface of the power element 22 is connected to the wiring pattern 32 via a conductive fixing material such as solder.

実装基板２８の上面に実装されるパワー素子２２は、例えば１アンペア以上の大電流が通過する半導体素子であり、具体的には、ＭＯＳＦＥＴ、ＩＧＢＴ、バイポーラトランジスタまたはダイオードが採用される。これらの複数が実装基板２８に実装されても良い。   The power element 22 mounted on the upper surface of the mounting substrate 28 is a semiconductor element through which a large current of, for example, 1 ampere or more passes, and specifically, a MOSFET, IGBT, bipolar transistor, or diode is employed. A plurality of these may be mounted on the mounting board 28.

パワー素子２２としてＭＯＳＦＥＴが採用された場合は、パワー素子２２の下面にドレイン電極が配置され、上面にソース電極およびゲート電極が設けられる。一方、パワー素子２２としてＩＧＢＴが採用された場合は、下面にコレクタ電極が設けられ、上面にエミッタ電極およびゲート電極が配置される。また、パワー素子２２としてバイポーラトランジスタが採用された場合は、下面にコレクタ電極が設けられ、上面にエミッタ電極およびベース電極が配置される。   When a MOSFET is adopted as the power element 22, a drain electrode is disposed on the lower surface of the power element 22, and a source electrode and a gate electrode are provided on the upper surface. On the other hand, when IGBT is adopted as power element 22, a collector electrode is provided on the lower surface, and an emitter electrode and a gate electrode are disposed on the upper surface. When a bipolar transistor is adopted as the power element 22, a collector electrode is provided on the lower surface, and an emitter electrode and a base electrode are disposed on the upper surface.

実装基板２８の上面に配置されたパワー素子２２は、金属細線２０を経由して回路基板１２の上面に形成された導電パターン１６と接続される。具体的には、例えばパワー素子２２がＭＯＳＦＥＴの場合、パワー素子２２の上面に設けられたソース電極およびゲート電極は、金属細線２０を経由して回路基板１２の上面に形成された導電パターン１６から成るパッドに接続される。一方、パワー素子２２の下面に設けられたドレイン電極は、先ず、半田を介してランド形状の配線パターン３２に電気的に接続される。そして、この配線パターン３２は、金属細線２０を経由して、回路基板１２の上面に形成されたパッド状の導電パターン１６と接続される。   The power element 22 disposed on the upper surface of the mounting substrate 28 is connected to the conductive pattern 16 formed on the upper surface of the circuit substrate 12 through the fine metal wires 20. Specifically, for example, when the power element 22 is a MOSFET, the source electrode and the gate electrode provided on the upper surface of the power element 22 are formed from the conductive pattern 16 formed on the upper surface of the circuit board 12 via the fine metal wire 20. Connected to the pad. On the other hand, the drain electrode provided on the lower surface of the power element 22 is first electrically connected to the land-shaped wiring pattern 32 via solder. The wiring pattern 32 is connected to the pad-like conductive pattern 16 formed on the upper surface of the circuit board 12 through the fine metal wire 20.

図１（Ｂ）を参照して、本形態では、実装基板２８の上面と回路基板１２の下面との間にスペーサ２６を配置している。スペーサ２６は、厚みが０．２ｍｍ以上０．５ｍｍ以下程度であり、実装基板２８と回路基板１２とを離間させて両者の間に間隙を形成する働きを有する。実装基板２８の上面と回路基板１２の下面とが離間する距離は、スペーサ２６の厚みと同等である。スペーサ２６の材料としては、エポキシ樹脂等の樹脂材料、セラミック等が採用可能である。   Referring to FIG. 1B, in this embodiment, a spacer 26 is disposed between the upper surface of the mounting substrate 28 and the lower surface of the circuit board 12. The spacer 26 has a thickness of about 0.2 mm to 0.5 mm, and has a function of separating the mounting board 28 and the circuit board 12 to form a gap therebetween. The distance at which the upper surface of the mounting substrate 28 and the lower surface of the circuit board 12 are separated is equal to the thickness of the spacer 26. As the material of the spacer 26, a resin material such as an epoxy resin, ceramic, or the like can be used.

図１（Ｃ）を参照すると、細長い直方体形状を呈する２本のスペーサ２６が、実装基板２８の対向する２つの側辺に沿って周辺部に配置されている。この様なスペーサ２６が、実装基板２８と回路基板１２との間に介在することにより、両者が均等に離間される。ここで、スペーサ２６の形状は図示以外の形状でも良く、例えば、実装基板２８の側辺に沿って離散的にスペーサ２６が配置されても良い。   Referring to FIG. 1C, two spacers 26 having an elongated rectangular parallelepiped shape are arranged in the peripheral portion along two opposing side edges of the mounting substrate 28. Since such a spacer 26 is interposed between the mounting board 28 and the circuit board 12, they are evenly spaced from each other. Here, the shape of the spacer 26 may be a shape other than the illustrated shape. For example, the spacers 26 may be discretely arranged along the side of the mounting substrate 28.

スペーサ２６で実装基板２８と回路基板１２とを離間させることにより、パワー素子２２が他の素子に与える悪影響が低減される。具体的には、大電流のスイッチングを行うパワー素子２２が動作時に発熱すると、発熱した熱は実装基板２８に伝導するが、スペーサ２６により離間されている回路基板１２にはそれほど伝導しない。従って、過熱により誤動作しやすい制御素子２３が回路基板１２の上面に実装されていても、パワー素子２２から発生した熱は回路基板１２には伝導しないので、パワー素子２２の発熱に起因して制御素子２３が過熱されることによる誤動作が抑制される。   By separating the mounting board 28 and the circuit board 12 by the spacer 26, the adverse effect of the power element 22 on other elements is reduced. Specifically, when the power element 22 that switches large current generates heat during operation, the generated heat is conducted to the mounting board 28, but is not conducted so much to the circuit board 12 separated by the spacer 26. Therefore, even if the control element 23 that is likely to malfunction due to overheating is mounted on the upper surface of the circuit board 12, the heat generated from the power element 22 is not conducted to the circuit board 12. A malfunction due to the element 23 being overheated is suppressed.

更に、上記した本形態の混成集積回路装置１０Ａによれば、パワー素子２２から発生した熱を効率的に外部に放出させることができる。具体的には、本形態では、パワー素子２２が配置される箇所を開口して開口部１８を設け、この開口部を塞ぐように配置された実装基板２８の上面にパワー素子２２を固着している。これにより、パワー素子２２が動作時に発生する熱は、配線パターン３２および実装基板２８を経由して良好に外部に放出される。従来例では、図８を参照すると、放熱の経路に基板１０１の上面を被覆する絶縁層１０２や、基板１０１の下面を覆う封止樹脂１０８が存在しており、これらの熱伝導性が悪いことによって放熱性が阻害されていたが、本形態ではこの様な樹脂材料（有機材料）が放熱の経路に存在していない。即ち、パワー素子２２の放熱の経路に存在するのは、金属からなる配線パターン３２およびセラミックから成る実装基板２８の無機材料のみであり、これらの熱伝導率は上記したように非常に良い。更に、パワー素子２２の固着に用いられる半田も放熱の経路となるが、半田は錫等から成る金属材料であるので、樹脂材料と比較すると熱伝導性に優れている。更にまた、実装基板２８は回路基板１２よりも薄く形成されているので、その分熱抵抗が小さくなる。以上の理由により、パワー素子２２が動作時に発生した熱は直ちに外部に放出されるので、パワー素子２２が過熱されることによる破壊や特性劣化が抑制されている。   Furthermore, according to the hybrid integrated circuit device 10A of the present embodiment described above, the heat generated from the power element 22 can be efficiently released to the outside. Specifically, in this embodiment, a portion where the power element 22 is disposed is opened to provide an opening 18, and the power element 22 is fixed to the upper surface of the mounting substrate 28 disposed so as to close the opening. Yes. As a result, heat generated during operation of the power element 22 is favorably released to the outside via the wiring pattern 32 and the mounting substrate 28. In the conventional example, referring to FIG. 8, the insulating layer 102 covering the upper surface of the substrate 101 and the sealing resin 108 covering the lower surface of the substrate 101 exist in the heat dissipation path, and their thermal conductivity is poor. However, in this embodiment, such a resin material (organic material) is not present in the heat dissipation path. That is, only the inorganic material of the wiring pattern 32 made of metal and the mounting board 28 made of ceramic exists in the heat dissipation path of the power element 22, and their thermal conductivity is very good as described above. Further, the solder used for fixing the power element 22 also serves as a heat dissipation path. However, since the solder is a metal material made of tin or the like, it has better thermal conductivity than the resin material. Furthermore, since the mounting board 28 is formed thinner than the circuit board 12, the thermal resistance is reduced accordingly. For the above reason, heat generated during operation of the power element 22 is immediately released to the outside, so that destruction and characteristic deterioration due to overheating of the power element 22 are suppressed.

一方、回路基板１２の上面には、発熱量が多いパワー素子２２は載置されず、パワー素子２２のスイッチングを制御する制御素子２３やチップ素子２４等の発熱量が比較的小さい素子のみが配置される。従って、放熱性に劣るが安価なガラスエポキシ基板を回路基板１２として採用でき、コストダウンが図れる。更に、ガラスエポキシ基板は加工性に優れた材料であるので、容易に開口部１８を形成できる。   On the other hand, the power element 22 that generates a large amount of heat is not placed on the upper surface of the circuit board 12, and only elements that generate a relatively small amount of heat such as the control element 23 and the chip element 24 that control the switching of the power element 22 are arranged. Is done. Therefore, an inexpensive glass epoxy substrate that is inferior in heat dissipation can be adopted as the circuit board 12, and the cost can be reduced. Furthermore, since the glass epoxy substrate is a material excellent in workability, the opening 18 can be easily formed.

更にまた、混成集積回路装置１０Ａでは、背景技術で述べた絶縁破壊の問題が回避される。具体的には、本形態では、実装基板２８自体が絶縁材料であるセラミックから成るので、実装基板２８と配線パターン３２との間に、絶縁破壊を起こしやすい樹脂からなる絶縁層を設ける必要が無い。また、配線パターン３２に、１０００Ｖ〜２０００Ｖ程度の電圧を印加しても、セラミックから成る実装基板２８は絶縁破壊を起こし難い。この様な理由により、装置全体の耐圧性が向上されている。   Furthermore, in the hybrid integrated circuit device 10A, the problem of dielectric breakdown described in the background art is avoided. Specifically, in this embodiment, since the mounting substrate 28 itself is made of ceramic which is an insulating material, it is not necessary to provide an insulating layer made of a resin that easily causes dielectric breakdown between the mounting substrate 28 and the wiring pattern 32. . Further, even when a voltage of about 1000 V to 2000 V is applied to the wiring pattern 32, the ceramic mounting substrate 28 is unlikely to cause dielectric breakdown. For this reason, the pressure resistance of the entire apparatus is improved.

図２を参照して、他の形態の混成集積回路装置の構成を説明する。図２（Ａ）−図２（Ｃ）に示す混成集積回路装置１０Ｂ−１０Ｄの構成は、上述した装置と基本的には同様であり、相違点は、実装基板２８にパワー素子２２が実装される構造にある。以下では相違点を中心に説明する。   With reference to FIG. 2, the configuration of another form of hybrid integrated circuit device will be described. The configuration of the hybrid integrated circuit device 10B-10D shown in FIGS. 2A to 2C is basically the same as that of the above-described device. The difference is that the power element 22 is mounted on the mounting substrate 28. It is in the structure. Below, it demonstrates centering around difference.

図２（Ａ）に示す混成集積回路装置１０Ｂでは、実装基板２８の裏面が封止樹脂３０により被覆される。このようにすることで、パワー素子２２から発生した熱の経路に封止樹脂３０が存在することに成るので、放熱性が若干低下する。しかしながら、実装基板２８の下面も被覆されるように封止樹脂３０を形成することにより、実装基板２８と封止樹脂３０との界面が外部に露出しないので、その界面を経由して水分が内部に侵入することが抑制され、耐湿性が向上する。また、下記する他の形態に関しても、このように実装基板２８も被覆されるように樹脂封止を行っても良い。   In the hybrid integrated circuit device 10 </ b> B shown in FIG. 2A, the back surface of the mounting substrate 28 is covered with the sealing resin 30. By doing in this way, since the sealing resin 30 exists in the path | route of the heat | fever which generate | occur | produced from the power element 22, heat dissipation is reduced a little. However, by forming the sealing resin 30 so that the lower surface of the mounting substrate 28 is also covered, the interface between the mounting substrate 28 and the sealing resin 30 is not exposed to the outside. Intrusion into the water is suppressed and moisture resistance is improved. Further, with respect to other forms described below, resin sealing may be performed so that the mounting substrate 28 is also covered in this way.

図２（Ｂ）に示す混成集積回路装置１０Ｃでは、パワー素子２２のみが実装される実装基板２８として、金属からなる基板を採用している。このように、セラミックよりも熱伝導性に優れた金属を、実装基板２８の材料として採用することにより、パワー素子２２から放出された熱をより効率的に外部に放出することができる。また、この場合、パワー素子２２の下面電極が半田を介して実装基板２８と接続され、この実装基板２８に接続する金属細線２０を経由して、回路基板１２上の導電パターン１６とパワー素子２２とが電気的に接続されても良い。即ち、金属からなる実装基板２８の電位は、パワー素子２２の裏面電極（例えばコレクタ電極）と同電位となる。   In the hybrid integrated circuit device 10C shown in FIG. 2B, a substrate made of metal is employed as the mounting substrate 28 on which only the power element 22 is mounted. As described above, by using a metal having higher thermal conductivity than ceramic as the material of the mounting substrate 28, the heat released from the power element 22 can be released to the outside more efficiently. In this case, the lower surface electrode of the power element 22 is connected to the mounting board 28 via solder, and the conductive pattern 16 on the circuit board 12 and the power element 22 are connected via the fine metal wire 20 connected to the mounting board 28. And may be electrically connected. That is, the potential of the mounting substrate 28 made of metal is the same as that of the back electrode (eg, collector electrode) of the power element 22.

図２（Ｃ）に示す混成集積回路装置１０Ｄでは、セラミックから成る実装基板２８の下面に、アルミニウムまたは銅等の金属材料から成る金属基板３４が固着されている。そして、金属基板３４の下面は封止樹脂３０から外部に露出している。従って、パワー素子２２から発生した熱は、配線パターン３２、実装基板２８および金属基板３４をこの順番で経由した後に外部に放出される。   In the hybrid integrated circuit device 10D shown in FIG. 2C, a metal substrate 34 made of a metal material such as aluminum or copper is fixed to the lower surface of a mounting substrate 28 made of ceramic. The lower surface of the metal substrate 34 is exposed to the outside from the sealing resin 30. Therefore, the heat generated from the power element 22 is discharged to the outside after passing through the wiring pattern 32, the mounting substrate 28, and the metal substrate 34 in this order.

ここで、金属基板３４の平面視での大きさは、パワー素子２２よりも大きい程度が好適であり、厚みは実装基板２８と同程度で良い。このようにすることで、パワー素子２２から発せられて実装基板２８を伝導した熱が、金属基板３４で拡散される。即ち、金属基板３４がヒートスプレッダーとして作用し、パワー素子２２よりも広い面積で熱が外部に放出され、放熱特性が向上する。   Here, the size of the metal substrate 34 in plan view is preferably larger than that of the power element 22, and the thickness may be the same as that of the mounting substrate 28. By doing so, the heat generated from the power element 22 and conducted through the mounting substrate 28 is diffused by the metal substrate 34. That is, the metal substrate 34 acts as a heat spreader, heat is released to the outside in a larger area than the power element 22, and heat dissipation characteristics are improved.

図３を参照して、更なる混成集積回路装置の他の形態を説明する。   With reference to FIG. 3, another embodiment of a further hybrid integrated circuit device will be described.

図３（Ａ）に示す混成集積回路装置１０Ｅでは、セラミックから成る実装基板２８の上面に金属基板３４を載置し、この金属基板３４の上面にパワー素子２２を実装している。従って、パワー素子２２から発生した熱は、金属基板３４、配線パターン３２および実装基板２８を経由して外部に放出される。図２（Ｂ）の場合と同様に、パワー素子２２から発生した熱が、金属基板３４にて周囲に拡散されて広い面積が伝導するので、放熱性が良好となる。   In the hybrid integrated circuit device 10E shown in FIG. 3A, a metal substrate 34 is placed on the upper surface of a mounting substrate 28 made of ceramic, and the power element 22 is mounted on the upper surface of the metal substrate 34. Therefore, the heat generated from the power element 22 is released to the outside through the metal substrate 34, the wiring pattern 32, and the mounting substrate 28. As in the case of FIG. 2B, heat generated from the power element 22 is diffused to the periphery by the metal substrate 34, and a large area is conducted, so that heat dissipation is improved.

図３（Ｂ）に示す混成集積回路装置１０Ｆでは、開口部１８の周辺部で回路基板１２を厚み方向に窪ませて凹状部３６を形成し、実装基板２８を凹状部３６に収納している。また、スペーサ２６は、凹状部３６の内部で、実装基板２８と回路基板１２とを離間させている。ここで、凹状部３６の深さは、厚み方向で、スペーサ２６のみが収納される程度でも良いし、スペーサ２６と実装基板２８の一部が収納される程度でも良い。このようにすることで、実装基板２８を設けることによる装置全体の厚みの増加が抑制される。この凹状部３６を設ける事項は、上記した他の形態に適用可能である。   In the hybrid integrated circuit device 10 </ b> F shown in FIG. 3B, the circuit board 12 is recessed in the thickness direction around the opening 18 to form a concave part 36, and the mounting board 28 is accommodated in the concave part 36. . The spacer 26 separates the mounting board 28 and the circuit board 12 inside the recessed portion 36. Here, the depth of the concave portion 36 may be such that only the spacer 26 is accommodated in the thickness direction, or may be such that only a part of the spacer 26 and the mounting substrate 28 is accommodated. By doing in this way, the increase in the thickness of the whole apparatus by providing the mounting board | substrate 28 is suppressed. The matter of providing the concave portion 36 is applicable to the other forms described above.

図４を参照して、更なる他の形態の混成集積回路装置１０Ｇの構成を説明する。図４（Ａ）は混成集積回路装置１０Ｇを示す断面図であり、図４（Ｂ）は開口部１８を拡大して示す平面図であり、図４（Ｃ）は図４（Ｂ）のＣ−Ｃ’線における断面図である。   With reference to FIG. 4, the configuration of a hybrid integrated circuit device 10G according to still another embodiment will be described. 4A is a cross-sectional view showing the hybrid integrated circuit device 10G, FIG. 4B is an enlarged plan view showing the opening 18, and FIG. 4C is a cross-sectional view of C in FIG. 4B. It is sectional drawing in the -C 'line.

上記した混成集積回路装置１０Ａ等では、回路基板１２と実装基板２８との間にスペーサを配置することで両者を離間したが、この図に示す混成集積回路装置１０Ｇでは、開口部１８にて平面視で実装基板２８を回路基板１２から離間させている。   In the above-described hybrid integrated circuit device 10A and the like, the spacers are disposed between the circuit board 12 and the mounting substrate 28 to separate them from each other. However, in the hybrid integrated circuit device 10G shown in FIG. The mounting board 28 is separated from the circuit board 12 in view.

図４（Ａ）を参照して、ここでは、実装基板２８の上面の周辺部は直に回路基板１２の下面に固着されており、両者の間に上記したスペーサは配置されていない。また、両者の間にエポキシ樹脂等の接着材が塗布されるとしても、その厚みは極めて薄い。   Referring to FIG. 4A, here, the peripheral portion of the upper surface of the mounting substrate 28 is directly fixed to the lower surface of the circuit board 12, and the spacer described above is not disposed between them. Even if an adhesive such as an epoxy resin is applied between the two, the thickness is extremely thin.

図４（Ｂ）および図４（Ｃ）を参照して、平面視で実装基板２８と開口部１８とを比較すると、紙面上縦方向に対しては実装基板２８は開口部１８よりも短く、紙面上横方向に対しては実装基板２８は開口部１８よりも長い。従って、開口部１８の紙面上上下端部は、開口部１８が実装基板２８により覆われない領域（離間領域１９）となる。一方、紙面上横方向に対しては、実装基板２８の左右両端部が、開口部１８周辺部の回路基板１２と重畳し、この重畳する部分にて両者が固着される。   4B and 4C, when the mounting board 28 and the opening 18 are compared in plan view, the mounting board 28 is shorter than the opening 18 in the vertical direction on the paper surface. The mounting board 28 is longer than the opening 18 in the horizontal direction on the paper. Accordingly, the upper and lower ends of the opening 18 on the paper surface are regions (separation regions 19) where the opening 18 is not covered by the mounting substrate 28. On the other hand, with respect to the horizontal direction on the paper surface, both left and right end portions of the mounting substrate 28 overlap with the circuit board 12 in the periphery of the opening 18, and both are fixed to each other at the overlapping portion.

このようにすることで、離間領域１９を介して実装基板２８と回路基板１２とが離間されるので、実装基板２８の全ての周辺部が回路基板１２と接触する場合と比較すると、実装基板２８と回路基板１２とを熱的に分離させることが可能となる。   By doing so, the mounting board 28 and the circuit board 12 are separated from each other via the separation region 19. Therefore, the mounting board 28 is compared with the case where all the peripheral portions of the mounting board 28 are in contact with the circuit board 12. And the circuit board 12 can be thermally separated.

更に、後述するように、製造方法の樹脂封止の工程にて、回路基板１２の上方に供給された封止樹脂を、この離間領域１９を経由して回路基板１２の下方に流動させることが可能となる。   Further, as will be described later, in the resin sealing step of the manufacturing method, the sealing resin supplied above the circuit board 12 can be caused to flow below the circuit board 12 via the separation region 19. It becomes possible.

図５を参照して、更なる他の形態の混成集積回路装置１０Ｈの構成を説明する。ここでは、２つの開口部１８Ａ、１８Ｂが設けられ、これらの開口部に配置された素子同士が、回路基板１２の下面に設けられた導電パターン１７Ａを経由して接続されている。   With reference to FIG. 5, the configuration of a hybrid integrated circuit device 10H according to still another embodiment will be described. Here, two openings 18A and 18B are provided, and elements arranged in these openings are connected via a conductive pattern 17A provided on the lower surface of the circuit board 12.

具体的には、紙面上にて左側に設けた開口部１８Ａを塞ぐように実装基板２８Ａが配置され、実装基板２８Ａにパワー素子２２Ａが実装されている。実装基板２８Ａの上面にはパワー素子２２Ａが接続される配線パターン３２Ａが配置され、回路基板１２の下面に設けた導電パターン１７と、半田等の導電性固着材を介して固着されている。ここで、実装基板２８Ａの上面は、回路基板１２に当接しても良いし離間しても良い。   Specifically, the mounting board 28A is arranged so as to close the opening 18A provided on the left side on the paper surface, and the power element 22A is mounted on the mounting board 28A. A wiring pattern 32A to which the power element 22A is connected is disposed on the upper surface of the mounting substrate 28A, and is fixed to the conductive pattern 17 provided on the lower surface of the circuit board 12 via a conductive fixing material such as solder. Here, the upper surface of the mounting substrate 28A may abut against or be separated from the circuit board 12.

また、紙面上にて右側に設けた開口部１８Ｂを塞ぐように実装基板２８Ｂが配置され、実装基板２８Ｂの上面にパワー素子２２Ｂが配置されている。そして、実装基板２８Ｂの上面に設けた配線パターン３２Ｂにパワー素子２２Ｂが接続され、導電パターン１７と半田を介して固着されている。   Further, the mounting board 28B is arranged so as to close the opening 18B provided on the right side on the paper surface, and the power element 22B is arranged on the upper surface of the mounting board 28B. The power element 22B is connected to the wiring pattern 32B provided on the upper surface of the mounting substrate 28B, and is fixed to the conductive pattern 17 via solder.

ここでは、実装基板２８Ａに実装されたパワー素子２２Ａと、実装基板２８Ｂに実装されたパワー素子２２Ｂとが、回路基板１２の裏面に設けた導電パターン１７Ａを経由して接続されている。例えば、これらの素子がＩＧＢＴであれば、パワー素子２２Ａ、２２Ｂのコレクタ電極どうしが、導電パターン１７Ａを経由して接続される。これにより、両者を接続するパターンを回路基板１２の上面に設ける必要がないので、回路基板１２を小型なものとなる。   Here, the power element 22A mounted on the mounting board 28A and the power element 22B mounted on the mounting board 28B are connected via the conductive pattern 17A provided on the back surface of the circuit board 12. For example, if these elements are IGBTs, the collector electrodes of the power elements 22A and 22B are connected via the conductive pattern 17A. As a result, there is no need to provide a pattern for connecting the two on the upper surface of the circuit board 12, so that the circuit board 12 can be made compact.

図６を参照して、上記した構成の混成集積回路装置の熱抵抗を測定した実験結果を説明する。ここでは、上記した混成集積回路装置１０Ａ、１０Ｄおよび１０Ｅを用意し、従来例のものと共に熱抵抗の経時変化を測定した。この図に示すグラフでは、縦軸は熱抵抗を示し、横軸は経過時間を対数で示している。ここで、熱抵抗が小さいことは、放熱性に優れていることを示している。また、熱抵抗の値が時間と共に変化する領域での熱抵抗（グラフでは１０秒までの領域）は過渡熱抵抗と称され、それ以降で経時的に熱抵抗が変化しない熱抵抗は（グラフでは１０秒以降の領域）は定常熱抵抗と称される。   With reference to FIG. 6, the experimental results of measuring the thermal resistance of the hybrid integrated circuit device having the above-described configuration will be described. Here, the hybrid integrated circuit devices 10A, 10D, and 10E described above were prepared, and the temporal change of the thermal resistance was measured together with the conventional example. In the graph shown in this figure, the vertical axis represents thermal resistance, and the horizontal axis represents elapsed time in logarithm. Here, a low thermal resistance indicates that the heat dissipation is excellent. In addition, the thermal resistance in a region where the value of thermal resistance changes with time (region up to 10 seconds in the graph) is referred to as transient thermal resistance, and the thermal resistance in which the thermal resistance does not change over time thereafter (in the graph, The region after 10 seconds) is called steady thermal resistance.

図１（Ａ）に示す混成集積回路装置１０Ａは、従来例と比較すると、１０秒までの過渡熱抵抗では劣るが、それ以降の定常熱抵抗では良好な値を示している。過渡熱容量が従来例よりも劣る原因は、セラミックから成る実装基板２８が、従来例のアルミから成る基板１０１よりも熱容量が小さいからである。また、混成集積回路装置１０Ａが定常熱抵抗に優れる原因は、上記したように、熱伝導率の低い樹脂材料が熱の経路に存在しないからである。   The hybrid integrated circuit device 10A shown in FIG. 1A is inferior in transient thermal resistance up to 10 seconds, but has a good value in steady thermal resistance thereafter. The reason why the transient heat capacity is inferior to that of the conventional example is that the mounting substrate 28 made of ceramic has a smaller heat capacity than the substrate 101 made of aluminum of the conventional example. Further, the reason why the hybrid integrated circuit device 10A is excellent in steady thermal resistance is that, as described above, a resin material having low thermal conductivity is not present in the heat path.

図２（Ｃ）に示す混成集積回路装置１０Ｄの実験結果を従来例と比較すると、過渡熱抵抗は従来例よりも劣るが、定常熱抵抗では従来例よりも優れている。この理由は、混成集積回路装置１０Ａの場合と同様である。また、この結果を混成集積回路装置１０Ａと比較すると、過渡熱抵抗値ではこのケースの方が優れている。この原因は、実装基板２８の下面に配置された金属基板３４がヒートシンクとして機能し、パワー素子２２の急激な温度上昇が抑制されたからである。   When the experimental result of the hybrid integrated circuit device 10D shown in FIG. 2C is compared with the conventional example, the transient thermal resistance is inferior to the conventional example, but the steady thermal resistance is superior to the conventional example. The reason is the same as in the case of the hybrid integrated circuit device 10A. Further, when this result is compared with the hybrid integrated circuit device 10A, this case is superior in the transient thermal resistance value. This is because the metal substrate 34 disposed on the lower surface of the mounting substrate 28 functions as a heat sink, and the rapid temperature rise of the power element 22 is suppressed.

図３（Ａ）に示す混成集積回路装置１０Ｅの実験結果を従来例と比較すると、過渡熱抵抗および定常熱抵抗の両方に於いて、混成集積回路装置１０Ｅが従来例よりも優れている。過渡熱抵抗が優れる理由は、動作の初期段階に於いてはパワー素子２２から発生した熱が金属基板３４に吸収されて急激な温度上昇が抑制されるからである。また、定常熱抵抗が優れる理由は、パワー素子２２から発生した熱が金属基板３４によって四方に広げられた後に、広い面積で実装基板２８から外部に放出されるからである。   When the experimental result of the hybrid integrated circuit device 10E shown in FIG. 3A is compared with the conventional example, the hybrid integrated circuit device 10E is superior to the conventional example in both transient thermal resistance and steady thermal resistance. The reason why the transient thermal resistance is excellent is that, in the initial stage of operation, the heat generated from the power element 22 is absorbed by the metal substrate 34 and a rapid temperature rise is suppressed. The reason why the steady thermal resistance is excellent is that the heat generated from the power element 22 is spread in all directions by the metal substrate 34 and then released to the outside from the mounting substrate 28 in a wide area.

以上の実験結果から、本形態の混成集積回路装置は、従来例のものよりも放熱性に優れていると判断される。   From the above experimental results, it is determined that the hybrid integrated circuit device of this embodiment has better heat dissipation than that of the conventional example.

図７を参照して、次に上記した構成の混成集積回路装置１０Ａの製造方法を説明する。図７（Ａ）は本工程を示す断面図であり、図７（Ｂ）は開口部１８を拡大して示す断面図であり、図７（Ｃ）は開口部１８を上方から見た平面図である。更に図７（Ｄ）は、図４に示した混成集積回路装置１０Ｇを樹脂封止する工程を示す断面図である。   With reference to FIG. 7, a method of manufacturing the hybrid integrated circuit device 10A having the above-described configuration will be described next. 7A is a cross-sectional view showing this step, FIG. 7B is an enlarged cross-sectional view showing the opening 18, and FIG. 7C is a plan view of the opening 18 viewed from above. It is. Further, FIG. 7D is a cross-sectional view showing a step of resin-sealing the hybrid integrated circuit device 10G shown in FIG.

図７（Ａ）を参照して、混成集積回路装置１０Ａの製造方法では、回路基板１２の上面に形成された導電パターンに制御素子等の回路素子が接続され、回路基板１２に設けられた開口部１８を塞ぐように、回路基板１２の下方に実装基板２８が配置されている。実装基板２８の上面にはパワー素子２２が配置されている。そして、実装基板２８の上面と回路基板１２の下面との間にはスペーサ２６が配置されており、これにより両者の間に間隙が形成されている。ここで、回路基板１２、実装基板２８及び、これらの基板に実装される回路素子の詳細は図１を参照して説明した通りである。また、回路基板１２の周辺部には図１に示したリードが固着されており、このリードが金型３８で挟持されることにより、金型３８の内部に於ける回路基板１２の位置が固定される。   Referring to FIG. 7A, in the method of manufacturing hybrid integrated circuit device 10A, circuit elements such as control elements are connected to conductive patterns formed on the upper surface of circuit board 12, and openings provided in circuit board 12 are provided. A mounting board 28 is disposed below the circuit board 12 so as to close the portion 18. The power element 22 is disposed on the upper surface of the mounting substrate 28. A spacer 26 is disposed between the upper surface of the mounting substrate 28 and the lower surface of the circuit board 12, thereby forming a gap therebetween. Here, details of the circuit board 12, the mounting board 28, and the circuit elements mounted on these boards are as described with reference to FIG. Further, the lead shown in FIG. 1 is fixed to the peripheral portion of the circuit board 12, and the position of the circuit board 12 in the mold 38 is fixed by sandwiching the lead by the mold 38. Is done.

上記構成を備えた回路基板１２は、金型３８の内部に収納される。金型３８は、上金型４０と下金型４２とから成り、両者を当接されることで形成されるキャビティ４６の内部に回路基板１２が収納されている。ここでは、実装基板２８の下面を外部に露出させるので、実装基板２８の下面は、下金型４２の内壁に当接している。一方、図２（Ａ）に示すように、実装基板２８の下面を封止樹脂３０で被覆する場合は、実装基板２８の下面を下金型４２の内壁から離間させる。   The circuit board 12 having the above configuration is accommodated in the mold 38. The mold 38 includes an upper mold 40 and a lower mold 42, and the circuit board 12 is accommodated in a cavity 46 formed by abutting both of them. Here, since the lower surface of the mounting substrate 28 is exposed to the outside, the lower surface of the mounting substrate 28 is in contact with the inner wall of the lower mold 42. On the other hand, as shown in FIG. 2A, when the lower surface of the mounting substrate 28 is covered with the sealing resin 30, the lower surface of the mounting substrate 28 is separated from the inner wall of the lower mold 42.

回路基板１２をキャビティ４６に収納した後は、ゲート４４から液状または半固形状の封止樹脂をキャビティ４６に注入する。注入される樹脂としては、エポキシ樹脂等の熱硬化性樹脂が採用される。注入された封止樹脂により、回路基板１２、回路基板１２の上面に固着された回路素子、実装基板２８、実装基板２８の上面に固着されたパワー素子が樹脂封止される。また、開口部１８にも封止樹脂が充填され、更に実装基板２８の下面は外部に露出する。その後、注入された封止樹脂が加熱硬化した後に除熱し、上金型４０と下金型４２とを離型した後に、樹脂封止された回路基板１２を金型３８から取り出す。   After the circuit board 12 is stored in the cavity 46, liquid or semi-solid sealing resin is injected from the gate 44 into the cavity 46. A thermosetting resin such as an epoxy resin is employed as the resin to be injected. By the injected sealing resin, the circuit board 12, the circuit element fixed to the upper surface of the circuit board 12, the mounting substrate 28, and the power element fixed to the upper surface of the mounting substrate 28 are resin-sealed. The opening 18 is also filled with sealing resin, and the lower surface of the mounting substrate 28 is exposed to the outside. Thereafter, after the injected sealing resin is heated and cured, the heat is removed, and the upper mold 40 and the lower mold 42 are released, and then the resin-sealed circuit board 12 is taken out from the mold 38.

図７（Ｂ）を参照して、本形態では、実装基板２８と回路基板１２との間にスペーサ２６を介在させることにより、両者の間に間隙を確保している。これにより、樹脂封止の工程にて開口部１８に流入した液状の封止樹脂３０は、スペーサ２６により形成された間隙を経由して、回路基板１２の下方に回りこむ。これにより、開口部１８の内部および回路基板１２の下方に封止樹脂３０が充填され、未充填領域であるボイドの出現が抑制される。   With reference to FIG. 7B, in this embodiment, a spacer 26 is interposed between the mounting board 28 and the circuit board 12 to secure a gap between them. As a result, the liquid sealing resin 30 that has flowed into the opening 18 in the resin sealing step passes under the circuit board 12 via the gap formed by the spacer 26. Thereby, the sealing resin 30 is filled inside the opening 18 and below the circuit board 12, and the appearance of voids that are unfilled regions is suppressed.

図７（Ｃ）を参照して、本形態では、実装基板２８の対向する側辺に沿って細長いスペーサ２６を配置している。従って、本工程にて開口部１８に流入された封止樹脂３０は、スペーサ２６に沿って横方向外側に向かって流動する。この図では、封止樹脂３０が流動する方向を矢印にて示している。   With reference to FIG. 7C, in this embodiment, elongated spacers 26 are arranged along the opposing sides of the mounting substrate 28. Therefore, the sealing resin 30 that has flowed into the opening 18 in this step flows along the spacer 26 toward the outside in the lateral direction. In this figure, the direction in which the sealing resin 30 flows is indicated by arrows.

更に本形態では、図７（Ａ）を参照して、ゲート４４の位置は、回路基板１２の上面よりも上方に設定されている。一例として、ゲート４４は回路基板１２の上面から１ｍｍ以上の上方に配置されている。これにより、ゲート４４からキャビティ４６に注入された封止樹脂の一部は、開口部１８を経由して良好に回路基板１２の下方に行き渡る。   Furthermore, in this embodiment, referring to FIG. 7A, the position of the gate 44 is set above the upper surface of the circuit board 12. As an example, the gate 44 is disposed above the upper surface of the circuit board 12 by 1 mm or more. As a result, a part of the sealing resin injected from the gate 44 into the cavity 46 spreads well below the circuit board 12 through the opening 18.

また、図７（Ｄ）を参照して、図４に示す混成集積回路装置１０Ｇの場合は、実装基板２８と回路基板１２との間に離間領域１９が存在するので、回路基板１２の上方に供給された封止樹脂３０は、この離間領域１９を経由して回路基板１２の下方に良好に流動する。   7D, in the case of the hybrid integrated circuit device 10G shown in FIG. 4, since the separation region 19 exists between the mounting board 28 and the circuit board 12, the circuit board 12 is located above. The supplied sealing resin 30 flows well below the circuit board 12 via the separation region 19.

以上が、本形態に係る混成集積回路装置の製造方法の説明である。   The above is the description of the method for manufacturing the hybrid integrated circuit device according to this embodiment.

１０Ａ，１０Ｂ，１０Ｃ，１０Ｄ，１０Ｅ，１０Ｆ，１０Ｇ，１０Ｈ 混成集積回路装置
１２ 回路基板
１４ リード
１６ 導電パターン
１７，１７Ａ 導電パターン
１８，１８Ａ，１８Ｂ 開口部
１９ 離間領域
２０ 金属細線
２２，２２Ａ，２２Ｂ パワー素子
２３ 制御素子
２４ チップ素子
２６ スペーサ
２８，２８Ａ，２８Ｂ 実装基板
３０ 封止樹脂
３２，３２Ａ，３２Ｂ 配線パターン
３４ 金属基板
３６ 凹状部
３８ 金型
４０ 上金型
４２ 下金型
４４ ゲート
４６ キャビティ 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H Hybrid integrated circuit device 12 Circuit board 14 Lead 16 Conductive pattern 17, 17A Conductive pattern 18, 18A, 18B Opening 19 Separation area 20 Metal thin wires 22, 22A, 22B Power element 23 Control element 24 Chip element 26 Spacer 28, 28A, 28B Mounting substrate 30 Sealing resin 32, 32A, 32B Wiring pattern 34 Metal substrate 36 Recess 38 Mold 40 Upper mold 42 Lower mold 44 Gate 46 Cavity

Claims (14)

上面に導電パターンが配置された回路基板と、
前記回路基板を部分的に開口した開口部と、
前記開口部と重畳するように前記回路基板の下方に配置された実装基板と、
前記実装基板の上面に配置されて前記導電パターンと電気的に接続された半導体素子と、を備え、
前記実装基板の一部を前記回路基板から離間させることを特徴とする回路装置。 A circuit board having a conductive pattern disposed on the upper surface;
An opening partly opening the circuit board;
A mounting board disposed below the circuit board so as to overlap the opening,
A semiconductor element disposed on an upper surface of the mounting substrate and electrically connected to the conductive pattern,
A circuit device characterized in that a part of the mounting substrate is separated from the circuit substrate. 前記回路基板の下面と前記実装基板の上面との間にスペーサを配置することにより、前記実装基板と前記回路基板とを離間させることを特徴とする請求項１に記載の回路装置。   The circuit device according to claim 1, wherein a spacer is disposed between the lower surface of the circuit board and the upper surface of the mounting board to separate the mounting board and the circuit board. 前記スペーサは、前記開口部の側辺に沿って設けられることを特徴とする請求項２に記載の回路装置。   The circuit device according to claim 2, wherein the spacer is provided along a side of the opening. 前記スペーサは、絶縁材料から成ることを特徴とする請求項２または請求項３に記載の回路装置。   The circuit device according to claim 2, wherein the spacer is made of an insulating material. 前記実装基板の幅を、前記開口部の幅よりも狭くすることにより、前記実装基板を前記回路基板から離間させることを特徴とする請求項１に記載の回路装置。   The circuit device according to claim 1, wherein the mounting board is separated from the circuit board by making a width of the mounting board narrower than a width of the opening. 前記実装基板は、前記回路基板よりも熱伝導性に優れる材料から成ることを特徴とする請求項１から請求項５の何れかに記載の回路装置。   6. The circuit device according to claim 1, wherein the mounting substrate is made of a material having higher thermal conductivity than the circuit substrate. 前記回路基板および前記半導体素子を被覆する封止樹脂を更に具備し、
前記実装基板の下面は前記封止樹脂から外部に露出することを特徴とする請求項１から請求項６の何れかに記載の回路装置。 Further comprising a sealing resin covering the circuit board and the semiconductor element;
The circuit device according to claim 1, wherein a lower surface of the mounting substrate is exposed to the outside from the sealing resin. 前記実装基板の上面に配置された金属基板の上面に前記半導体素子が固着されることを特徴とする請求項１から請求項７の何れかに記載の回路装置。   The circuit device according to claim 1, wherein the semiconductor element is fixed to an upper surface of a metal substrate disposed on the upper surface of the mounting substrate. 前記開口部を囲む部分の前記回路基板の下面を窪ませて凹状部を形成し、
前記スペーサは前記凹状部に備えられることを特徴とする請求項１から請求項８の何れかに記載の回路装置。 Recessing the lower surface of the circuit board surrounding the opening to form a concave portion,
The circuit device according to claim 1, wherein the spacer is provided in the concave portion. 上面に導電パターンが配置されると共に開口部が設けられた回路基板を用意し、半導体素子が上面に実装された実装基板を、前記開口部と重畳する位置で前記回路基板の下方に配置する工程と、
金型のキャビティに前記回路基板および前記実装基板を収納し、前記回路基板の上面、側面および下面の周辺部を封止樹脂で被覆する工程と、を備え、
前記実装基板を前記回路基板から離間させることで、前記実装基板と前記回路基板との間に間隙を形成し、前記間隙を経由して前記封止樹脂を流動させることを特徴とする回路装置の製造方法。 A step of preparing a circuit board on which an upper surface is provided with a conductive pattern and having an opening, and disposing a mounting board on which a semiconductor element is mounted on the upper surface below the circuit board at a position overlapping the opening. When,
Storing the circuit board and the mounting board in a cavity of a mold, and covering the periphery of the upper surface, side surface, and lower surface of the circuit board with a sealing resin, and
A circuit device characterized in that a gap is formed between the mounting board and the circuit board by separating the mounting board from the circuit board, and the sealing resin is caused to flow through the gap. Production method. 前記回路基板の下面と前記実装基板の上面との間にスペーサを配置することにより、前記実装基板と前記回路基板との間に間隙を形成することを特徴とする請求項１０に記載の回路装置の製造方法。   The circuit device according to claim 10, wherein a gap is formed between the mounting substrate and the circuit board by arranging a spacer between the lower surface of the circuit board and the upper surface of the mounting board. Manufacturing method. 前記スペーサは前記開口部の対向する２つの側辺に沿って設けられ、
前記封止樹脂で被覆する工程では、前記スペーサに沿って前記封止樹脂を流動させることを特徴とする請求項１１に記載の回路装置の製造方法。 The spacer is provided along two opposing sides of the opening,
The method for manufacturing a circuit device according to claim 11, wherein in the step of covering with the sealing resin, the sealing resin is caused to flow along the spacer. 前記実装基板の幅を前記開口部の幅よりも狭くすることにより、前記実装基板と前記回路基板との間に前記間隙を形成することを特徴とする請求項１０に記載の回路装置の製造方法。   The method for manufacturing a circuit device according to claim 10, wherein the gap is formed between the mounting substrate and the circuit substrate by making a width of the mounting substrate narrower than a width of the opening. . 前記封止樹脂で被覆する工程では、前記回路基板よりも上方に配置された前記金型のゲートを経由して前記封止樹脂を前記キャビティに注入し、前記開口部に流入した前記封止樹脂を、前記間隙を経由して前記回路基板の下方に流動させることを特徴とする請求項１０から請求項１３の何れかに記載の回路基板の製造方法。   In the step of coating with the sealing resin, the sealing resin is injected into the cavity through the gate of the mold disposed above the circuit board and flows into the opening. 14. The method for manufacturing a circuit board according to claim 10, wherein the circuit board is caused to flow downwardly through the gap through the circuit board.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256803A (en) * 2011-06-10 2012-12-27 Mitsubishi Electric Corp Power module and manufacturing method of the same
JP2020505791A (en) * 2017-01-25 2020-02-20 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ Method of mechanically connecting electronic components and electronic component assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256803A (en) * 2011-06-10 2012-12-27 Mitsubishi Electric Corp Power module and manufacturing method of the same
JP2020505791A (en) * 2017-01-25 2020-02-20 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ Method of mechanically connecting electronic components and electronic component assembly

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