JP2013118367A - Thin film transistor, manufacturing method of the same, display device equipped with thin film transistor and sputtering target material - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor which inhibits decrease in electric characteristic value of a TFT using a Cu alloy to wiring; and provide a manufacturing method of the thin film transistor, a display device equipped with the thin film transistor and a sputtering target material.SOLUTION: A TFT comprises: a gate insulation film; a Si-based semiconductor layer; source/drain electrodes having a Cu alloy layer; and an oxide film formed at a boundary of the Si-based semiconductor layer with the source electrode and the drain electrode. The Cu alloy layer contains Cu and at least one kind of additive element. When a peak value of a depth distribution of an oxygen atomic concentration in the oxide film is not less than 40 atom% and not more than 66 atom%, and a distance from the position of the peak value of the oxygen atomic concentration or from the boundary of the Si-based semiconductor layer with the source/drain electrodes, at which an oxygen distribution indicates 10 atom% is defined as a film thickness of the oxide film, the film thickness of the oxide film is 1.8 nm and under.

Description

  The present invention relates to a thin film transistor, a manufacturing method thereof, an active matrix display device using the thin film transistor, and a sputtering target material.

Recently, thin film transistors: in an active matrix display device using (TFT T hin F ilm T ransistor ) to the pixel circuit, its size, high definition of pixels, improved video performance by doubling the frame frequency, further 3D consumer There is a demand for improving the image quality of display devices. On the other hand, the price of display devices continues to decline at a pace exceeding expectations, and factors that push up manufacturing costs such as rising prices of energy resources and rare metals are also increasing. Therefore, there is an urgent need to develop a technique for further reducing manufacturing costs.

To satisfy the above requirements, for example, a liquid crystal display device: In (LCD L iquid C rystal D isplays ), varying the semiconductor layer of the TFT, an amorphous silicon film is microcrystalline silicon or polycrystalline silicon or an oxide semiconductor, There is also an attempt to change the wiring material from aluminum (Al) or an Al alloy to copper (Cu). Microcrystalline silicon, polycrystalline silicon, or an oxide semiconductor has higher carrier mobility than amorphous silicon, so the driving voltage can be greatly reduced, and pixel definition and power consumption can be reduced. In addition, a driver circuit can be formed in the peripheral portion of the display device.

  Since Cu wiring has lower electrical resistance than Al wiring, it is possible to suppress the propagation delay phenomenon in which the electrical signal transmitted through the wiring is delayed, and it is possible to further improve the quality of moving images by increasing the size of the display device and increasing the frame frequency. Become. Also, the Al wiring has a Mo / Al / Mo laminated film structure in which the upper and lower sides of the Al film are sandwiched by expensive molybdenum (Mo) in order to suppress the generation of hillocks and ensure electrical connection with the transparent conductive film. However, since Cu can be directly connected to the transparent conductive film, molybdenum can be saved. Therefore, the manufacturing cost can be reduced.

  Further, in order to increase the size of the organic EL display device and improve the image quality, in addition to applying a high mobility semiconductor layer, a wiring material having a lower resistance than that of the Al wiring is required. The drive transistor provided in the pixel circuit of the organic EL display device controls the current flowing in the organic EL layer using the saturation region and adjusts the brightness. However, the influence of the voltage drop due to the wiring resistance with the increase in the size of the display device If it cannot be ignored, the assumed voltage is not supplied to the driving transistor, and driving in the saturation region becomes impossible, resulting in uneven brightness. Therefore, application of Cu wiring is being studied to improve display quality.

  However, the following problems exist when the Cu wiring is applied to the TFT. Cu has poor adhesion to glass substrates and semiconductor layers. Further, when Cu is in contact with the semiconductor layer, Cu diffuses inside the semiconductor layer due to heat applied in the manufacturing process after the wiring is formed, thereby degrading TFT characteristics and lowering display quality. As a countermeasure for such adhesion and diffusion barrier properties, there is a method of forming Mo or Mo alloy between the base film and the Cu film. However, as described above, Mo is expensive, and a laminated structure of metals having different electrochemical properties makes etching difficult, so that the manufacturing cost increases.

In view of this, a method has been proposed in which a Cu alloy is used to precipitate an additive element at the interface by using a thermal process to form an additive element oxide film having excellent adhesion and diffusion barrier properties. Here thermal process, CVD (C hemical V apor D eposition) process and an alignment film baking process in a liquid crystal display device, such as annealing for curing the oxide semiconductor film, the temperature experienced by the TFT substrate after the wiring formation Assumed. For the self-formation of the additive element oxide film, necessary and sufficient oxygen atoms must exist in advance at the interface between the Cu alloy and the film in contact therewith.

In Patent Document 1 is recommended CuMn alloy, the source and drain of the TFT: A method of applying a Cu alloy (SD S ource D rain) electrodes, for example, perform an oxygen plasma treatment before forming the Cu alloy, silicon A method has been proposed in which the upper layer of the film is modified to temporarily form a silicon oxide layer SiO _x and oxygen necessary for forming the additive element oxide film is applied.

  Patent Document 2 below discloses a method of applying a Cu alloy to an oxide semiconductor. The oxide semiconductor film contains in advance oxygen necessary for self-formation of the additive element oxide film.

JP 2008-28287A JP 2011-91364 A

  However, as in Patent Document 1, when a Cu alloy is used for the wiring, if an oxidation treatment using oxygen plasma is performed on a semiconductor layer made of a silicon film, damage caused by the oxygen plasma treatment is introduced into the semiconductor layer made of a silicon film. There is a problem that the mobility of the TFT is lowered.

Further, as in Patent Document 2, when a Cu alloy is used for the wiring, when the Cu alloy is brought into contact with the semiconductor layer made of an oxide semiconductor film and heated, the subthreshold coefficient increases and the threshold voltage shifts in the negative direction. However, there is a problem that the TFT is normally on.
An object of the present invention is to suppress a decrease in electrical characteristic value of a TFT using a Cu alloy for wiring.

  According to an aspect of the present invention, a gate insulating film, a Si-based semiconductor layer, a source / drain electrode having a Cu alloy layer, and the source and drain electrodes and the Si on the substrate in order from the substrate side. A thin film transistor including an oxide film formed at an interface with a semiconductor layer, wherein the Cu alloy layer includes Cu and at least one additional element, and oxygen atoms in the oxide film. Concentration depth distribution has a peak value of 40 atomic% or more and 66 atomic% or less, and from the peak value of the atomic concentration of oxygen or from the interface between the source and drain electrodes and the Si-based semiconductor layer. When the distance at which the oxygen distribution is 10 atomic% is defined as the thickness of the oxide film, the oxide film has a thickness of 1.8 nm or less.

  Here, the oxide film formed at the source / drain electrode interface having the Si-based semiconductor layer and the Cu alloy layer is excellent in adhesion and diffusion barrier properties, and has a low electrical resistance. It is a self-forming film formed of a silicon oxide film. At this time, since an oxide film having excellent adhesion and diffusion barrier properties is also formed on the ultrathin oxide film immediately above the gate insulating film, the source electrode and the drain electrode are unlikely to peel off. Further, it is suggested that the diffusion of Cu atoms to the Si semiconductor layer is suppressed, and that there is no silicon oxide film serving as a parasitic resistance near the interface between the source and drain electrodes and the Si semiconductor layer (reduction in mobility). That is, no decrease in on-current is observed).

  Further, when the distance from the peak value or from the interface between the Cu alloy layer and the Si semiconductor layer is defined as the silicon oxide film thickness, the film thickness is 1.6 nm or less. Alternatively, when the distance at which the oxygen distribution is 20 atomic% from the interface between the Cu alloy layer and the Si semiconductor layer is defined as the silicon oxide film thickness, the film thickness is 1.4 nm or less, and from the peak value or from the Cu alloy layer When the distance at which the oxygen distribution is 25 atomic% from the interface of the Si semiconductor layer is defined as the silicon oxide film thickness, the film thickness is preferably 1.2 nm or less.

  Further, the average of the line density of the portion where the constituent material of the source electrode and the drain electrode diffuses into the Si-based semiconductor layer at the interface between the source and drain electrodes and the Si-based semiconductor layer is 7 per 480 nm. The following is preferable.

In other words, if the material density of the source electrode and the drain electrode is 7 × 7/480 × 480 nm ² or less (212.6 / μm ² or less) where the material diffuses into the Si semiconductor layer. It can be seen that adhesion can be secured.

According to another aspect of the present invention, a source / drain having a gate insulating film, a Si-based semiconductor layer, and a Cu alloy layer containing Cu and at least one additive element on the substrate in order from the substrate side. A thin film transistor comprising an electrode and an oxide film formed at an interface between the source and drain electrodes and the Si-based semiconductor layer, wherein a gate electrode structure is formed on the substrate, and Depositing the Si-based semiconductor film on the gate insulating film after depositing the gate insulating film; forming a very thin oxide film on the surface of the Si-based semiconductor layer by a plasma oxidation method; and the Cu alloy Forming a source / drain electrode having a layer, wherein the oxide film is formed by a plasma oxidation method, and an RF power density in the plasma oxidation method is 0.22 0.67 W / cm ² or less, and, a method of manufacturing the thin film transistor, wherein the treatment time is less 240 seconds 60 seconds is provided.

In addition, a source / drain electrode having a gate insulating film, a Si-based semiconductor layer, a Cu alloy layer containing Cu and at least one kind of additive element on the substrate in order from the substrate side; An oxide film formed at an interface between an electrode and the Si-based semiconductor layer, and after forming a gate electrode structure on the substrate and depositing a gate insulating film thereon, Depositing the Si-based semiconductor film on the gate insulating film; forming a very thin oxide film on the surface of the Si-based semiconductor layer by plasma oxidation; and source / drain electrodes having the Cu alloy layer The oxide film is formed by a plasma oxidation method, and the product of the RF power density and the processing time in the plasma oxidation method is 26. Manufacturing method of a thin film transistor which is a 4~52.8W · sec / cm ² is provided.

  In addition, the present invention provides a source / source having a gate insulating film having an oxide film, an oxide semiconductor layer, and a Cu alloy layer containing Cu and at least one additive element on the substrate in order from the substrate side. A thin film transistor comprising a drain electrode, an oxide film formed at an interface between the source electrode and the drain electrode and the oxide semiconductor layer, and a protective film for protecting the whole, wherein the oxide film includes: The atomic concentration of the additive element and oxygen in the source electrode and the drain electrode has a peak, and the peak value of oxygen is larger than the peak value of the additive element.

  At the formation temperature of the protective film, Cu atoms and additive elements in the Cu under the source electrode and the drain electrode are precipitated at the interface, combined with the insulating film formed in advance on the oxide semiconductor layer, Oxygen diffusion from the oxide semiconductor layer is suppressed. In other words, the oxide semiconductor film is oxidized before the Cu alloy film is formed, and the surface is temporarily changed to an insulator, so that the Cu element is formed and the additive element diffuses in the process involving heat. Even when the additive element oxide film is formed, necessary and sufficient oxygen exists at the interface between the Cu alloy and the oxide semiconductor film, so that oxygen does not diffuse from the deep part of the oxide semiconductor film. In addition, since the peak value of the atomic concentration of oxygen is larger than the peak value of the additive element, the current rising characteristic of the TFT is good, and the Cu alloy wiring can be applied to the oxide semiconductor TFT.

  In addition, oxygen is combined and an oxide film having low electrical resistance is self-formed, so that the adhesion and diffusion barrier properties between the source and drain electrodes and the oxide semiconductor layer are improved. Therefore, according to the thin film transistor, diffusion of oxygen from the oxide semiconductor layer is suppressed, and Cu alloy wiring can be applied to the oxide semiconductor TFT.

  In addition, since the oxide film having excellent adhesion and diffusion barrier properties is self-formed even with the extremely thin oxide film directly on the gate insulating film, the source electrode and the drain electrode are unlikely to peel off.

In the above, the equilibrium oxygen potential of the oxide generation reaction of the additive element in the source electrode and the drain electrode is smaller than the equilibrium oxygen potential of at least one element constituting the oxide semiconductor layer.
A part of the protective film may be made of a silicon nitride film.

By forming at least a part of the protective film from a silicon nitride film, hydrogen may diffuse into the oxide semiconductor layer, resulting in a decrease in electrical characteristics. However, the insulating film above the oxide semiconductor layer reduces this. And the diffusion of hydrogen into the oxide semiconductor film is prevented.

  According to another aspect of the present invention, a Cu alloy layer including a gate insulating film having an oxide film, an oxide semiconductor layer, Cu, and at least one additive element on the substrate in order from the substrate side. A method of manufacturing a thin film transistor, comprising: a source / drain electrode including: an oxide film formed at an interface between the source and drain electrodes and the oxide semiconductor layer; and a protective film that protects the whole. In the step of forming the protective film, in the oxide film, the atomic concentration of the additive element and oxygen in the source electrode and the drain electrode has a peak, and the peak value of oxygen is larger than the peak value of the additive element. A method for manufacturing a thin film transistor is provided.

At the formation temperature of the protective film, Cu atoms and additive elements in the Cu under the source electrode and the drain electrode are precipitated at the interface, combined with the insulating film formed in advance on the oxide semiconductor layer, Oxygen diffusion from the oxide semiconductor layer is suppressed. In other words, the oxide semiconductor film is oxidized before the Cu alloy film is formed, and the surface is temporarily changed to an insulator, so that the Cu element is formed and the additive element diffuses in the process involving heat. Even when the additive element oxide film is formed, necessary and sufficient oxygen exists at the interface between the Cu alloy and the oxide semiconductor film, so that oxygen does not diffuse from the deep part of the oxide semiconductor film.
Further, the present invention may be a display device using any of the thin film transistors described above.

  According to the TFT of the present invention, it is possible to realize the application of Cu alloy wiring without causing a decrease in the electrical characteristic value of the TFT.

It is a factor effect figure regarding mobility. It is a figure which shows a response | compatibility of the product of normalized mobility, RF power density, and processing time. It is a figure of elemental composition distribution clarified from the TEM-EELS analysis. No. in Table 1 4 and no. It is a figure which shows the depth distribution of the oxygen of 13 Si semiconductor side. No. in Table 1 4 and no. It is a figure which shows the result of EELS spectrum analysis of 13 oxygen. It is the figure which showed the mode of the interface observation by TEM. It is the figure which showed the mode of the interface observation by TEM. It is the figure which showed the mode of the interface observation by TEM. It is the figure which showed the mode of the interface observation by TEM. It is a figure which shows distribution of oxygen and the atomic concentration of an addition element of oxide semiconductor TFT. 6 is a cross-sectional view showing a manufacturing process of the thin film transistor of Example 1. FIG. No. in Table 1 4, no. 13 is a diagram illustrating transfer characteristics of TFTs according to the related art and the prior art. It is sectional drawing which shows the manufacturing process of the thin-film transistor of Example 20. It is a figure which shows Example 20 and the transfer characteristic of TFT of a prior art. 42 is a diagram illustrating a pixel configuration example of a thin film transistor substrate of a liquid crystal display device according to Example 35. FIG. FIG. 38 is a cross-sectional view showing a configuration example of a liquid crystal display device of Example 35.

  Hereinafter, a TFT manufacturing method and structure according to an embodiment of the present invention, and a technique for applying it to a display device will be described in detail with reference to the drawings.

  First, prior to the detailed description of the embodiment, regarding TFTs using Cu alloy for wiring, the reason why the electrical characteristic value is reduced and the method of improving the reason are as follows. This will be explained separately for each case. An example of the structure will be described in Example 1.

<When the semiconductor layer is a silicon film>
When the semiconductor layer is a silicon film and a Cu alloy is applied to the SD electrode wiring, the silicon film does not sufficiently contain oxygen necessary for self-formation of the additive element oxide film. Oxidation is performed to modify the upper layer (surface layer) of the silicon film to temporarily form a silicon oxide film (SiO _x ). A TFT was fabricated by the same method as the method described in Patent Document 1 and the electrical characteristics were evaluated. However, the mobility was significantly lower than that of a TFT to which Mo of conventional wiring was applied. This decrease in mobility causes a decrease in on-current, which causes a problem of increasing the drive voltage.

Therefore, in order to determine the factor of this mobility decrease, an L9 orthogonal table is prepared from three control factors of “strength of oxidation treatment”, “amount of added element”, and “film thickness of Cu alloy”, and the mobility decrease The main factors were investigated. The strength of the oxidation treatment was adjusted by the RF power density of the oxygen plasma treatment, and manganese (Mn) was used as an additive element in Cu. At each level, the RF power density is 0.22, 0.44, 0.89 W / cm ² , the Mn concentration in the Cu alloy is 2, 4, 10 atomic%, and the film thickness of the Cu alloy Was set to 17, 33, and 50 nm.

  The size of the evaluated element was calculated from the saturation region where the channel length (L) was 10 μm and the channel width (W) was 100 μm, and the source / drain voltage (Vds) was 10 V. The reason for selecting this element size is that it is close to the size actually applied to the display device, and the influence of the parasitic resistance can be clearly observed when the channel length L is 1 to 100 μm.

  In addition, the mobility was normalized by the mobility value of the TFT to which Mo of conventional wiring was applied, and the case of the same value was set to 1.0.

  FIG. 1 is a factor effect diagram of mobility. As a result, the factor in which the normalized mobility largely fluctuates due to different parameters (A1 to A3, B1 to B3, C1 to C3), that is, the strength of the oxidation treatment is the main factor for the decrease in mobility, that is, the silicon film It was found that the depth distribution of oxygen inside was important.

  Therefore, the correspondence between the oxygen depth distribution and the mobility of the TFT was investigated, and an optimum oxygen depth distribution that does not cause a decrease in mobility was obtained. The RF power density and treatment time of the oxygen plasma treatment were adjusted to adjust the oxygen depth distribution. A detailed manufacturing method of the TFT will be described in the column of Example 1 below. For the same reason as described above, the evaluation element has a channel length (L) of 10 μm and a channel width (W) of 100 μm. Further, the mobility of the TFT to which the Cu alloy wiring was applied was normalized by the mobility value of the TFT to which Mo of the conventional wiring was applied, and the case of the same value was set to 1.0. In addition, the product of the RF power density and the treatment time was determined as an index representing the strength of the oxidation treatment, and the correspondence between the value and the normalized mobility was obtained. Furthermore, the case where the mobility of the TFT to which Mo of the conventional wiring is applied is larger than that of the TFT, the case where it is approximately equal is Δ, and the case where a clear decrease (deterioration) is seen is determined as X. Table 1 shows the results.

From Table 1, it was found that the mobility largely depends on the RF power density and decreases as the RF power density increases. This is because, as the RF power density increases, the implantation of oxidizing species becomes stronger, and oxygen atoms are introduced deep into the silicon semiconductor film. As a result, the remaining oxide on the semiconductor layer side does not match the additive element oxide film. It is presumed that the silicon film becomes a parasitic resistance. No. It can be seen that when the RF power density of 5 is 0.44 W / cm ² and the processing time is 120 seconds, the mobility is lower than that of the conventional wiring TFT.

Therefore, for example, the optimum oxygen depth distribution in which the film quality variation is relatively small and the mobility is not lowered in a short processing time is No. 4 is realized with an RF power density of 0.44 W / cm ² and a processing time of 60 seconds. No. No. 7 has a mobility superior to that of the conventional wiring even when the RF power density is 0.67 W / cm ² and the processing time is 60 seconds. Since the processing time of No. 8 has a clear decrease in mobility of 120 seconds, No. 4 is preferred.

FIG. 2 is a diagram showing the correspondence between the normalized mobility and the product of RF power density / processing time in Table 1. As shown in FIG. 2, it was found that the normalized mobility depends on the value of the product of the RF power density and the processing time. Then, it was found that when the product value of the RF power density and the processing time is 52.8 W · sec / cm ² or less, mobility equal to or higher than that of the conventional wiring can be obtained. Considering the variation, it is preferably 60 W · sec / cm ² or less, and more preferably 50 W · sec / cm ² .

Accordingly, next, the depth distribution of oxygen and its chemical bonding state, transmission electron microscope electron energy loss spectroscopy: Comparison with (TEM-EELS T ransmission E lectron M icroscopy and E lectron E nergy L oss S pectroscopy) investigated. The sample used for the comparison is No. 1 in Table 1. 1, no. 4, no. 13 and a sample in which Cu atoms were diffused deep into the silicon semiconductor film for reference. First, FIG. 3 shows the elemental composition distribution clarified by TEM-EELS analysis (with Cu diffusion in (a)).

Here, phosphorus (P) to be introduced for the ohmic contact of the Cu alloy layer and the Si semiconductor layer, since it can not be detected by EELS analysis, energy dispersive X-ray analysis (EDX: E nergy D ispersive X -ray spectroscopy) and combined with the results of the EELS analysis.

  As shown in FIG. 3 (a), in the sample in which Cu atoms are diffused deep into the silicon semiconductor film, the peak value of oxygen atoms is as low as about 30 atomic%, and FIGS. 3 (b), (c), ( No. of Table 1 in the part which suppressed the diffusion of Cu atom shown by d). 1, no. 4, no. The peak value of 13 samples was 40 atomic% or more. No. 1 in Table 1 of FIG. In 13, the electrical characteristics are clearly degraded. 3B and No. 1 in Table 1 of FIG. 1, No. 1 in Table 1. In No. 4, the electrical characteristics are good, and oxygen atoms are 40 atom% and 58% at the interface of the Si semiconductor film. Good values are obtained at these oxygen concentrations.

Therefore, in order to suppress the diffusion of Cu atoms into the Si semiconductor layer, it is necessary that the oxygen atoms be 40 atomic% or more and 66 atomic% or less at the interface between the Cu alloy layer and the Si semiconductor film. Incidentally, 66 atomic% is a value derived from the form of a silicon dioxide film (SiO ₂ ) to which oxygen cannot be further applied.

  Next, from the viewpoint of mobility, the depth distribution of oxygen on the Si semiconductor layer side and its chemical bonding state were compared. 4 shows No. 1 in Table 1 having excellent mobility. No. 4 and a decrease in mobility was observed. It is a figure which shows the depth distribution of the oxygen of 13 Si semiconductor side.

  As shown in FIG. 4, since the peak value of oxygen exists at the interface between the Cu alloy and the Si semiconductor layer, the horizontal axis in the figure is the distance from the peak position to the Si semiconductor layer side. The standardized mobility was as low as 0.62, No. As shown in FIG. 4, the oxygen depth distribution of the sample No. 13 has a higher mobility than the conventional wiring. It shows a high value up to a position clearly deeper than that of 4 (about 1 to 3 nm). Therefore, as described above, oxygen atoms are in the range of 40 atomic% to 66 atomic% at the interface of the Si semiconductor film. It was found that the cause of the mobility decrease in 13 is that the silicon oxide film remaining on the Si semiconductor layer side becomes a parasitic resistance. Here, the oxygen of several atomic% detected in the deep part (3.0 nm or more) of the Si semiconductor layer in FIG. 4 is an artifact caused by the background drawing. Based on this, when the degree of depth distribution of oxygen that does not cause a decrease in mobility is defined, the distance at which the oxygen distribution is 10 atomic% from the peak value or from the interface between the Cu alloy layer and the Si semiconductor layer is defined as the silicon oxide film thickness. When defined, it is understood that the film thickness should be 1.8 nm or less. Further, when the distance from the peak value or from the interface between the Cu alloy layer and the Si semiconductor layer is defined as the silicon oxide film thickness, the film thickness is 1.6 nm or less, from the peak value or from the Cu value. When the distance at which the oxygen distribution is 20 atomic% from the interface between the alloy layer and the Si semiconductor layer is defined as the silicon oxide film thickness, the film thickness is 1.4 nm or less, from the peak value or between the Cu alloy layer and the Si semiconductor layer. When the distance at which the oxygen distribution is 25 atomic% from the interface is defined as the silicon oxide film thickness, it can be seen that the film thickness should be 1.2 nm or less.

In addition, from the chemical bonding state of oxygen, No. 1 in Table 1 4 (FIG. 5A) and No. 4 13 (FIG. 5B) was compared. FIG. 5 is a diagram showing the results of EELS spectrum analysis of silicon. The horizontal axis is energy loss, and the vertical axis is absorption intensity. The spot size of the beam is 0.7 nmφ. No. In the sample No. 4, the peak near the energy loss 110 eV suggesting the silicon oxide film (SiO _x ) is weak around the peak value of the oxygen depth distribution, that is, only at the interface (C) between the Cu alloy layer and the Si semiconductor layer. Although it can be seen, no. In 13 samples, it was clearly observed even at a location 1 nm away from the interface between the Cu alloy layer and the Si semiconductor layer (C and D). From this, it can be seen that the cause of the mobility decrease is the silicon oxide film remaining on the Si semiconductor layer side.

  6A to 6D are diagrams showing the results of observing the interface elements of the elements shown in Table 1 with a TEM. The elements observed were No. 1 in Table 1 from FIG. 1, no. 3, no. 4, no. 13 four elements.

  Element No. In No. 1, there was no problem in the mobility value (decrease in value), but peeling of the Cu wiring film occurred several months after the device was fabricated. 6A (a) is a magnification of 200,000 times, and FIG. 6A (b) is a magnification of 500,000 times. The same applies to FIGS. 6B to 6D.

As shown in FIG. In one element, the linear density of the number of diffusions (the number of diffusion points) is 12/480 nm, which is larger than other elements. Thus, when there are many diffusing parts, stress generated from the diffusing parts increases and film peeling occurs, making it difficult to use as a product. Therefore, in order to ensure adhesion over a long period of several months or more, it is necessary to reduce the number of diffusion sites as much as possible. No. in Table 1 In 14 elements other than 1, no film peeling occurred. Therefore, it was found that the product of the RF power density and the processing time needs to be 26.4 W · sec / cm ² or more in order to ensure adhesion. Further, from the results of FIGS. 6B and 6C, it is understood that the linear density of the number of diffusions should be 7 pieces / 480 nm or less in order to ensure adhesion. In addition, since the Cu alloy layer and the semiconductor layer have no two-dimensional anisotropy of the film quality, in terms of the surface density of the number of diffusion, the adhesiveness is 7 × 7/480 × 480 nm ² or less. It can be seen that it can be secured. In FIG. In the element 13, the diffusion location is 0, but the mobility is clearly lowered as described above, and thus it cannot be used for a product.

  From the above results, according to this embodiment, the semiconductor layer is mainly a silicon film, and the depth distribution of the atomic concentration of oxygen in the oxide film has a peak value of 40 atomic% to 66 atomic%. When the distance from the peak value of the atomic concentration of oxygen or the oxygen distribution from the interface between the source and drain electrodes and the semiconductor layer is defined as 10 atomic% is defined as the silicon oxide film thickness, When the film thickness is 1.8 nm or less and the distance from the peak value or from the interface between the Cu alloy layer and the Si semiconductor layer that the oxygen distribution is 15 atomic% is defined as the silicon oxide film thickness, the film thickness is 1.6 nm or less. When the distance from the peak value or from the interface between the Cu alloy layer and the Si semiconductor layer is defined as the silicon oxide film thickness, the film thickness is 1.4 nm or less. When oxygen distribution from the interface of u alloy layer and the Si semiconductor layer is defined as a silicon oxide film thickness the distance to be 25 atomic%, the film thickness is found to be good 1.2nm or less, to.

When the oxidation treatment for forming the oxide film is a plasma oxidation method, the RF power density of the plasma oxidation method is 0.22 or more and 0.67 W / cm ² or less, and the treatment time is 60 seconds. It is preferably 240 seconds or less, or the product of the RF power density and the processing time is preferably 26.4 Wsec / cm ² or more and 52.8 Wsec / cm ² or less. It is preferable that the linear density of the portion where the constituent materials of the source electrode and the drain electrode are diffused into the semiconductor layer at the interface of the semiconductor layer is 7 or less on average per distance of 480 nm.
It can be seen that by satisfying the above conditions, a thin film transistor substrate using Cu alloy wiring excellent in electrical characteristics and reliability can be produced.

<When the semiconductor layer is an oxide semiconductor film>
Next, the case where the semiconductor layer is an oxide semiconductor film is described. In the case where the semiconductor layer is an oxide semiconductor film and a Cu alloy is applied to the SD electrode wiring, the element-added oxide film is formed by the additive element in the Cu alloy depriving oxygen in the oxide semiconductor. Therefore, the equilibrium oxygen potential of the oxide formation reaction of the additive element in the Cu alloy is smaller than that of at least one element constituting the oxide semiconductor layer. At this time, the number of free electrons increases in the oxide semiconductor film in the vicinity of the interface from which oxygen has been removed, and the oxide semiconductor film is modified into an n ⁺ oxide semiconductor film having metallic properties. Accordingly, there is an advantage that a carrier injection barrier originally existing between the additive element oxide film and the oxide semiconductor is lowered and mobility is increased.

  However, when the additive element in the Cu alloy deprives oxygen from the oxide semiconductor, external diffusion of oxygen occurs from the semiconductor layer to the Cu alloy film so as to compensate for it, and oxygen defects increase in the oxide semiconductor film. The number of free electrons increases. As a result, a negative shift of the threshold voltage and an increase in the subthreshold coefficient occur, and the current rising characteristic is deteriorated.

In addition, an oxide semiconductor having a larger number of free electrons than an Si semiconductor or the like originally has a tendency to operate normally on (depletion) having a large current value even when the gate voltage is 0 V. When the carrier injection barrier with the oxide semiconductor is lowered, this original characteristic appears clearly. It is difficult to design a normally on TFT, and for example, it is difficult to apply it to a driver circuit or a pixel switch transistor provided in the periphery of the panel. Therefore, maintaining the carrier injection barrier between the additive element oxide film and the oxide semiconductor without generating an n ⁺ oxide semiconductor film results in a normally-off (enhancement) operation and facilitates circuit design. .

  From the above viewpoint, in the case where the semiconductor layer is an oxide semiconductor film, in order to use a Cu alloy for wiring without causing a negative threshold voltage shift, a subthreshold coefficient increase, and a normally-on operation, the oxide semiconductor film It is required to suppress the diffusion of oxygen into the Cu alloy layer. In this method, an oxide semiconductor film is subjected to an oxidation treatment before the Cu alloy is formed, and the surface thereof is temporarily modified to an insulator. As a result, even when the Cu alloy is formed and the additive element diffuses in the treatment with heat to form the additive element oxide film, necessary and sufficient oxygen exists at the interface between the Cu alloy and the oxide semiconductor film. Diffusion of oxygen from the deep portion of the oxide semiconductor film does not occur.

FIG. 7 is a diagram showing a concentration distribution of the additive element and oxygen when the additive element is, for example, Mn in the Cu alloy / oxide film (for example, MnO _x ) / oxide semiconductor layer. FIG. 7B is a diagram illustrating an example described in Patent Document 2, and FIG. 7A is a diagram illustrating an example according to the present embodiment. Here, as shown in FIG. 7A, the peak value of the oxygen concentration needs to be higher than the peak value of the concentration of the additive element. By doing so, as described above, necessary and sufficient oxygen exists at the interface between the Cu alloy and the oxide semiconductor film, so that oxygen does not diffuse from the deep part of the oxide semiconductor film.

  As a final form, as shown in FIG. 7B, when the peak value of the oxygen concentration is lower than the peak value of the concentration of the additive element, oxygen diffusion may reach the Cu alloy layer. Recognize. On the other hand, as shown in FIG. 7A, the atomic concentration distribution of oxygen has a peak at the interface between the oxide semiconductor and the Cu alloy, and the peak value is larger than the peak value of the additive element in the Cu alloy. Thus, an additive element that does not allow oxygen diffusion to reach the Cu alloy layer is also difficult to diffuse into the oxide semiconductor layer. Therefore, it can be seen that the additive element and oxygen each remain in the oxide film and do not diffuse further. A detailed manufacturing method of such a TFT will be described in Example 2 below.

  Hereinafter, examples in which the semiconductor layer is a silicon film and in which the semiconductor layer is an oxide semiconductor film will be described.

[Example 1]
<When the semiconductor layer is a silicon film>
Below, the manufacturing method of TFT of Example 1 is demonstrated. The TFT of Example 1 has a top contact structure in which a semiconductor layer is formed of a silicon film, is a bottom gate type, and a source electrode and a drain electrode are formed after the semiconductor layer is formed. Since the TFT structure becomes complicated if an accurate film thickness and size are reflected, the figure is schematically shown.

  FIG. 8 is a diagram showing a manufacturing process of the TFT according to this example, and FIGS. 8A to 8D are cross-sectional views of the TFT at each step.

  First, a Cu alloy 2 is formed by sputtering or the like on a substrate 1 made of an insulating material such as non-alkali glass. The film thickness of the Cu alloy 2 is, for example, about 10 nm to 150 nm, and preferably 20 nm to 50 nm. Here, the Cu alloy 2 to be deposited plays a role of improving the adhesion to the substrate 1. Examples of the additive element in the Cu alloy 2 include manganese (Mn), magnesium (Mg), calcium (Ca), nickel (Ni), zinc (Zn), silicon (Si), aluminum (Al), and beryllium (Be ), Gallium (Ga), indium (In), iron (Fe), titanium (Ti), vanadium (V), cobalt (Co), zirconium (Zr), hafnium (Hf), cerium (Ce), etc. More than the kind, the addition amount is preferably 0.5 to 20 atomic%. Furthermore, the Cu alloy 2 may contain 0.01 to 10 atomic% of phosphorus (P) because the production of the sputtering target material becomes easy. It is desirable that the substrate 1 contains a necessary and sufficient number of oxygen atoms in advance so that the additive element in the Cu alloy 2 diffuses to the interface and forms an oxide in a manufacturing process involving heat later. For example, an alkali-free glass substrate satisfies this condition. In Example 1, a Cu-Mn alloy in which 4 atomic% of Mn was added to Cu was deposited to a thickness of 50 nm. The sputtering target material used for film formation was manufactured by the following method. A furnace in which oxygen-free copper with a purity of 3N or more and Mn flake material with a purity of 3N or more are charged in a crucible at a blending ratio of 4.7 at%, sealed at a temperature of 1100 to 1200 ° C., and the atmosphere is replaced with Ar gas. Was dissolved. When the molten metal concentration was sufficiently uniform, the hot water was poured into the mold. The oxide film (black skin) on the surface of the obtained ingot was removed, hot rolling was performed at 850 ° C., and this was finished to a predetermined size by cutting to obtain a sputtering target material of this example. The reason why the additive element concentration of the sputtering target material is set to 4.7 at% is that, as a result of the study, the additive element concentration in the electrode film is 15% to 50% lower than the additive element concentration in the sputtering target material. This is because they found it. This is presumably because Cu and the additive element once deviate in the plasma state during sputtering, and Cu preferentially adheres as a film. Since the rate of decrease varies depending on the type and concentration of the element, the rate of decrease is calculated according to each combination, and an electrode film having a predetermined additive element concentration is obtained by adding a large amount of decrease to the sputtering target material in advance. Can do. After the formation of the Cu—Mn alloy film, pure Cu 3 is continuously formed by sputtering in the same manner. The film thickness of pure Cu3 is about 100 to 1000 nm, and preferably 200 to 500 nm. In Example 1, pure Cu was deposited on a Cu—Mn alloy by 300 nm. After performing a photolithography process on this, patterning is performed using a wet etching method, and the resist is peeled off, whereby a gate electrode 4 as shown in FIG. 8A can be formed. The substrate 1 may be a metal substrate such as a flexible plastic substrate or a stainless alloy other than alkali-free glass. In order to suppress impurity diffusion from the substrate 1 to the Cu layer, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof may be formed on the substrate 1 as a barrier film. At that time, if the barrier film does not contain sufficient oxygen atoms, a method of performing an oxidation treatment before forming the Cu alloy and forming an oxide film on the surface of the barrier film may be used. As for the gate electrode 4, Mo or Ti may be used for the barrier metal, and the conductive layer may be made of Al or Al alloy.

Next, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof is formed (deposited) as the gate insulating film 5 by plasma CVD, sputtering, coating, or the like. The film thickness is about 10 nm to 1000 nm, and 50 to 400 nm is preferable. The temperature at the time of forming the gate insulating film 5 is about 200 to 500 ° C., and the additive element in the Cu alloy 2 under the gate electrode 4 is deposited at the interface, and the oxide film having excellent adhesion at the interface with the substrate 1 (Not shown) self-form. Subsequently, a hydrogenated amorphous silicon film (a-Si: H) as the active semiconductor layer 6 and a hydrogenated amorphous silicon film doped with phosphorus (P) as the contact film 7 are formed by plasma CVD, sputtering, or coating, for example. n ⁺ a-Si: H) are sequentially formed (deposited) to form the semiconductor layer 8. The thickness of the active semiconductor layer 6 is about 10 to 300 nm, preferably 30 to 200 nm, and the thickness of the contact film 7 is about 1 to 100 nm and 5 to 60 nm. In Example 1, plasma CVD is used to dope the gate insulating film 5 with a silicon nitride film of about 350 nm, the active semiconductor layer 6 with a hydrogenated amorphous silicon film of about 180 nm, and the contact film 7 with phosphorus (P). A hydrogenated amorphous silicon film was formed to a thickness of about 25 nm. Next, as shown in FIG. 8B, a photolithography process is performed, the semiconductor layer 8 is patterned into an island shape using a dry etching method, and the resist is peeled off.

Next, oxidation treatment is performed to form an ultrathin oxide film 7 a that suppresses Cu atom diffusion into the semiconductor layer 8 on the surface of the semiconductor layer 8. At this time, the ultrathin oxide film 7a is simultaneously formed on the surface of the gate insulating film 5. As the oxidation treatment, for example, a plasma oxidation method using oxygen gas or nitrous oxide gas, a method of exposing to an oxidizing atmosphere such as ozone gas, oxygen gas or nitrous oxide gas, a thermal oxidation method of applying a heat treatment in an oxidizing atmosphere, A UV ozone oxidation method, an ozone hydroxylation method, or the like that generates ozone by introducing ozone gas and irradiates it with UV light to oxidize it can be used. In Example 1, an ultrathin oxide film 7a having a thickness of about 1 to 2 nm was temporarily formed on the semiconductor layer 8 by using a plasma oxidation method using oxygen gas. Suitable processing conditions are an RF power density of 0.044 to 0.44 W / cm ² , a processing time of 60 to 600 seconds, and a substrate temperature in the range of room temperature to 200 ° C. More preferable conditions from the reduction are RF power density of 0.22 to 0.44 Wcm ² , processing time of 60 to 240 seconds, and substrate temperature of room temperature to 150 ° C.

  Next, a laminated film made of Cu alloy 9 and pure Cu 10 is formed (deposited) in this order by sputtering. The film thickness of the Cu alloy 9 is about 10 to 150 nm, preferably 20 nm to 50 nm, and the film thickness of the pure Cu 10 is about 100 to 1000 nm, preferably about 200 to 500 nm. Examples of the element added to the Cu alloy 9 include 1 from Mn, Mg, Ca, Ni, Zn, Si, Al, Be, Ga, In, Fe, Ti, V, Co, Zr, Hf, Ce, and the like. More than one kind can be selected, and the addition amount is preferably 0.5 to 20 atomic%. Furthermore, the Cu alloy 9 may contain 0.01 to 10 atomic% of phosphorus (P) because the production of the sputtering target material becomes easy. In Example 1, a Cu—Mn alloy in which 4 atomic% of Mn was mixed in Cu was deposited (deposited) by about 50 nm, and pure Cu was deposited on the Cu—Mn alloy by about 300 nm. Thereafter, through a photolithography process, patterning is performed by a wet etching method to form the source electrode 11 and the drain electrode 12. Next, as shown in FIG. 8C, using the photoresist used for forming the source electrode 11 and the drain electrode 12 as they are, the ultrathin oxide film 7a and the contact film 7 on the channel are removed by dry etching, Strip the resist. The ultrathin oxide film 7a is as thin as about 1 to 2 nm and does not hinder the progress of dry etching.

  Next, in order to cure the active semiconductor layer 6 damaged by dry etching, hydrogen plasma treatment is performed to terminate the dangling bonds of silicon with hydrogen. Next, as shown in FIG. 8D, a protective film 13 made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof is formed by plasma CVD, sputtering, or coating. Film (deposit). In Example 1, the hydrogen plasma treatment and the formation of the protective film 13 were continuously performed without breaking the vacuum. The thickness of the protective film 13 is about 100 to 1000 nm, and preferably 200 to 500 nm. At this time, since the formation temperature of the protective film 13 is 200 ° C. or higher, Cu atoms and additive elements in the Cu alloy 9 under the source electrode 11 and the drain electrode 12 are precipitated at the interface. Cu atoms and additive elements deposited on the interface combine with the ultrathin oxide film 7a formed in advance on the contact film 7 to self-form an oxide film 14 having excellent adhesion and diffusion barrier properties and low electrical resistance. To do. At this time, since the oxide film 15 having excellent adhesion and diffusion barrier properties is formed in the ultrathin oxide film 7a immediately above the gate insulating film 5 as well, the source electrode 11 and the drain electrode 12 do not peel off. In Example 1, a silicon nitride film was formed on the protective film 13 to a thickness of about 300 nm. A photolithography process is performed on this, a contact hole (not shown) for exchanging electrical signals with an external device is opened, and the resist is peeled off. In this manner, a TFT having a bottom gate type top contact structure for the display device of Example 1 can be manufactured.

  Here, the result of comparing and evaluating the electrical characteristic values of Example 1 and the conventional TFT employing Mo will be described. The evaluated TFT element size is 100 μm for channel width (also referred to as gate width) W and 10 μm for channel length (also referred to as gate length) L, which is close to the element size actually used in the display device, and the parasitic resistance moves. This is an area that greatly affects the degree value. The source / drain voltage was 10 V, and the mobility and threshold voltage were calculated from the saturation region.

FIG. 4 (solid line), no. It is a figure which shows the transfer characteristic of TFT of 13 (broken line) and the prior art (thick broken line) which employ | adopted Mo. The vertical axis of the graph is the logarithm of the drain current. Mo / Cu / Mo is used for the gate electrode 4 and Mo / Cu / Mo is used for the source electrode 11 and the drain electrode 12, and the oxidation treatment is omitted in the process of the first embodiment, and the others are manufactured through similar processes. When the electrical characteristics of the TFT were evaluated, the saturation mobility was 0.71 cm ² / Vs, the saturation threshold voltage was 1.9 V, and the S value was 0.86 V / dec. No. 1 in Table 1 of the first embodiment. The electrical characteristics of TFT No. ⁴ are as follows. The saturation mobility is 0.76 cm ² / Vs, the saturation threshold voltage is 1.9 V, and the S value is 0.93 V / dec. It was performance. Further, there was no increase in off-current, and it was equivalent to the prior art TFT. This suggests that the diffusion of Cu atoms into the semiconductor layer 8 is suppressed, and that there is no silicon oxide film acting as a parasitic resistance near the interface between the source electrode 11 and the drain electrode 12 and the semiconductor layer 8. In the process of this example, the RF power density was set to 1.11 W / cm ² , and others were prepared through the same process as No. 1 in Table 1. As described above, since the silicon oxide film serving as a parasitic resistance exists in the element 13, a decrease in mobility, that is, a decrease in on-current is observed.

  Thus, according to the TFT of Example 1, oxygen atoms are present at 40 atomic% or more and 66 atomic% or less at the interface between the Cu alloy 9 and the semiconductor layer 8, and the interface between the Cu alloy 9 and the semiconductor layer 8 is present. When the distance at which the oxygen distribution is 10 atomic% is defined as the silicon oxide film thickness, when the film thickness satisfies the condition of 1.8 nm or less, Cu atoms do not diffuse and mobility does not decrease. It has been shown that alloy wiring can be applied.

  In the first embodiment, the gate electrode 4, the source electrode 11, and the drain electrode 12 are composed of a Cu alloy and pure Cu stack, but may be a single layer of Cu alloy. In this case, for example, Ca, Mg, and Zn are preferable because of the low electrical resistance. Further, a three-layer structure of Cu alloy / pure Cu / Cu alloy may be used.

  Here, an example in which a hydrogenated amorphous silicon film is used as the active semiconductor layer 6 is shown, but the technique of this embodiment is also used for microcrystalline silicon and polycrystalline silicon having higher mobility, and a laminated film thereof. It is effective. The contact film 7 may also be microcrystalline silicon, polycrystalline silicon, or a laminated film thereof. These are collectively referred to as a Si-based semiconductor layer (film).

  Furthermore, since the technique of the first embodiment is effective for a semiconductor that does not intentionally contain oxygen, the same effect can be obtained even with a SiGe film in which germanium (Ge) is mixed in a silicon film, for example. In order to further improve TFT electrical characteristics, a channel etch stopper structure in which etching is stopped in the channel layer may be employed. It may be a top gate type or a bottom contact structure in which a source electrode and a drain electrode are formed before forming a semiconductor layer.

  When the adhesion between the source electrode 11 and drain electrode 12 extending outward from the semiconductor layer 8 and the gate insulating film 5 is to be strengthened, an oxidation treatment is performed immediately after the gate insulating film 5 is formed on the gate insulating film 5. A technique for forming an oxide film is effective. If Cu atoms diffuse from the interface between the source electrode 11 and drain electrode 12 and the protective film 13 and the adhesion of the protective film 13 becomes weak, an oxidation treatment may be performed immediately before the protective film 13 is formed. .

[Examples 1 and 2 to 19]
As shown in Table 2, in Example 1, the element to be added to the copper alloy electrode was Mo, but in Examples 2 to 19, the components shown in Table 2 and the target materials having the added concentrations were used, respectively. A copper alloy electrode having components and target addition concentrations was formed in the same manner as in Example 1 to produce a thin film transistor. The actual additive element concentration of the source / drain copper alloy electrode was quantified using EDX (energy dispersive X-ray spectroscopy) by removing the substrate during the manufacturing process. The manufactured thin film transistor was left in the atmosphere at 25 ° C. for 60 days, and the presence or absence of peeling between the Si semiconductor layer and the source / drain copper alloy electrode was examined with a scanning electron microscope. Moreover, the presence or absence of etching residue when the source / drain copper alloy electrode in the manufacturing process of the thin film transistor was formed by etching was investigated by SEM. The etching solution used was phosphoric acid: 5 wt%, ammonium dihydrogen phosphate: 5 wt%, hydrogen peroxide: 2 wt%, and water: the balance. These results are also shown in Table 2.

  As a comparative example, a copper alloy electrode was formed using a pure Cu target material and a copper alloy target material having an addition concentration different from the range of the present invention, and the Si semiconductor layer and the source / drain copper alloy electrode of the manufactured thin film transistor were separated. Comparative examples 1 to 3 show the results of a similar investigation on the presence or absence of etching and the presence or absence of etching residues.

  In Examples 1 to 19, since the additive element concentration of the sputtering target material is increased by 15% to 50% from the target concentration of the source / drain copper alloy electrode, the actual electrode concentration is also in accordance with the target. Moreover, since the element which improves adhesiveness was added 0.5-20 at%, peeling of the copper alloy electrode was not seen. Furthermore, no etching residue was observed in the range of 0.5 to 20 at%.

  On the other hand, since there was no additive element in Comparative Example 1, peeling of the copper alloy electrode occurred. In Comparative Example 2, since the additive element concentration of the sputtering target material is the same as the target additive element concentration of the copper alloy electrode, the actual additive element concentration of the copper alloy electrode is 0.5 at% or less, and peeling of the copper alloy electrode is observed. It was. In Comparative Example 3, since the concentration of the additive element in the electrode exceeded 20%, a residue was generated during the etching.

[Example 20]
<When the semiconductor layer is an oxide semiconductor film>
A method for manufacturing the TFT of Example 20 of the present invention will be described below. The TFT of Example 20 has a top contact structure in which a semiconductor layer is formed of an oxide semiconductor film, is a bottom gate type, and a source electrode and a drain electrode are formed after the semiconductor layer is formed. It should be noted that the TFT structure is complicated if the accurate film thickness and size are reflected, and therefore, schematically shown in the figure. In addition, a part of the description overlapping between the present embodiment 20 and the embodiment 1 is omitted.

  FIGS. 10A to 10D are views showing a cross section of the TFT at each step. First, as in Example 1, a Cu alloy 2 is formed (deposited) on a substrate 1 made of an insulating material such as alkali-free glass by a sputtering method. Next, pure Cu3 is similarly continuously deposited (deposited) by sputtering. After performing a photolithography process on this, patterning is performed using a wet etching method, and the resist is peeled off. Here, the gate electrode 4 as shown in FIG.

  Next, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or a laminated film thereof is formed as the gate insulating film 5 by plasma CVD, sputtering, coating, or the like. (accumulate. The film thickness is about 10 nm to 1000 nm, preferably 50 to 400 nm. At this time, the temperature at the time of film formation is about 200 to 500 ° C., and the additive element in the Cu alloy 2 under the gate electrode 4 is precipitated at the interface, and the oxide film having excellent adhesion at the interface with the substrate 1 ( Self-forming) (not shown).

Next, if necessary, an oxidation process is performed to form an ultrathin oxide film (not shown) on the surface of the gate insulating film 5. The reason is to reduce hydrogen mixed from the gate insulating film 5 into the oxide semiconductor film in addition to suppressing Cu atom diffusion into the gate insulating film 5.

  Next, an oxide semiconductor is formed (deposited) as the active semiconductor layer 6 by plasma CVD, sputtering, coating, or the like. Examples of oxide semiconductors include zinc oxide, indium oxide, gallium oxide, tin oxide, copper oxide, zirconium oxide, titanium oxide, aluminum oxide copper, zinc tin oxide, zinc oxide indium, gallium indium oxide, zinc gallium tin oxide, and oxide. Examples thereof include indium magnesium, zinc oxide, indium hafnium, and zinc gallium indium, and are made of an oxide containing at least one element selected from Zn, In, Ga, Sn, Al, Ti, Mg, Zr, Cu, and Hf. Among them, it is preferable to use an amorphous zinc gallium indium oxide (a-InGaZnO) -based oxide semiconductor that is excellent in uniformity of electrical characteristics of the TFT. The thickness of the active semiconductor layer 6 is about 1 to 200 nm, and 10 to 100 nm is suitable for adjusting the gate voltage to be turned off to around 0V.

  Next, as shown in FIG. 10B, a photolithography process is performed, the active semiconductor layer 6 is patterned into an island shape using a dry etching method or a wet etching method, and the resist is peeled off. The island-shaped patterning may be formed using a lift-off method. In that case, a photolithography process is performed before the active semiconductor layer 6 is formed.

  Next, oxidation treatment is performed to temporarily modify the upper layers of the active semiconductor layer 6 and the gate insulating film 5 to the insulating film 6a. In Example 20, a plasma oxidation method using nitrous oxide gas is employed because of its strong oxidizing power. As a result, even if the additive element in the Cu alloy 2 is diffused thereafter to form the additive element oxide film, necessary and sufficient oxygen is present at the interface between the Cu alloy 2 and the active semiconductor layer 6. Diffusion of oxygen from the deep part of the film 6 does not occur.

  Next, similarly to Example 1, a laminated film made of Cu alloy 9 and pure Cu 10 is formed in this order by sputtering. The film thickness of the Cu alloy 9 is about 10 to 150 nm, preferably 20 nm to 50 nm, and the film thickness of the pure Cu 10 is about 100 to 1000 nm, preferably about 200 to 500 nm. At this time, in order to form the additive element oxide film, the equilibrium oxygen potential of the oxide formation reaction of the additive element in the Cu alloy 9 is smaller than that of at least one element constituting the active semiconductor layer 6. Select For example, one or more types can be selected from Mn, Mg, Ca, Zn, Si, Al, Be, Ga, Ti, V, Zr, Hf, Ce, etc., and the addition amount is 0.5 to 20 atomic%. Is preferred. Furthermore, the Cu alloy 9 may contain 0.01 to 10 atomic% of phosphorus (P) because the production of the sputtering target material becomes easy. The manufacturing method of a sputtering target material can take the same method as Example 1, and it is good to make the addition element density | concentration of sputtering target material increase 15 to 50% from the target addition element density | concentration in a copper alloy electrode. In Example 20, a Cu—Mn alloy was used as the Cu alloy 9. The equilibrium oxygen potential of the Mn oxide formation reaction is smaller than that of the constituent elements In, Ga, Zn of the active semiconductor layer 6 and satisfies the condition. Thereafter, as shown in FIG. 10C, a source electrode 11 and a drain electrode 12 are formed through a photolithography process and patterned by a wet etching method or a dry etching method. At this time, the insulating film 6a on the active semiconductor layer 6 protects the active semiconductor layer 6 from damage caused in the etching process, and also serves as an etch stopper layer.

  Next, as shown in FIG. 10D, the protective film 13 made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film thereof is formed by plasma CVD, sputtering, coating, or the like. Is deposited (deposited). The thickness of the protective film 13 is about 100 to 1000 nm, and preferably 200 to 500 nm. At this time, since the formation temperature of the protective film 13 is 200 ° C. or more, Cu atoms and additive elements in the Cu alloy 9 under the source electrode 11 and the drain electrode 12 are precipitated at the interface, and are previously formed on the active semiconductor layer 6. In combination with the insulating film 6a formed in this step, the oxide film 14 having excellent adhesion and diffusion barrier properties and having low electrical resistance is self-formed. When a part of the protective film 13 is made of a silicon nitride film, hydrogen may diffuse into the active semiconductor layer 6 and the electrical characteristics may be deteriorated. However, the insulating film 6a on the upper layer of the active semiconductor layer 6 There is also an effect of suppressing by reducing and preventing diffusion of hydrogen into the oxide semiconductor film. In addition, since the oxide film 15 having excellent adhesion and diffusion barrier properties is self-formed even in the insulating film 6a immediately above the gate insulating film 5, the film peeling of the source electrode 11 and the drain electrode 12 hardly occurs. Further, a photolithography process is performed on this, a contact hole (not shown) for exchanging electrical signals with an external device is opened, and the resist is peeled off. In this manner, the oxide semiconductor TFT of Example 20 can be manufactured.

  Here, the electrical characteristics of the present Example 20 and the prior art TFT in which the peak value of the atomic concentration of oxygen is smaller than that of the additive element are compared and evaluated. FIG. 11 is a diagram showing a schematic diagram of transfer characteristics of Example 20 and the prior art TFT. The vertical axis of the graph is the logarithm of the drain current. Looking at the transfer characteristics of the conventional TFT, the on-current is large, but a negative shift of the threshold voltage and an increase in the subthreshold coefficient occur, and the normally-on operation is performed. However, the TFT of Example 20 in which the peak value of the atomic concentration of oxygen is larger than the peak value of the additive element has a normally-off operation that rises sharply in the vicinity of the gate voltage of 0V. Therefore, according to the present Example 20, it was shown that the diffusion of oxygen from the active semiconductor layer 6 is suppressed, and the Cu alloy wiring can be applied to the oxide semiconductor TFT.

  In Example 20, the gate electrode 4, the source electrode 11, and the drain electrode 12 are composed of a Cu alloy and pure Cu laminate, but may be a single layer of Cu alloy. In this case, for example, Ca, Mg, and Zn are preferable because of the low electrical resistance. Further, a three-layer structure of Cu alloy / pure Cu / Cu alloy may be used. The oxide semiconductor used for the active semiconductor layer 6 may be amorphous or polycrystalline, and can be applied to a stacked film of these. A channel etch stopper structure may be employed to further improve TFT electrical characteristics. A top gate type or a bottom contact structure may be used.

  When Cu atoms diffuse from the interface between the source electrode 11 and drain electrode 12 and the protective film 13 and the adhesion of the protective film 13 becomes weak, an oxidation treatment may be performed immediately before the protective film 13 is formed.

  In addition, in order to make the TFT electrical characteristics stable and uniform, heat treatment may be additionally performed after the oxide semiconductor is formed. The heat treatment is preferably performed after the source electrode 11 and the drain electrode 12 are formed. This is because the diffusion of the additive element in the source electrode 11 and the drain electrode 12 is promoted, and the oxide film 14 and the oxide film 15 are easily obtained.

[Examples 20 and 21-34]
As shown in Table 3, in Example 20, the element to be added to the copper alloy electrode was Mo, but in Examples 21 to 34, the components shown in Table 3 and the target materials having the added concentrations were used, respectively. Copper alloy electrodes having components and target addition concentrations were formed in the same manner as in Example 20 to manufacture thin film transistors. The actual additive element concentration of the source / drain copper alloy electrode was quantified using EDX (energy dispersive X-ray spectroscopy) by removing the substrate during the manufacturing process. The manufactured thin film transistor was left in the atmosphere at 25 ° C. for 60 days, and the presence or absence of peeling between the oxide semiconductor layer and the source / drain copper alloy electrode layer was examined with a scanning electron microscope. Moreover, the presence or absence of etching residue when the source / drain copper alloy electrode in the manufacturing process of the thin film transistor was formed by etching was investigated by SEM. The etching solution used was phosphoric acid: 5 wt%, ammonium dihydrogen phosphate: 5 wt%, hydrogen peroxide: 2 wt%, and water: the balance. These results are also shown in Table 3.

  As a comparative example, whether the equilibrium oxygen potential of the oxide formation reaction of the pure Cu target material and the copper alloy target material and the additive element whose additive concentration is different from the range of the present invention is larger than that of the element constituting the oxide semiconductor layer. A copper alloy electrode is formed using a copper alloy target material added with Ni, In, Fe, and Co having the same value, whether or not the oxide semiconductor layer and source / drain electrode layer of the manufactured thin film transistor are peeled off, etching The result of having investigated similarly the presence or absence of a residue is shown to Comparative Examples 6-12.

  In Examples 20 to 34, since the additive element concentration of the sputtering target material is increased by 15% to 50% from the target concentration of the source / drain electrode, the actual electrode concentration is also in accordance with the target. Moreover, since the element which improves adhesiveness was added 0.5-20 at%, peeling of the copper alloy electrode was not seen. Furthermore, no etching residue was observed in the range of 0.5 to 20 at%.

On the other hand, in Comparative Example 6, since there was no additive element, peeling of the copper alloy electrode occurred. In Comparative Example 7, since the additive element concentration of the sputtering target material was the same as the target additive element concentration of the electrode, the actual additive element concentration of the electrode was 0.5 at% or less, and peeling of the copper alloy electrode was observed. In Comparative Example 8, since the concentration of the additive element in the electrode exceeded 20%, a residue was generated during the etching. In Comparative Examples 9 to 12, the equilibrium oxygen potential of the oxide formation reaction of the additive element is greater than or equal to that of the element constituting the active semiconductor layer 6, so that the additive element oxide layer is present at the interface with the oxide semiconductor layer. It did not form and the adhesion decreased and peeling of the copper alloy electrode was observed.

[Example 35]
<Display device>
FIG. 12 and FIG. 13 illustrate the contents of Example 35. A method of using the TFTs of Examples 1 and 20 for a display device will be described using a liquid crystal display device as an example. In order to avoid complexity, the detailed structure of the TFT is not shown.

  FIG. 12 is a diagram illustrating a pixel configuration example on the TFT substrate 101 in the active matrix liquid crystal display device 100 according to the thirty-fifth embodiment. As shown in FIG. 12, it has a scanning line 102 on a TFT substrate 101 and a signal line 103 formed in a direction perpendicular to the scanning line 102. A TFT 104 is provided at a point where the scanning line 102 and the signal line 103 intersect, and a part of the wiring of the TFT 104 is connected to the pixel electrode 105 connected to the TFT 104. A storage capacitor 106 is formed using part of the pixel electrode 105 and the scanning line 102. In the step of forming the scanning line 102, the gate electrode 4 (not shown) of the TFTs of Example 1 and Example 20 is used as the source of the TFT of Example 1 and Example 20 in the step of forming the signal line 103. Electrode 11 (not shown) and drain electrode 12 (not shown) are formed.

  FIG. 13 is a cross-sectional view illustrating a configuration example of an active matrix liquid crystal display device according to Example 35. In FIG. As shown in FIG. 13, the liquid crystal display device 100 includes a light source 111, a polarizing plate 112, a TFT substrate 101, a TFT 104, an insulating film 113, a pixel electrode 105, an alignment film 114, a liquid crystal layer 115, a spacer 116, a common electrode 117, a color. A filter 118, a black matrix 119, a color filter substrate 120, and a polarizing film 121 are included.

Here, a display control method of the liquid crystal display device 100 will be briefly described. Only a specific polarization component of the light emitted from the light source 111 passes through the polarizing plate 112 and travels toward the liquid crystal layer 115. The liquid crystal layer 115 controls the gradation of the pixel by adjusting the light transmittance that passes through the polarizing film 121 in accordance with the voltage supplied to the pixel electrode 105 and the common electrode 117.

  Next, a method for controlling the liquid crystal layer 115 will be briefly described with reference to FIG. First, when a gate signal is applied from the scanning line 102 to the TFT 104, the TFT 104 is turned on, and a signal voltage applied to the signal line 103 is applied to the pixel electrode 105 and the storage capacitor 106 via the TFT 104. Thereby, a desired voltage is applied to the liquid crystal layer 115, and the liquid crystal molecules operate to control the light transmittance. At this time, the storage capacitor 106 has a role of holding a voltage signal. That is, even when the TFT 104 is turned off, the voltage level supplied to the liquid crystal layer 115 is adjusted to be constant until the next signal is applied.

  According to the TFT of the present embodiment, it is possible to realize the application of Cu alloy wiring without causing a decrease in the electrical characteristic value of the TFT. At this time, it is possible to apply the Cu alloy to the electrode of the thin film transistor by presenting an optimal oxygen depth distribution that suppresses the decrease in electric resistance. In the above-described embodiment, the configuration and the like illustrated in the accompanying drawings are not limited to these, and can be appropriately changed within a range in which the effect of the present invention is exhibited. In addition, various modifications can be made without departing from the scope of the object of the present invention.

  The present invention is applicable to a thin film transistor.

1: Substrate 2: Cu alloy 3: Pure Cu
4: Gate electrode 5: Gate insulating film 6: Active semiconductor layer 6a: Insulating film 7: Contact film 7a: Ultrathin oxide film 8: Semiconductor layer (6, 7)
9: Cu alloy 10: Pure Cu
11: Source electrode 12: Drain electrode 13: Protective film 14: Oxide film (formed at the interface between the SD electrodes 11 and 12 and the semiconductor layer 8 (6 and 7))
15: Oxide film (formed at the interface between the SD electrodes 11 and 12 and the gate insulating film 5)
100: Liquid crystal display device 101: TFT substrate 102: Scanning line 103: Signal line 104: TFT
105: pixel electrode 106: storage capacitor 111: light source 112: polarizing plate 113: insulating film 114: alignment film 115: liquid crystal layer 116: spacer 117: common electrode 118: color filter 119: black matrix 120: color filter substrate 121: polarization the film

Claims (15)

On the substrate, a gate insulating film, a Si-based semiconductor layer, a source / drain electrode having a Cu alloy layer, an oxide film formed at an interface between the source and drain electrodes and the Si-based semiconductor layer, A thin film transistor comprising:
The Cu alloy layer includes Cu and at least one additive element,
The depth distribution of the atomic concentration of oxygen in the oxide film has a peak value of 40 atomic% or more and 66 atomic% or less, and from the peak value of the atomic concentration of oxygen or the source electrode and drain electrode When the distance at which the oxygen distribution from the interface between the Si-based semiconductor layer is 10 atomic% is defined as the thickness of the oxide film, the thickness of the oxide film is 1.8 nm or less. A thin film transistor.   At the interface between the source and drain electrodes and the Si-based semiconductor layer, the line density of the portion where the constituent materials of the source and drain electrodes are diffused into the Si-based semiconductor layer is an average of 7 or less per 480 nm distance. The thin film transistor according to claim 1, wherein the thin film transistor is provided.   The Cu alloy layer includes at least one selected from Cu, Mn, Mg, Ca, Ni, Zn, Si, Al, Be, Ga, In, Fe, Ti, V, Co, Zr, Hf, and Ce. 3. The thin film transistor according to claim 1, wherein the thin film transistor comprises an additive element, and the concentration of the additive element is 0.5 to 20 at%. On the substrate, a gate insulating film, a Si-based semiconductor layer, a source / drain electrode having a Cu alloy layer containing Cu and at least one additional element, the source and drain electrodes, and the Si-based semiconductor layer, An oxide film formed on the interface of the thin film transistor, comprising:
After forming a gate electrode structure on the substrate and depositing a gate insulating film thereon,
Depositing the Si-based semiconductor film on the gate insulating film;
Forming a very thin oxide film on the surface of the Si-based semiconductor layer by a plasma oxidation method;
Forming a source / drain electrode having the Cu alloy layer,
The oxide film is formed by a plasma oxidation method, the RF power density in the plasma oxidation method is 0.22 to 0.67 W / cm ² or less, and the treatment time is 60 seconds or more and 240 seconds or less. A method for manufacturing a thin film transistor. On the substrate, a gate insulating film, a Si-based semiconductor layer, a source / drain electrode having a Cu alloy layer containing Cu and at least one additional element, the source and drain electrodes, and the Si-based semiconductor layer, An oxide film formed on the interface of the thin film transistor, comprising:
After forming a gate electrode structure on the substrate and depositing a gate insulating film thereon,
Depositing the Si-based semiconductor film on the gate insulating film;
Forming a very thin oxide film on the surface of the Si-based semiconductor layer by a plasma oxidation method;
Forming a source / drain electrode having the Cu alloy layer,
The oxide film is formed by a plasma oxidation method,
A method of manufacturing a thin film transistor, wherein a product of an RF power density and the processing time in the plasma oxidation method is 26.4 to 52.8 W · sec / cm ² .   It is a sputtering target material used for formation of the source / drain electrode which consists of a copper alloy of the thin-film transistor of any one of Claim 1 to 3, Comprising: It is more than the additive element density | concentration in a copper alloy layer (additive element) A sputtering target material having a high concentration in a range of (concentration × 15% or more and less than 50%). On the substrate, a gate insulating film having an oxide film, an oxide semiconductor layer, a source / drain electrode having a Cu alloy layer containing Cu and at least one additive element, the source electrode and the drain electrode, A thin film transistor comprising an oxide film formed at an interface with an oxide semiconductor layer, and a protective film for protecting the whole,
In the oxide film, the atomic concentration of the additive element and oxygen in the source electrode and the drain electrode has a peak, and the peak value of oxygen is larger than the peak value of the additive element.   The equilibrium oxygen potential of an oxide generation reaction of an additive element in the source electrode and the drain electrode is smaller than an equilibrium oxygen potential of at least one element constituting the oxide semiconductor layer. Thin film transistor.   The Cu alloy layer of the source electrode and the drain electrode includes at least one additive element selected from Cu, Mn, Mg, Ca, Zn, Si, Al, Be, Ga, Ti, V, Zr, Hf, and Ce. 9. The thin film transistor according to claim 7, wherein the concentration of the additive element is 0.5 to 20 at%.   The thin film transistor according to claim 7, wherein a part of the protective film is made of a silicon nitride film. On the substrate, a gate insulating film having an oxide film, an oxide semiconductor layer, a source / drain electrode having a Cu alloy layer containing Cu and at least one additive element, the source electrode and the drain electrode, A method of manufacturing a thin film transistor comprising an oxide film formed at an interface with an oxide semiconductor layer, and a protective film for protecting the whole,
In the step of forming the protective film,
In the thin film transistor, the atomic concentration of the additive element and oxygen in the source electrode and the drain electrode has a peak, and the peak value of oxygen is larger than the peak value of the additive element in the oxide film. Production method.   It is a sputtering target material used for formation of the source / drain electrode which consists of a copper alloy of the thin-film transistor of any one of Claim 7-10, Comprising: An additive element rather than the additive element density | concentration in a copper alloy layer A sputtering target material characterized in that the concentration is high in the range of concentration x 15% or more and less than 50%.   A display device using the thin film transistor according to any one of claims 1, 2, 3, 7, 8, 9, and 10.   It consists of at least one additional element selected from Cu and Mn, Mg, Ca, Ni, Zn, Si, Al, Be, Ga, In, Fe, Ti, V, Co, Zr, Hf, and Ce. A sputtering target material characterized in that the concentration of the element is 0.7 to 40 at%. A sputtering target material comprising 0.7 to 29 at% Mn and the balance being Cu.

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