JP5432771B2 - Display device and manufacturing method of display device - Google Patents

Description

  The present invention relates to a display device using a TFT substrate having a thin film transistor.

  In recent years, an active matrix display device using a thin film transistor (TFT) in a pixel circuit is required to be large and to improve image quality such as moving image performance. On the other hand, the price of display devices continues to decline at a pace exceeding expectations, and factors that push up manufacturing costs such as soaring energy resources and rare metals are also increasing. Therefore, there is an urgent need to develop further manufacturing cost reduction technology.

  As one measure for increasing the size of the liquid crystal display device, improving the image quality, and reducing the manufacturing cost, there is an attempt to change the wiring material applied to the TFT from conventional Al (aluminum) or Al alloy to Cu (copper). The Cu wiring has a lower resistance than the conventional Al wiring. Therefore, the propagation delay phenomenon in which the electrical signal transmitted through the wiring is delayed can be reduced, and the size can be further increased. It is also possible to increase the frame frequency and improve the quality of moving images. Furthermore, the Al wiring has a Mo / Al / Mo laminated structure in which the upper and lower sides of the Al film are sandwiched by expensive molybdenum (Mo) in order to suppress the generation of hillocks and ensure electrical connection with the transparent conductive film. Since Cu can be directly connected to the transparent conductive film, molybdenum can be saved. Therefore, the manufacturing cost can be reduced.

  In order to increase the size and improve the image quality of an organic EL display device, a wiring material having a resistance lower than that of a conventional Al wiring is required. The drive transistor provided in the pixel circuit of the organic EL display device controls the current flowing through the organic EL layer using the saturation region, and adjusts the luminance. If the voltage drop due to the wiring resistance cannot be ignored due to the increase in size of the organic EL display device, the assumed voltage is not supplied to the drive transistor, making it impossible to drive in the saturation region, resulting in luminance unevenness. . Therefore, application of Cu wiring is being studied to improve display quality.

  However, the following problems exist when Cu wiring is applied to TFTs in display devices such as the above-described liquid crystal display devices and organic EL display devices. Cu has poor adhesion to the underlying glass substrate and the silicon (Si) film. Further, when the base is a Si film, Cu is diffused into the Si film due to heat applied in the process after the wiring is formed, thereby degrading the TFT characteristics and lowering the display quality. As a countermeasure for such adhesion and diffusion barrier properties, there is a method of forming Mo or Mo alloy between the base film and the Cu film. However, as described above, Mo is expensive, and the laminated structure of metals having different electrochemical properties makes etching difficult, so that the manufacturing cost increases.

  Therefore, by using a Cu alloy as at least a part of the wiring material and further utilizing a thermal process, the additive element of the Cu alloy is precipitated at the interface with the base, and the additive element has excellent adhesion and diffusion barrier properties. There are methods for forming oxides. Here, the thermal process means a CVD (Chemical Vapor Deposition) process or an alignment film baking process after the wiring is formed, and it is assumed that the temperature experienced by the TFT substrate is applied in these CVD processes. ing.

  When this Cu alloy is used for the gate electrode, the underlying glass substrate contains necessary and sufficient oxygen atoms, so that oxide formation is easy. However, when a Cu alloy is used for the source / drain (SD) electrode, the underlying contact film does not have the number of oxygen atoms necessary for forming an oxide.

  Therefore, Patent Document 1 proposes a method for forming a silicon oxide layer SiOx by applying an oxygen plasma treatment before forming a Cu alloy film to modify the upper layer of the contact film as a means for applying the Cu alloy to the SD electrode. Yes.

JP 2009-4518 A

  However, as described above, when the Cu alloy is used for the source / drain electrodes of the TFT, if the contact film is subjected to an oxidation treatment, not only Si but also impurities doped in the contact film, such as phosphorus (P) or boron (B) is also oxidized. As a result, the impurities mixed in to achieve ohmic contact lose their effect, the parasitic resistance existing in the current path between the source / drain electrodes and the semiconductor layer increases, the on-characteristics of the TFT deteriorate, and the display quality is reduced. Deteriorate.

  Accordingly, in view of the above problems, the present invention provides a TFT display device that maintains good on-characteristics even when a contact film is oxidized in a TFT using a Cu alloy as a source / drain electrode. It is another object of the present invention to provide a method for manufacturing a display device. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  In view of the above object, a display device according to the present invention includes a semiconductor layer, a source electrode and a drain electrode each including a copper alloy layer including copper and one kind of additive element, and each of the source electrode and the drain electrode. A display device comprising a thin film transistor substrate comprising a contact film formed between an electrode and the semiconductor layer, and an oxide film formed between the respective electrode and the contact film, wherein the contact The film includes impurities and silicon, and the oxide film includes silicon, impurities, and oxygen, and an impurity concentration in the oxide film is lower than an impurity concentration in the contact film.

  In one embodiment of the display device according to the present invention, the oxide film may be characterized in that oxygen atoms are distributed at a predetermined concentration or more.

Further, in one embodiment of the display device according to the present invention, the oxide film may be characterized in that an oxygen atom concentration of 1.0 × 10 ²² atoms / cm ³ or more is distributed.

In one embodiment of the display device according to the present invention, the oxide film has an impurity concentration of 1 at a position where an oxygen atom concentration of 1.0 × 10 ²² atoms / cm ³ is detected on the contact film side. becomes .0 × ^{10 20} atoms / cm ³ or more, wherein the side of each electrode, at the position where the oxygen atom concentration of 1.0 × ^{10 22} atoms / cm ³ is detected, the impurity concentration is 1.0 × ^{10 19} It may be characterized in that the number is not more than pieces / cm ³ .

In the display device according to the aspect of the invention, the oxide film may have an impurity concentration at a position where an oxygen atom concentration of 1.0 × 10 ²² atoms / cm ³ is detected on the electrode side. The impurity concentration may be 1/100 or less of the impurity concentration at the position where the oxygen atom concentration of 1.0 × 10 ²² atoms / cm ³ is detected on the contact film side.

In one embodiment of the display device according to the present invention, the oxide film has an impurity concentration of less than 1.0 × 10 ²⁰ atoms / cm ^{3 at a} position where the oxygen atom concentration takes a maximum value. It is good.

  In the display device according to the aspect of the invention, in the oxide film, the impurity concentration decreases as the distance from the contact film increases, and in the oxide film, the contact is more than the position where the oxygen atom concentration becomes the maximum value. It may be characterized in that the decrease of the impurity concentration starts on the film side.

  In the display device according to the aspect of the present invention, the oxide film may be 1/10 or less of the impurity concentration in the contact film at a position where the oxygen atom concentration is maximum. .

  In one embodiment of the display device according to the present invention, the oxide film may further contain copper and the additive element.

  In view of the above object, a method for manufacturing a display device according to the present invention is a method for manufacturing a display device having a thin film transistor, which includes a step of forming a semiconductor layer, copper, and at least one additional element. An electrode forming step of forming a source electrode and a drain electrode having a copper alloy layer; a step of forming a contact film for electrically connecting each of the source electrode and the drain electrode and the semiconductor layer; A step of forming a silicon oxide film containing silicon and oxygen between each of the source electrode and the drain electrode and the contact film. In the step of forming the contact film, impurities are added. A silicon film is formed, and the step of forming the silicon oxide film is performed by using a silicon film having an impurity concentration lower than that of the silicon film as a buffer film. A step of to form, on the buffer layer, and a step of performing an oxidation treatment, and it is characterized.

  In view of the above-described object, the display device according to the present invention includes a semiconductor layer, a source electrode and a drain electrode each having a copper alloy layer containing copper and at least one additive element, and the source electrode and the drain electrode. A display device having a thin film transistor including a contact film formed between each of the electrodes and the semiconductor layer, and an oxide film formed between the respective electrode and the contact film, The contact film includes an impurity and silicon, and the oxide film includes a step of forming a silicon film having a lower impurity concentration than the contact film as a buffer film, and a step of oxidizing the buffer film. It is formed by a process.

  According to the present invention, in a TFT using a Cu alloy as a source / drain electrode or wiring, even when the contact film is subjected to an oxidation treatment, a display device in which deterioration of the on-characteristic of the TFT is prevented, and A method for manufacturing a display device can be provided. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

It is a schematic cross section which shows the structure of the display apparatus which concerns on Embodiment 1 of this invention. It is a schematic diagram which shows the mode of the pixel area | region of the thin-film transistor substrate in Embodiment 1 of this invention. It is a schematic cross section of the thin-film transistor in Embodiment 1 of this invention. It is a schematic cross section which shows the mode of the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a schematic cross section which shows the mode of the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a schematic cross section which shows the mode of the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a schematic cross section which shows the mode of the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a schematic cross section which shows the mode of the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a schematic cross section which shows the mode of the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a flowchart which shows the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a graph which shows the impurity element density | concentration and oxygen atom density | concentration of the oxide film in Embodiment 1 of this invention.

  Embodiments of a display device according to the present invention will be described below with reference to the drawings.

[Embodiment 1]
FIG. 1 is a schematic cross-sectional view illustrating the configuration of the display device according to the first embodiment. The display device in this embodiment is an active matrix type liquid crystal display device. As shown in FIG. 1, the liquid crystal display device includes a TFT substrate 101, a color filter substrate 120, a polarizing plate 112, a polarizing film 121 and a light source 111, and between the TFT substrate 101 and the color filter substrate 120. A spacer 116 is interposed between the liquid crystal layer 115 and the liquid crystal layer 115. The TFT substrate 101 includes a substrate 100, a TFT 104, an insulating film 113, a pixel electrode 105, and an alignment film 114. The color filter substrate 120 includes a substrate 100, a black matrix 119, and a color filter. The filter 118, the insulating film 113, the common electrode 117, and the alignment film 114 are included.

  FIG. 2 illustrates one of a plurality of pixel regions formed on the TFT substrate 101 in the display device according to the first embodiment. In the TFT substrate 101, a plurality of scanning lines 102 and a plurality of signal lines 103 are formed in a direction perpendicular to the scanning lines 102, and each pixel region is partitioned by these. As shown in FIG. 2, the TFT 104 is disposed at a point where the scanning line 102 and the signal line 103 intersect, and one of the source electrode and the drain electrode of the TFT 104 is connected to the pixel electrode 105. A storage capacitor 106 is provided using part of the pixel electrode 105 and the scanning line 102.

  Here, a display control method of the liquid crystal display device in the present embodiment will be briefly described. Only a specific polarization component of the light emitted from the light source 111 passes through the polarizing plate 112 and travels toward the liquid crystal layer 115. The liquid crystal layer 115 adjusts the light transmittance that passes through the polarizing film 121 in accordance with the voltage supplied to the pixel electrode 105 and the common electrode 117, whereby the gradation of the pixel is controlled.

  Next, a method for controlling the liquid crystal layer 115 will be briefly described with reference to FIG. First, when a gate signal is applied from the scanning line 102 to the TFT 104, the TFT 104 is turned on, and a signal voltage applied to the signal line 103 is applied to the pixel electrode 105 and the storage capacitor 106 via the TFT 104. Thereby, a desired voltage is applied to the liquid crystal layer 115, and the liquid crystal molecules operate to control the light transmittance. That is, even when the TFT 104 is turned off, the voltage level supplied to the liquid crystal layer 115 is adjusted to be constant until the next signal is applied.

  Here, FIG. 3 is a schematic cross-sectional view showing the configuration of the TFT according to Embodiment 1 of the present invention. Such a figure is a cross-sectional view that is generally used in order to make it easy to see the main components of the TFT. This cross section is parallel to the direction in which the carriers of the channel formed by applying the gate voltage travel.

  As shown in FIG. 3, the configuration of the TFT 104 according to the first embodiment is that a gate electrode 2, a gate insulating film 3, a semiconductor layer 4, a contact film 5, an oxide film 8, and a drain electrode are formed on an insulating substrate 100 such as glass. 9, a source electrode 10, a protective film 11 for protecting the TFT, and a pixel electrode 105 for applying a voltage to the liquid crystal layer. The drain electrode 9 and the source electrode 10 have a copper alloy layer, and this copper alloy layer contains copper and at least one kind of additive element. In the copper alloy layer, copper is the main component. In the present embodiment, the drain electrode 9 and the source electrode 10 include a copper alloy layer and a pure copper layer, and the pure copper layer is laminated on the upper side of the copper alloy layer. It may be. The semiconductor layer 4 is an active semiconductor layer that controls a current between the drain electrode 9 and the source electrode 10 when a voltage is applied to the gate electrode 2. The contact film 5 is formed between the drain electrode 9 and the source electrode 10 and the semiconductor layer 4, and is a film for electrically connecting them, and is composed of a silicon film to which an impurity element is added. The When the oxide film 8 having excellent adhesion and diffusion barrier properties and low resistance is formed, first, a silicon film having an impurity concentration lower than that of the contact film 5 (hereinafter referred to as a buffer) is formed on the contact film 5. Membrane) is temporarily provided. In this embodiment, the buffer film is an amorphous silicon film formed without adding impurities. After the buffer film is formed, part or all of the buffer film is modified by oxidation treatment to temporarily form a silicon oxide film, and the copper alloy contained in the drain electrode 9 and the source electrode 10 is accompanied by heat. The oxide film 8 is formed by being combined by the treatment. Details of the manufacturing method will be described later.

  The buffer film for forming the oxide film 8 plays a role of preventing the impurity element doped in the contact film 5 from being oxidized by the oxidation treatment. In the heat treatment for forming the oxide film 8, since the impurity element diffuses from the contact film 5, the oxide film 8 finally contains the impurity element. However, as will be described later, since the buffer film having an impurity concentration lower than that of the contact film 5 is oxidized, the concentration of the impurity element in the oxide film 8 is lower than the concentration of the impurity element in the contact film 5. . As a result, the oxide of impurities in the oxide film 8 can be reduced, an increase in parasitic resistance is suppressed, and good on-characteristics of the TFT are maintained.

  Below, the manufacturing method of TFT of Example 1 is demonstrated. 4A to 4F are cross-sectional views showing how the TFT 104 according to this embodiment is manufactured, and FIG. 5 is a flowchart showing the manufacturing process of the TFT 104 according to this embodiment. As shown in FIG. 5, the TFT substrate 101 having a thin film transistor is manufactured through the steps S501 to S510.

  First, as shown in FIG. 4A, the gate electrode 2 is formed on the substrate 100 made of an insulating material such as glass (S501). In this embodiment, in S501, first, a Cu alloy film is formed to a thickness of about 50 nm by a sputtering method. The Cu alloy film plays a role of developing adhesiveness with the glass substrate 100. As an additive element in the Cu alloy film, for example, one or more kinds of elements such as Mn, Mg, Ni, Zn, Si, Al, Fe, Ti, Co, Zr, and Hf, and the addition amount is 0.5 to 10 atomic%. preferable. In addition, it is desirable that the substrate 100 contains a necessary and sufficient number of oxygen atoms so that the additive element in the Cu alloy forms an oxide in a later step. For example, an alkali-free glass substrate satisfies this condition. Next, a pure Cu film is similarly formed by sputtering to a thickness of about 300 nm. Further, after performing a photolithography process on this, patterning is performed using a wet etching method, and the gate electrode 2 is formed as shown in FIG. 4A (S501).

  Next, as shown in FIG. 4B, the gate insulating film 3, the semiconductor layer 4, the contact film 5, and the buffer film 6 are formed (S502 to S505).

  The gate insulating film 3 in S502 is formed, for example, by forming a silicon nitride film (SiNx) with a thickness of about 350 nm by plasma CVD. At this time, the temperature at the time of film formation is 300 ° C. or more, and the additive element in the Cu alloy film under the gate electrode 2 is deposited at the interface, and an oxide film having excellent adhesion at the interface with the substrate 100 is self-formed. To do.

The semiconductor layer 4 in S503 is formed by forming a hydrogenated amorphous silicon film (a-SiH) with a thickness of about 180 nm by plasma CVD. The contact film 5 in S504 is formed by depositing a hydrogenated amorphous silicon film (n + a-Si: H) of about 25 nm while doping phosphorus (P) which is an impurity. Further, as the buffer film 6 in S506, a hydrogenated amorphous silicon film is sequentially formed to a thickness of about 5 nm without adding impurities. At this time, as shown in FIG. 4B, the buffer film 6 is formed so as to cover the contact film 5, and prevents the impurity element in the contact film 5 from being oxidized in the subsequent oxidation treatment step (S506). Take on. Further, the concentration of the impurity element contained in the contact film 5 is preferably 1.0 × 10 ²⁰ atoms / cm ³ or more. This is because when it is less than 1.0 × 10 ²⁰ pieces / cm ³ , a decrease in on-current and an increase in off-current occur. In S504, the flow rates of silane (SiH ₄ ) gas, phosphine (PH ₃ ) gas, and hydrogen (H ₂ ) gas were adjusted so as to satisfy the concentration of the impurity element. Each process of forming the semiconductor layer 4, the contact film 5, and the buffer film 6 was continuously performed in the same film formation chamber.

  Then, as shown in FIG. 4C, as a pretreatment for forming the oxide film 8, the buffer film 6 is oxidized to temporarily form the silicon oxide film 7 (S506). In this embodiment, as shown in FIG. 4C, oxygen plasma treatment using oxygen gas is applied to modify the upper layer of the buffer film 6 to form a silicon oxide film 7 of about 2 nm. At this time, since the buffer film 6 protects the contact film 5 from the oxidation treatment, an increase in parasitic resistance due to oxidation of the impurity element in the contact film 5 is suppressed. In this embodiment, the oxygen plasma treatment is applied. However, as another oxidation treatment method, a method of performing heat treatment while flowing oxygen gas, a method of using ozone, or the like may be used.

  In this embodiment, in S505, the buffer film 6 is formed without adding an impurity. For example, while the impurity is added so that the concentration becomes 1/10 of the impurity concentration in the contact film 5, an amorphous state is added. A silicon film may be formed. Even with such a buffer film 6, compared to the case where the contact film 5 is directly oxidized, the parasitic resistance of the current path between the drain electrode 9 and the semiconductor layer 4 is less likely to increase, and the on-characteristics of the TFT 104. Reduction is suppressed.

  Thereafter, as shown in FIG. 4D, the shape of the semiconductor layer 4, the contact film 5 and the silicon oxide film 7 is processed collectively (S507), and further, the drain electrode 9 and the source electrode 10 are formed (S508). .

  In S507, a photolithography process is performed, and the semiconductor layer 4, the contact film 5, the buffer film 6, and the silicon oxide film 7 are subjected to island patterning using a dry etching method, so that these shapes are collectively processed.

  In the electrode forming step of S508, a laminate composed of a copper alloy layer and a pure copper layer is formed in this order by sputtering to a thickness of about 50 nm and 300 nm, respectively. Thereafter, through a photolithography process, the drain electrode 9 and the source electrode 10 are formed by patterning by a wet etching method. Further, using the photoresist used for forming the drain electrode 9 and the source electrode 10 as they are, the contact film 5, the buffer film 6 and the silicon oxide film 7 on the channel of the semiconductor layer 4 are removed by a dry etching method. Remove the photoresist. As an element added to the copper alloy, for example, one or more elements such as Mn, Mg, Ni, Zn, Si, Al, Fe, Ti, Co, Zr, and Hf are added, and the addition amount is 0.5 to 10 atomic%. preferable. Further, in the present embodiment, the drain electrode 9 and the source electrode 10 are configured by stacking a copper alloy layer and a pure copper layer, but may be a single layer of copper alloy. As an additive element in that case, for example, Mg and Zn are preferable.

  Then, as shown in FIG. 4E, the protective film 11 is formed (S509). This protective film 11 is formed by forming a silicon nitride film of about 500 nm by plasma CVD. The protective film forming step of S509 is also a step in which the TFT substrate 101 is subjected to heat treatment because the film forming temperature of the protective film 11 is 200 ° C. or higher. Through such a heat treatment step, Cu atoms and additive elements in the Cu alloy film under the drain electrode 9 and the source electrode 10 are deposited on the silicon oxide film 7 side. Cu atoms and additive elements deposited on the silicon oxide film 7 react with the buffer film 6 and the silicon oxide film 7 on the contact film 5 formed in advance, and have excellent adhesion and diffusion barrier properties, and a low resistance oxide film. 8 self-form.

  Thereafter, as shown in FIG. 4F, pixel electrodes are formed (S510). In S510, first, the protective film 11 is subjected to a photolithography process to open a contact hole, and then a transparent conductive film such as an ITO (Indium Tin Oxide) film is formed to a thickness of about 150 nm by a sputtering method. The pixel electrode 105 is formed by performing a lithography process and patterning. In this manner, the thin film transistor for the liquid crystal display device in Embodiment 1 can be manufactured.

  Hereinafter, the self-formed oxide film 8 will be described. FIG. 6 is a graph showing the distribution of impurity element concentration and oxygen atom concentration in the oxide film 8 in this embodiment. The horizontal axis in FIG. 6 indicates the position in the depth direction of the oxide film 8 and the like, and the vertical axis indicates the concentration. In addition, the figure also shows the concentration in the vicinity of the boundary between the oxide film 8 and the contact film 5 and in the vicinity of the boundary between the oxide film 8 and the drain electrode 9 and the like. In FIG. 6, the oxygen atom concentration in this embodiment is shown by a two-dot chain line, and the impurity concentration is shown by a solid line. In the case of the conventional technique (except that the buffer film 6 is not formed, the oxygen atom concentration is produced by the same process as this embodiment) The impurity concentration in the case of ()) is indicated by a dotted line. As shown in FIG. 6, in this embodiment, oxygen atoms are distributed with a peak in a normal distribution between the drain electrode 9 and the like and the contact film 5. Further, the concentration of the impurity element in the oxide film 8 is lower than the concentration of the impurity element in the contact film 5, and the concentration of the impurity element is distributed so as to decrease as the distance from the contact film 5 increases. The concentration of the element in the contact film 5, the oxide film 8, the drain electrode 9, and the like can be measured using SIMS (Secondary Ionization Mass Spectrometer) analysis, and can be measured by so-called BackSide-SIMS analysis.

Specifically, the oxide film 8 is a film in which oxygen atoms of a predetermined concentration or more are distributed. In this embodiment, a region having an oxygen atom concentration of 1.0 × 10 ²² atoms / cm ³ or more is oxidized. The material film 8 is a film having a thickness of about 5 nm. Compared with the case where the buffer film 6 is not formed, the concentration of the impurity element in the oxide film 8 is lower in the TFT 104 of the present embodiment provided with the buffer film 6. The impurity element concentration at the boundary between the oxide film 8 and the contact film 5 (position where the oxygen atom concentration of a predetermined concentration is detected) is 1.0 × 10 ²⁰ / cm ^{3 as} shown in FIG. The impurity element concentration at the boundary between the oxide film 8 and the drain electrode 9 is 1.0 × 10 ¹⁹ atoms / cm ³ or less as shown in FIG.

  Since the oxide film 8 is formed through a process in which the buffer film 6 is subjected to oxygen treatment, it contains at least silicon and oxygen, and the impurity concentration is lower than that of the contact film 5. As a result, the parasitic resistance of the current path between the drain electrode 9 and the like and the semiconductor layer 4 is unlikely to increase, and the on-characteristic deterioration of the TFT 104 is suppressed. Further, the oxide film 8 is formed through the heat treatment process as described above, so that it contains an additive element of Cu alloy and Cu atoms in addition to silicon oxide, and adhesion and diffusion. The film has excellent barrier properties and low resistance.

Further, the oxide film 8 has a peak of oxygen atom concentration as shown in FIG. In the position where the maximum value of the oxygen atom concentration is detected in the oxide film 8, the parasitic resistance can be hardly increased by making the impurity concentration less than 1.0 × 10 ²⁰ atoms / cm ^3. And less than 1.0 × 10 ¹⁹ pieces / cm ³ , and more preferably less than 1.0 × 10 ¹⁸ pieces / cm ³ . Further, as shown in FIG. 6, the concentration of the impurity element decreases on the contact film 5 side from the position where the maximum value of the oxygen atom concentration is detected. Specifically, the maximum value of the oxygen atom concentration is detected. At the position where the contact is made, the impurity concentration is 1/10 or less of the impurity concentration in the contact film 5 (the average impurity concentration in the contact film 5). The impurity concentration at a position oxygen atom concentration on the side of such a drain electrode 9 is 1.0 × ^{10 22} atoms / cm ³ is an oxygen atom concentration is 1.0 × ^{10 22} pieces on the side of the contact layer 5 / cm The impurity concentration may be set to 1/100 or less of the impurity concentration at a position of ³ or less, and by doing so, it is difficult to increase the parasitic resistance.

Note that the buffer film 6 provided in S505 is preferably provided with a thickness of 1 nm to 10 nm. Thus, the impurity concentration at the boundary between the drain electrode 9 or the source electrode 10 and the oxide film 8 (in this embodiment, the position where the oxygen atom concentration is 1.0 × 10 ²² atoms / cm ³ ) is 1 0.0 × 10 ¹⁹ pieces / cm ³ or less. Further, when the thickness of the buffer film 6 is less than 1 nm, the film thickness variation becomes large in the substrate surface, which may make it difficult to obtain uniform transistor characteristics. In addition, the contact film 5 is oxidized. This is undesirable because the parasitic resistance is likely to increase. When the thickness of the buffer film 6 is 10 nm or more, the buffer film 6 that remains without being modified into the low-resistance oxide film 8 acts as a high-resistance film, and the on-characteristics of the TFT deteriorates, degrading the display quality. Therefore, it is not desirable.

When the thickness of the buffer film 6 is 1 nm, the concentration of the impurity element contained in the oxide film 8 is the boundary with the drain electrode 9 or the source electrode 10 (the oxygen atom concentration is 1.0 × 10 ²² atoms / cm ³ ), approximately 1.0 × 10 ¹⁹ pieces / cm ³ . Therefore, if the thickness of the buffer film 6 is 1 nm or more and 10 nm or less, the concentration of the impurity element contained in the oxide film 8 is 1.0 × 10 ¹⁹ at the boundary with the drain electrode 9 or the source electrode 10. / Cm ³ or less. On the other hand, the concentration of the impurity element contained in the contact film 5 needs to be 1.0 × 10 ²⁰ pieces / cm ³ or more at the boundary with the oxide film 8. This is because when the impurity element concentration is 1.0 × 10 ²⁰ atoms / cm ³ or less, the on characteristics and the off characteristics of the TFT 104 are deteriorated.

Note that the oxide film 8 is preferably a film in which oxygen atoms are distributed at 1.0 × 10 ²² atoms / cm ³ or more as in this embodiment, from the viewpoint of adhesion with the drain electrode 9 and the like.

  In the TFT 104 of this embodiment, it is possible to prevent oxidation of the impurity element in the contact film 5 from the oxidation treatment by temporarily forming the buffer film 6 having an impurity concentration lower than that of the contact film 5. As a result, it is possible to apply the Cu wiring to the drain electrode 9 and the like while suppressing the deterioration of the ON characteristics. Further, by using this TFT in a liquid crystal display device, it is possible to further increase the size, improve the image quality, and reduce the manufacturing cost.

  In this embodiment, a silicon nitride film (SiNx) is used for the gate insulating film 3, but a silicon oxide film (SiOx) may be used, or a laminated film of these may be used. Further, although a hydrogenated amorphous silicon film is used for the semiconductor layer 4, microcrystalline silicon or polycrystalline silicon may be used, or a laminated film of these may be used. Furthermore, as the contact film 5, a film formed by adding impurities to microcrystalline silicon is also applicable.

  In addition, although the embodiment which employ | adopted the liquid crystal display device was demonstrated above, the display device which concerns on this invention may be a liquid crystal display device of a horizontal electric field system including the IPS type, or a liquid crystal of a vertical electric field system It may be a display device, an organic EL display device, or another display device other than these. In addition, it cannot be overemphasized that embodiment of this invention is not restricted to said embodiment.

  2 gate electrode, 3 gate insulating film, 4 semiconductor layer, 5 contact film, 6 buffer film, 7 silicon oxide film, 8 oxide film, 9 drain electrode, 10 source electrode, 11 protective film, 100 substrate, 101 TFT substrate, 102 scanning line, 103 signal line, 104 TFT, 105 pixel electrode, 106 storage capacitor, 111 light source, 112 polarizing plate, 113 insulating film, 114 alignment film, 115 liquid crystal layer, 116 spacer, 117 common electrode, 118 color filter, 119 Black matrix, 120 color filter substrate, 121 polarizing film.

Claims (1)

A method of manufacturing a display device having a thin film transistor,
Forming a semiconductor layer;
An electrode forming step of forming a source electrode and a drain electrode having a copper alloy layer containing copper and at least one additional element; and
Forming a contact film for electrically connecting each of the source electrode and the drain electrode and the semiconductor layer;
Forming a silicon oxide film containing silicon and oxygen between each of the source electrode and the drain electrode and the contact film,
In the step of forming the contact film,
A silicon film doped with impurities is formed,
The step of forming the silicon oxide film includes
Forming a silicon film having a lower impurity concentration than the silicon film as a buffer film;
Performing an oxidation treatment on the buffer film,
A manufacturing method of a display device characterized by the above.

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